zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Family_15 CPB Initialization |
| 6 | * |
| 7 | * Enables core performance boost. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU/F15/TN |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ****************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 20 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 31 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | ****************************************************************************** |
| 43 | */ |
| 44 | |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | #include "AGESA.h" |
| 50 | #include "amdlib.h" |
| 51 | #include "GeneralServices.h" |
| 52 | #include "cpuFamilyTranslation.h" |
| 53 | #include "cpuF15PowerMgmt.h" |
| 54 | #include "cpuF15TnPowerMgmt.h" |
| 55 | #include "cpuFeatures.h" |
| 56 | #include "cpuCpb.h" |
| 57 | #include "Filecode.h" |
| 58 | CODE_GROUP (G3_DXE) |
| 59 | RDATA_GROUP (G3_DXE) |
| 60 | |
| 61 | #define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE |
| 62 | |
| 63 | /*---------------------------------------------------------------------------------------- |
| 64 | * D E F I N I T I O N S A N D M A C R O S |
| 65 | *---------------------------------------------------------------------------------------- |
| 66 | */ |
| 67 | |
| 68 | /*---------------------------------------------------------------------------------------- |
| 69 | * T Y P E D E F S A N D S T R U C T U R E S |
| 70 | *---------------------------------------------------------------------------------------- |
| 71 | */ |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | /*---------------------------------------------------------------------------------------- |
| 79 | * E X P O R T E D F U N C T I O N S |
| 80 | *---------------------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | /*---------------------------------------------------------------------------------------*/ |
| 84 | /** |
| 85 | * BSC entry point for checking whether or not CPB is supported. |
| 86 | * |
| 87 | * @param[in] CpbServices The current CPU's family services. |
| 88 | * @param[in] PlatformConfig Contains the runtime modifiable feature input data. |
| 89 | * @param[in] Socket Zero based socket number to check. |
| 90 | * @param[in] StdHeader Config handle for library and services. |
| 91 | * |
| 92 | * @retval TRUE CPB is supported. |
| 93 | * @retval FALSE CPB is not supported. |
| 94 | * |
| 95 | */ |
| 96 | BOOLEAN |
| 97 | STATIC |
| 98 | F15TnIsCpbSupported ( |
| 99 | IN CPB_FAMILY_SERVICES *CpbServices, |
| 100 | IN PLATFORM_CONFIGURATION *PlatformConfig, |
| 101 | IN UINT32 Socket, |
| 102 | IN AMD_CONFIG_PARAMS *StdHeader |
| 103 | ) |
| 104 | { |
| 105 | CPB_CTRL_REGISTER CpbControl; |
| 106 | PCI_ADDR PciAddress; |
| 107 | |
| 108 | PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; |
| 109 | LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); |
| 110 | return (BOOLEAN) (CpbControl.NumBoostStates != 0); |
| 111 | } |
| 112 | |
| 113 | |
| 114 | /*---------------------------------------------------------------------------------------*/ |
| 115 | /** |
Peter Lemenkov | 5797b2e | 2018-10-19 16:57:27 +0200 | [diff] [blame] | 116 | * BSC entry point for enabling Core Performance Boost. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 117 | * |
| 118 | * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. |
| 119 | * |
| 120 | * @param[in] CpbServices The current CPU's family services. |
| 121 | * @param[in] PlatformConfig Contains the runtime modifiable feature input data. |
| 122 | * @param[in] EntryPoint Current CPU feature dispatch point. |
| 123 | * @param[in] Socket Zero based socket number to check. |
| 124 | * @param[in] StdHeader Config handle for library and services. |
| 125 | * |
| 126 | * @retval AGESA_SUCCESS Always succeeds. |
| 127 | * |
| 128 | */ |
| 129 | AGESA_STATUS |
| 130 | STATIC |
| 131 | F15TnInitializeCpb ( |
| 132 | IN CPB_FAMILY_SERVICES *CpbServices, |
| 133 | IN PLATFORM_CONFIGURATION *PlatformConfig, |
| 134 | IN UINT64 EntryPoint, |
| 135 | IN UINT32 Socket, |
| 136 | IN AMD_CONFIG_PARAMS *StdHeader |
| 137 | ) |
| 138 | { |
| 139 | CPB_CTRL_REGISTER CpbControl; |
| 140 | PCI_ADDR PciAddress; |
| 141 | F15_PSTATE_MSR PstateMsrData; |
| 142 | UINT32 Pbx; |
| 143 | |
| 144 | if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { |
| 145 | PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; |
| 146 | LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); |
| 147 | if (CpbControl.NumBoostStates == 0) { |
| 148 | CpbControl.ApmMasterEn = 0; |
| 149 | } else { |
| 150 | CpbControl.ApmMasterEn = 1; |
| 151 | } |
| 152 | LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); |
| 153 | |
| 154 | } else if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { |
| 155 | PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; |
| 156 | LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); |
| 157 | if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) { |
| 158 | // If any boosted P-state is still enabled, set BoostSrc = 1. |
| 159 | for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) { |
| 160 | LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader); |
| 161 | if (PstateMsrData.PsEnable == 1) { |
| 162 | CpbControl.BoostSrc = 1; |
| 163 | LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); |
| 164 | break; |
| 165 | } |
| 166 | } |
| 167 | } |
| 168 | } |
| 169 | return AGESA_SUCCESS; |
| 170 | } |
| 171 | |
| 172 | CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport = |
| 173 | { |
| 174 | 0, |
| 175 | F15TnIsCpbSupported, |
| 176 | F15TnInitializeCpb |
| 177 | }; |