zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Platform Specific Memory Configuration |
| 6 | * |
| 7 | * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: OPTION |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 19 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 30 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | ****************************************************************************** |
| 42 | */ |
| 43 | |
| 44 | #ifndef _PLATFORM_MEMORY_CONFIGURATION_H_ |
| 45 | #define _PLATFORM_MEMORY_CONFIGURATION_H_ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #ifndef PSO_ENTRY |
| 52 | #define PSO_ENTRY UINT8 |
| 53 | #endif |
| 54 | |
| 55 | /*---------------------------------------------------------------------------------------- |
| 56 | * D E F I N I T I O N S A N D M A C R O S |
| 57 | *---------------------------------------------------------------------------------------- |
| 58 | */ |
| 59 | /*---------------------------------------------------------------------------------------- |
| 60 | * T Y P E D E F S, S T R U C T U R E S, E N U M S |
| 61 | *---------------------------------------------------------------------------------------- |
| 62 | */ |
| 63 | /*---------------------------------------------------------------------------------------- |
| 64 | * PLATFORM SPECIFIC MEMORY DEFINITIONS |
| 65 | *---------------------------------------------------------------------------------------- |
| 66 | */ |
| 67 | /// |
| 68 | /// Memory Speed and DIMM Population Masks |
| 69 | /// |
| 70 | ///< DDR Speed Masks |
| 71 | ///< Specifies the DDR Speed on a memory channel |
| 72 | /// |
| 73 | #define ANY_SPEED 0xFFFFFFFFul |
| 74 | #define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66)) |
| 75 | #define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66)) |
| 76 | #define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66)) |
| 77 | #define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66)) |
| 78 | #define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66)) |
| 79 | #define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66)) |
| 80 | #define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66)) |
| 81 | #define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66)) |
| 82 | #define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66)) |
| 83 | #define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66)) |
| 84 | /// |
| 85 | ///< DIMM POPULATION MASKS |
| 86 | ///< Specifies the DIMM Population on a channel (can be added together to specify configuration). |
| 87 | ///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1 |
| 88 | ///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1 |
| 89 | /// |
| 90 | #define ANY_ 0xFF ///< Any dimm configuration the current channel |
| 91 | #define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel |
| 92 | #define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel |
| 93 | #define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel |
| 94 | #define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel |
| 95 | #define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel |
| 96 | #define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel |
| 97 | #define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel |
| 98 | #define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel |
| 99 | #define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel |
| 100 | #define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel |
| 101 | #define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel |
| 102 | #define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel |
| 103 | #define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel |
| 104 | #define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel |
| 105 | #define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel |
| 106 | #define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel |
| 107 | #define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel |
| 108 | #define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel |
| 109 | #define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel |
| 110 | #define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel |
| 111 | /// |
| 112 | ///< CS POPULATION MASKS |
| 113 | ///< Specifies the CS Population on a channel (can be added together to specify configuration). |
| 114 | ///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting |
| 115 | /// |
| 116 | #define CS_ANY_ 0xFF ///< Any CS configuration |
| 117 | #define CS0_ 0x01 ///< CS0 bit map mask |
| 118 | #define CS1_ 0x02 ///< CS1 bit map mask |
| 119 | #define CS2_ 0x04 ///< CS2 bit map mask |
| 120 | #define CS3_ 0x08 ///< CS3 bit map mask |
| 121 | #define CS4_ 0x10 ///< CS4 bit map mask |
| 122 | #define CS5_ 0x20 ///< CS5 bit map mask |
| 123 | #define CS6_ 0x40 ///< CS6 bit map mask |
| 124 | #define CS7_ 0x80 ///< CS7 bit map mask |
| 125 | /// |
| 126 | ///< Number of Dimms on the current channel |
| 127 | ///< This is a mask used to indicate the number of dimms in a channel |
| 128 | ///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms) |
| 129 | /// |
| 130 | #define ANY_NUM 0xFF ///< Any number of Dimms |
| 131 | #define NO_DIMM 0x00 ///< No Dimms present |
| 132 | #define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel |
| 133 | #define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel |
| 134 | #define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel |
| 135 | #define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel |
| 136 | |
| 137 | /// |
| 138 | ///< DIMM VOLTAGE MASKS |
| 139 | /// |
| 140 | #define VOLT_ANY_ 0xFF ///< Any voltage configuration |
| 141 | #define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask |
| 142 | #define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask |
| 143 | #define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask |
| 144 | |
| 145 | // |
| 146 | // < Not applicable |
| 147 | // |
| 148 | #define NA_ 0 ///< Not applicable |
| 149 | |
| 150 | /*---------------------------------------------------------------------------------------- |
| 151 | * |
| 152 | * Platform Specific Override Definitions for Socket, Channel and Dimm |
| 153 | * This indicates where a platform override will be applied. |
| 154 | * |
| 155 | *---------------------------------------------------------------------------------------- |
| 156 | */ |
| 157 | /// |
| 158 | ///< SOCKET MASKS |
| 159 | ///< Indicates associated processor sockets to apply override settings |
| 160 | /// |
| 161 | #define ANY_SOCKET 0xFF ///< Apply to all sockets |
| 162 | #define SOCKET0 0x01 ///< Apply to socket 0 |
| 163 | #define SOCKET1 0x02 ///< Apply to socket 1 |
| 164 | #define SOCKET2 0x04 ///< Apply to socket 2 |
| 165 | #define SOCKET3 0x08 ///< Apply to socket 3 |
| 166 | #define SOCKET4 0x10 ///< Apply to socket 4 |
| 167 | #define SOCKET5 0x20 ///< Apply to socket 5 |
| 168 | #define SOCKET6 0x40 ///< Apply to socket 6 |
| 169 | #define SOCKET7 0x80 ///< Apply to socket 7 |
| 170 | /// |
| 171 | ///< CHANNEL MASKS |
| 172 | ///< Indicates Memory channels where override should be applied |
| 173 | /// |
| 174 | #define ANY_CHANNEL 0xFF ///< Apply to all Memory channels |
| 175 | #define CHANNEL_A 0x01 ///< Apply to Channel A |
| 176 | #define CHANNEL_B 0x02 ///< Apply to Channel B |
| 177 | #define CHANNEL_C 0x04 ///< Apply to Channel C |
| 178 | #define CHANNEL_D 0x08 ///< Apply to Channel D |
| 179 | /// |
| 180 | /// DIMM MASKS |
| 181 | /// Indicates Dimm Slots where override should be applied |
| 182 | /// |
| 183 | #define ALL_DIMMS 0xFF ///< Apply to all dimm slots |
| 184 | #define DIMM0 0x01 ///< Apply to Dimm Slot 0 |
| 185 | #define DIMM1 0x02 ///< Apply to Dimm Slot 1 |
| 186 | #define DIMM2 0x04 ///< Apply to Dimm Slot 2 |
| 187 | #define DIMM3 0x08 ///< Apply to Dimm Slot 3 |
| 188 | /// |
| 189 | /// REGISTER ACCESS MASKS |
| 190 | /// Not supported as an at this time |
| 191 | /// |
| 192 | #define ACCESS_NB0 0x0 |
| 193 | #define ACCESS_NB1 0x1 |
| 194 | #define ACCESS_NB2 0x2 |
| 195 | #define ACCESS_NB3 0x3 |
| 196 | #define ACCESS_NB4 0x4 |
| 197 | #define ACCESS_PHY 0x5 |
| 198 | #define ACCESS_DCT_XT 0x6 |
| 199 | /*---------------------------------------------------------------------------------------- |
| 200 | * |
| 201 | * Platform Specific Overriding Table Definitions |
| 202 | * |
| 203 | *---------------------------------------------------------------------------------------- |
| 204 | */ |
| 205 | |
| 206 | #define PSO_END 0 ///< Table End |
| 207 | #define PSO_CKE_TRI 1 ///< CKE Tristate Map |
| 208 | #define PSO_ODT_TRI 2 ///< ODT Tristate Map |
| 209 | #define PSO_CS_TRI 3 ///< CS Tristate Map |
| 210 | #define PSO_MAX_DIMMS 4 ///< Max Dimms per channel |
| 211 | #define PSO_CLK_SPEED 5 ///< Clock Speed |
| 212 | #define PSO_DIMM_TYPE 6 ///< Dimm Type |
| 213 | #define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map |
| 214 | #define PSO_MAX_CHNLS 8 ///< Max Channels per Socket |
| 215 | #define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed |
| 216 | #define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel |
| 217 | #define PSO_MEM_TECH 11 ///< Channel Memory Type |
| 218 | #define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay |
| 219 | #define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed |
| 220 | #define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs |
| 221 | #define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type |
| 222 | #define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V |
| 223 | #define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width |
| 224 | #define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent |
| 225 | #define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel |
| 226 | #define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override |
| 227 | |
| 228 | /*---------------------------------- |
| 229 | * CONDITIONAL PSO SPECIFIC ENTRIES |
| 230 | *---------------------------------*/ |
| 231 | // Condition Types |
| 232 | #define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types |
| 233 | #define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block |
| 234 | #define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected |
| 235 | #define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel |
| 236 | #define PSO_CONDITION_REG 103 // Reserved |
| 237 | #define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types |
| 238 | // Action Types |
| 239 | #define PSO_ACTION_MIN 120 ///< Start of Action Entry Types |
| 240 | #define PSO_ACTION_ODT 120 ///< ODT values to override |
| 241 | #define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override |
| 242 | #define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override |
| 243 | #define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override |
| 244 | #define PSO_ACTION_REG 124 // Reserved |
| 245 | #define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration |
| 246 | #define PSO_ACTION_MAX 125 ///< End of Action Entry Types |
| 247 | #define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types |
| 248 | |
| 249 | /*---------------------------------- |
| 250 | * TABLE DRIVEN PSO SPECIFIC ENTRIES |
| 251 | *---------------------------------*/ |
| 252 | // Condition descriptor |
| 253 | #define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor |
| 254 | |
| 255 | // Overriding entry types |
| 256 | #define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types |
| 257 | #define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit |
| 258 | #define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom |
| 259 | #define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr |
| 260 | #define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns |
| 261 | #define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values |
| 262 | #define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values |
| 263 | #define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode |
| 264 | #define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL] |
| 265 | #define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR] |
| 266 | #define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT] |
| 267 | #define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed] |
| 268 | #define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT |
| 269 | #define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type |
| 270 | #define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types |
| 271 | |
| 272 | /*---------------------------------------------------------------------------------------- |
| 273 | * CONDITIONAL OVERRIDE TABLE MACROS |
| 274 | *---------------------------------------------------------------------------------------- |
| 275 | */ |
| 276 | #define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \ |
| 277 | PSO_CPU_FAMILY_TO_OVERRIDE, 4, \ |
| 278 | ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF) |
| 279 | |
| 280 | #define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ |
| 281 | PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \ |
| 282 | , Bit7Map |
| 283 | |
| 284 | #define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \ |
| 285 | PSO_CKE_TRI, 5, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map |
| 286 | |
| 287 | #define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ |
| 288 | PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map |
| 289 | |
| 290 | #define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ |
| 291 | PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map |
| 292 | |
| 293 | #define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \ |
| 294 | PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel |
| 295 | |
| 296 | #define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \ |
| 297 | PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel |
| 298 | |
| 299 | #define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ |
| 300 | PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel |
| 301 | |
| 302 | #define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \ |
| 303 | PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket |
| 304 | |
| 305 | #define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \ |
| 306 | PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \ |
| 307 | BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24) |
| 308 | |
| 309 | #define DRAM_TECHNOLOGY(SocketID, MemTechType) \ |
| 310 | PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24) |
| 311 | |
| 312 | #define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ |
| 313 | Byte6Seed, Byte7Seed, ByteEccSeed) \ |
| 314 | PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ |
| 315 | Byte6Seed, Byte7Seed, ByteEccSeed |
| 316 | |
| 317 | #define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ |
| 318 | Byte6Seed, Byte7Seed, ByteEccSeed) \ |
| 319 | PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \ |
| 320 | Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \ |
| 321 | Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8) |
| 322 | |
| 323 | #define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \ |
| 324 | PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE |
| 325 | |
| 326 | #define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \ |
| 327 | PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE |
| 328 | |
| 329 | #define LVDIMM_FORCE_VOLT1_5_FOR_D0 \ |
| 330 | PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE |
| 331 | |
| 332 | #define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \ |
| 333 | PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth |
| 334 | |
| 335 | #define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \ |
| 336 | PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy |
| 337 | |
| 338 | /*---------------------------------------------------------------------------------------- |
| 339 | * CONDITIONAL OVERRIDE TABLE MACROS |
| 340 | *---------------------------------------------------------------------------------------- |
| 341 | */ |
| 342 | #define CONDITION_AND \ |
| 343 | PSO_CONDITION_AND, 0 |
| 344 | |
| 345 | #define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \ |
| 346 | PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk |
| 347 | |
| 348 | #define COND_SPD(Byte, Mask, Value) \ |
| 349 | PSO_CONDITION_SPD, 3, Byte, Mask, Value |
| 350 | |
| 351 | #define COND_REG(Access, Offset, Mask, Value) \ |
| 352 | PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \ |
| 353 | ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \ |
| 354 | ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF) |
| 355 | |
| 356 | #define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \ |
| 357 | PSO_ACTION_ODT, 9, \ |
| 358 | ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \ |
| 359 | Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt |
| 360 | |
| 361 | #define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \ |
| 362 | PSO_ACTION_ADDRTMG, 10, \ |
| 363 | ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ |
| 364 | ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ |
| 365 | (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF) |
| 366 | |
| 367 | #define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \ |
| 368 | PSO_ACTION_ODCCONTROL, 10, \ |
| 369 | ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ |
| 370 | ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ |
| 371 | (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF) |
| 372 | |
| 373 | #define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \ |
| 374 | PSO_ACTION_SLEWRATE, 10, \ |
| 375 | ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ |
| 376 | ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ |
| 377 | (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF) |
| 378 | |
| 379 | #define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \ |
| 380 | PSO_ACTION_SPEEDLIMIT, 9, \ |
| 381 | ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \ |
| 382 | (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \ |
| 383 | (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \ |
| 384 | (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF) |
| 385 | |
| 386 | /*---------------------------------------------------------------------------------------- |
| 387 | * END OF CONDITIONAL OVERRIDE TABLE MACROS |
| 388 | *---------------------------------------------------------------------------------------- |
| 389 | */ |
| 390 | /*---------------------------------------------------------------------------------------- |
| 391 | * TABLE DRIVEN OVERRIDE MACROS |
| 392 | *---------------------------------------------------------------------------------------- |
| 393 | */ |
| 394 | /// Configuration sub-descriptors |
| 395 | typedef enum { |
| 396 | CONFIG_GENERAL, ///< CONFIG_GENERAL |
| 397 | CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT |
| 398 | CONFIG_RC2IBT, ///< CONFIG_RC2IBT |
| 399 | CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE |
| 400 | } Config_Type; |
| 401 | |
| 402 | // ==================== |
| 403 | // Configuration Macros |
| 404 | // ==================== |
| 405 | #define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \ |
| 406 | PSO_TBLDRV_CONFIG, 9, \ |
| 407 | CONFIG_GENERAL, \ |
| 408 | DimmPerCH, DimmVolt, \ |
| 409 | ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ |
| 410 | ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF) |
| 411 | |
| 412 | #define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \ |
| 413 | PSO_TBLDRV_CONFIG, 7, \ |
| 414 | CONFIG_SPEEDLIMIT, \ |
| 415 | DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm |
| 416 | |
| 417 | #define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \ |
| 418 | PSO_TBLDRV_CONFIG, 10, \ |
| 419 | CONFIG_RC2IBT, \ |
| 420 | DimmPerCH, DimmVolt, \ |
| 421 | ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ |
| 422 | ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ |
| 423 | NumOfReg |
| 424 | |
| 425 | //================== |
| 426 | // Overriding Macros |
| 427 | //================== |
| 428 | #define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \ |
| 429 | PSO_TBLDRV_SPEEDLIMIT, 6, \ |
| 430 | (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \ |
| 431 | (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \ |
| 432 | (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF) |
| 433 | |
| 434 | #define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \ |
| 435 | PSO_TBLDRV_ODT_RTTNOM, 2, \ |
| 436 | TgtCS, RttNom |
| 437 | |
| 438 | #define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \ |
| 439 | PSO_TBLDRV_ODT_RTTWR, 2, \ |
| 440 | TgtCS, RttWr |
| 441 | |
| 442 | #define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \ |
| 443 | PSO_TBLDRV_ODTPATTERN, 16, \ |
| 444 | ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \ |
| 445 | ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \ |
| 446 | ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \ |
| 447 | ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF) |
| 448 | |
| 449 | #define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \ |
| 450 | PSO_TBLDRV_ADDRTMG, 4, \ |
| 451 | ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF) |
| 452 | |
| 453 | #define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \ |
| 454 | PSO_TBLDRV_ODCCTRL, 4, \ |
| 455 | ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF) |
| 456 | |
| 457 | #define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \ |
| 458 | PSO_TBLDRV_SLOWACCMODE, 1, \ |
| 459 | SlowAccMode |
| 460 | |
| 461 | #define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \ |
| 462 | PSO_TBLDRV_RC2_IBT, 2, \ |
| 463 | TgtDimm, IBT |
| 464 | |
| 465 | #define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \ |
| 466 | PSO_TBLDRV_CONFIG, 1, \ |
| 467 | CONFIG_DONT_CARE, \ |
| 468 | PSO_TBLDRV_MR0_CL, 3, \ |
| 469 | RegValOfTcl, MR0CL13, MR0CL0 |
| 470 | |
| 471 | #define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \ |
| 472 | PSO_TBLDRV_CONFIG, 1, \ |
| 473 | CONFIG_DONT_CARE, \ |
| 474 | PSO_TBLDRV_MR0_WR, 2, \ |
| 475 | RegValOfTwr, MR0WR |
| 476 | |
| 477 | #define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \ |
| 478 | PSO_TBLDRV_CONFIG, 1, \ |
| 479 | CONFIG_DONT_CARE, \ |
| 480 | PSO_TBLDRV_RC10_OPSPEED, 5, \ |
| 481 | ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ |
| 482 | MR10OPSPEED |
| 483 | |
| 484 | #define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \ |
| 485 | PSO_TBLDRV_LRDIMM_IBT, 4, \ |
| 486 | F0RC8, F1RC0, F1RC1, F1RC2 |
| 487 | |
| 488 | |
| 489 | //============================ |
| 490 | // Macros for removing entries |
| 491 | //============================ |
| 492 | #define INVALID_CONFIG_FLAG 0x8000 |
| 493 | |
| 494 | #define TBLDRV_INVALID_CONFIG \ |
| 495 | PSO_TBLDRV_INVALID_TYPE, 0 |
| 496 | |
| 497 | /*---------------------------------------------------------------------------------------- |
| 498 | * END OF TABLE DRIVEN OVERRIDE MACROS |
| 499 | *---------------------------------------------------------------------------------------- |
| 500 | */ |
| 501 | |
| 502 | #endif // _PLATFORM_MEMORY_CONFIGURATION_H_ |