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zbao7d94cf92012-07-02 14:19:14 +08001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD Multi-socket option API.
6 *
7 * Contains structures and values used to control the multi-socket option code.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: OPTION
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*****************************************************************************
16 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080017 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
18 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +080019 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080020 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +080030 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080031 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +080041 ******************************************************************************
42 */
43
44#ifndef _OPTION_MULTISOCKET_H_
45#define _OPTION_MULTISOCKET_H_
46
47/*----------------------------------------------------------------------------------------
48 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
49 *----------------------------------------------------------------------------------------
50 */
51
52/*----------------------------------------------------------------------------------------
53 * D E F I N I T I O N S A N D M A C R O S
54 *----------------------------------------------------------------------------------------
55 */
56
57
58/*----------------------------------------------------------------------------------------
59 * T Y P E D E F S, S T R U C T U R E S, E N U M S
60 *----------------------------------------------------------------------------------------
61 */
62
63/**
64 * This function loops through all possible socket locations, gathering the number
65 * of power management steps each populated socket requires, and returns the
66 * highest number.
67 *
68 * @param[out] NumSystemSteps Maximum number of system steps required
69 * @param[in] StdHeader Config handle for library and services
70 *
71 */
72typedef VOID OPTION_MULTISOCKET_PM_STEPS (
73 OUT UINT8 *NumSystemSteps,
74 IN AMD_CONFIG_PARAMS *StdHeader
75 );
76
77/**
78 * This function loops through all possible socket locations, starting core 0 of
79 * each populated socket to perform the passed in AP_TASK. After starting all
80 * other core 0s, the BSC will perform the AP_TASK as well. This must be run by
81 * the system BSC only.
82 *
83 * @param[in] TaskPtr Function descriptor
84 * @param[in] StdHeader Config handle for library and services
85 * @param[in] ConfigParams AMD entry point's CPU parameter structure
86 *
87 * @return The most severe error code from AP_TASK
88 *
89 */
90typedef AGESA_STATUS OPTION_MULTISOCKET_PM_CORE0_TASK (
91 IN VOID *TaskPtr,
92 IN AMD_CONFIG_PARAMS *StdHeader,
93 IN VOID *ConfigParams
94 );
95
96/**
97 * This function loops through all possible socket locations, comparing the
98 * maximum NB frequencies to determine the slowest. This function also
99 * determines if all coherent NB frequencies are equivalent.
100 *
101 * @param[in] NbPstate NB P-state number to check (0 = fastest)
102 * @param[in] PlatformConfig Platform profile/build option config structure.
103 * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
104 * @param[out] SystemNbCofDenominator NB frequency denominator for the system
105 * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
106 * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
107 * @param[in] StdHeader Config handle for library and services
108 *
109 * @retval TRUE At least one processor has NbPstate enabled.
110 * @retval FALSE NbPstate is disabled on all CPUs
111 */
112typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
113 IN UINT32 NbPstate,
114 IN PLATFORM_CONFIGURATION *PlatformConfig,
115 OUT UINT32 *SystemNbCofNumerator,
116 OUT UINT32 *SystemNbCofDenominator,
117 OUT BOOLEAN *SystemNbCofsMatch,
118 OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
119 IN AMD_CONFIG_PARAMS *StdHeader
120 );
121
122/**
123 * This function loops through all possible socket locations, checking whether
124 * any populated sockets require NB COF VID programming.
125 *
126 * @param[in] StdHeader Config handle for library and services
127 *
128 */
129typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
130 IN AMD_CONFIG_PARAMS *StdHeader
131 );
132
133/**
134 * This function loops through all possible socket locations, collecting any
135 * power management initialization errors that may have occurred. These errors
136 * are transferred from the core 0s of the socket in which the errors occurred
137 * to the BSC's heap. The BSC's heap is then searched for the most severe error
138 * that occurred, and returns it. This function must be called by the BSC only.
139 *
140 * @param[in] StdHeader Config handle for library and services
141 *
142 */
143typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
144 IN AMD_CONFIG_PARAMS *StdHeader
145 );
146
147/**
148 * This function loops through all possible socket locations and Nb Pstates,
149 * comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
150 * the system.
151 *
152 * @param[in] PlatformConfig Platform profile/build option config structure.
153 * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz
154 * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz
155 * @param[in] StdHeader Config handle for library and services
156 */
157typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
158 IN PLATFORM_CONFIGURATION *PlatformConfig,
159 OUT UINT32 *MinSysNbFreq,
160 OUT UINT32 *MinP0NbFreq,
161 IN AMD_CONFIG_PARAMS *StdHeader
162 );
163
164/**
165 * This function returns the current running core's PCI Config Space address.
166 *
167 * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
168 * @param[in] StdHeader Header for library and services.
169 */
170typedef BOOLEAN OPTION_MULTISOCKET_GET_PCI_ADDRESS (
171 OUT PCI_ADDR *PciAddress,
172 IN AMD_CONFIG_PARAMS *StdHeader
173 );
174
175/**
176 * This function writes to all nodes on the executing core's socket.
177 *
178 * @param[in] PciAddress The Function and Register to update
179 * @param[in] Mask The bitwise AND mask to apply to the current register value
180 * @param[in] Data The bitwise OR mask to apply to the current register value
181 * @param[in] StdHeader Header for library and services.
182 *
183 */
184typedef VOID OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI (
185 IN PCI_ADDR *PciAddress,
186 IN UINT32 Mask,
187 IN UINT32 Data,
188 IN AMD_CONFIG_PARAMS *StdHeader
189 );
190
191#define MULTISOCKET_STRUCT_VERSION 0x01
192
193/**
194 * Provide build configuration of cpu multi-socket or single socket support.
195 *
196 */
197typedef struct {
198 UINT16 OptMultiSocketVersion; ///< Table version
199 OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
200 OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
201 OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
202 OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
203 OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
204 OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
205 OPTION_MULTISOCKET_GET_PCI_ADDRESS *GetCurrPciAddr; ///< Method: Get PCI Config Space Address for the current running core.
206 OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI *ModifyCurrSocketPci; ///< Method: Writes to all nodes on the executing core's socket.
207} OPTION_MULTISOCKET_CONFIGURATION;
208
209/*----------------------------------------------------------------------------------------
210 * F U N C T I O N P R O T O T Y P E
211 *----------------------------------------------------------------------------------------
212 */
213
214
215#endif // _OPTION_MULTISOCKET_H_