zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Install of build option: GNB |
| 6 | * |
| 7 | * Contains AMD AGESA install macros and test conditions. Output is the |
| 8 | * defaults tables reflecting the User's build options selection. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: Options |
| 13 | * @e \$Revision: 64464 $ @e \$Date: 2012-01-21 11:28:59 -0600 (Sat, 21 Jan 2012) $ |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 19 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 30 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * |
| 42 | ***************************************************************************/ |
| 43 | |
| 44 | #ifndef _OPTION_GNB_INSTALL_H_ |
| 45 | #define _OPTION_GNB_INSTALL_H_ |
| 46 | |
Alexandru Gagniuc | 986349d | 2014-03-29 16:52:46 -0500 | [diff] [blame] | 47 | #include <Proc/Common/S3SaveState.h> |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 48 | /* This option is designed to be included into the platform solution install |
| 49 | * file. The platform solution install file will define the options status. |
| 50 | * Check to validate the definition |
| 51 | */ |
| 52 | |
| 53 | //--------------------------------------------------------------------------------------------------- |
| 54 | // Family installation |
| 55 | //--------------------------------------------------------------------------------------------------- |
| 56 | |
| 57 | |
| 58 | |
| 59 | #define GNB_TYPE_TN FALSE |
| 60 | #define GNB_TYPE_LN FALSE |
| 61 | #define GNB_TYPE_ON FALSE |
| 62 | |
| 63 | #if (OPTION_FAMILY14H_ON == TRUE) |
| 64 | #undef GNB_TYPE_ON |
| 65 | #define GNB_TYPE_ON TRUE |
| 66 | #endif |
| 67 | |
| 68 | #if (OPTION_FAMILY12H_LN == TRUE) |
| 69 | #undef GNB_TYPE_LN |
| 70 | #define GNB_TYPE_LN TRUE |
| 71 | #endif |
| 72 | |
| 73 | #if (OPTION_FAMILY15H_TN == TRUE) |
| 74 | #undef GNB_TYPE_TN |
| 75 | #define GNB_TYPE_TN TRUE |
| 76 | #endif |
| 77 | |
| 78 | |
| 79 | |
| 80 | #if (GNB_TYPE_TN == TRUE || GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 81 | //--------------------------------------------------------------------------------------------------- |
| 82 | // Service installation |
| 83 | //--------------------------------------------------------------------------------------------------- |
| 84 | |
Alexandru Gagniuc | 986349d | 2014-03-29 16:52:46 -0500 | [diff] [blame] | 85 | #include <Proc/GNB/Common/Gnb.h> |
| 86 | #include <Proc/GNB/Common/GnbPcie.h> |
| 87 | #include <Proc/GNB/Common/GnbGfx.h> |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 88 | |
| 89 | #define SERVICES_POINTER NULL |
| 90 | #if (GNB_TYPE_TN == TRUE) |
Alexandru Gagniuc | 986349d | 2014-03-29 16:52:46 -0500 | [diff] [blame] | 91 | #include <Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h> |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 92 | #endif |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 93 | CONST GNB_SERVICE * CONST ServiceTable = SERVICES_POINTER; |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 94 | |
| 95 | //--------------------------------------------------------------------------------------------------- |
| 96 | // BUILD options |
| 97 | //--------------------------------------------------------------------------------------------------- |
| 98 | |
| 99 | #ifndef CFG_IGFX_AS_PCIE_EP |
| 100 | #define CFG_IGFX_AS_PCIE_EP TRUE |
| 101 | #endif |
| 102 | |
| 103 | #ifndef CFG_LCLK_DEEP_SLEEP_EN |
| 104 | #if (GNB_TYPE_TN == TRUE) |
| 105 | #define CFG_LCLK_DEEP_SLEEP_EN FALSE |
| 106 | #else |
| 107 | #define CFG_LCLK_DEEP_SLEEP_EN TRUE |
| 108 | #endif |
| 109 | #endif |
| 110 | |
| 111 | #ifndef CFG_LCLK_DPM_EN |
| 112 | #define CFG_LCLK_DPM_EN TRUE |
| 113 | #endif |
| 114 | |
| 115 | #ifndef CFG_GMC_POWER_GATING |
| 116 | #if (GNB_TYPE_TN == TRUE) |
| 117 | #define CFG_GMC_POWER_GATING GmcPowerGatingWidthStutter |
| 118 | #else |
| 119 | #define CFG_GMC_POWER_GATING GmcPowerGatingWidthStutter |
| 120 | #endif |
| 121 | #endif |
| 122 | |
| 123 | #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE |
| 124 | #if (GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE) |
| 125 | #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE |
| 126 | #else |
| 127 | #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE |
| 128 | #endif |
| 129 | #endif |
| 130 | |
| 131 | #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE |
| 132 | #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE |
| 133 | #endif |
| 134 | |
| 135 | #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT |
| 136 | #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE |
| 137 | #endif |
| 138 | |
| 139 | #ifndef CFG_GNB_LOAD_REAL_FUSE |
| 140 | #define CFG_GNB_LOAD_REAL_FUSE TRUE |
| 141 | #endif |
| 142 | |
| 143 | #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING |
| 144 | #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) |
| 145 | #endif |
| 146 | |
| 147 | #ifndef CFG_GNB_PCIE_LINK_L0_POOLING |
| 148 | #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) |
| 149 | #endif |
| 150 | |
| 151 | #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME |
| 152 | #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) |
| 153 | #endif |
| 154 | |
| 155 | #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME |
| 156 | #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) |
| 157 | #endif |
| 158 | |
| 159 | #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM |
| 160 | #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM |
| 161 | #else |
| 162 | #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard |
| 163 | #endif |
| 164 | |
| 165 | #ifndef CFG_GNB_FORCE_CABLESAFE_OFF |
| 166 | #define CFG_GNB_FORCE_CABLESAFE_OFF FALSE |
| 167 | #endif |
| 168 | |
| 169 | #ifndef CFG_ORB_CLOCK_GATING_ENABLE |
| 170 | #define CFG_ORB_CLOCK_GATING_ENABLE TRUE |
| 171 | #endif |
| 172 | |
| 173 | #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS |
| 174 | #define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0 |
| 175 | #endif |
| 176 | |
| 177 | #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE |
| 178 | #if (GNB_TYPE_TN == TRUE) |
| 179 | #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE TRUE |
| 180 | #else |
| 181 | #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE |
| 182 | #endif |
| 183 | #endif |
| 184 | |
| 185 | #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE |
| 186 | #if (GNB_TYPE_TN == TRUE) |
| 187 | #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE TRUE |
| 188 | #else |
| 189 | #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE |
| 190 | #endif |
| 191 | #endif |
| 192 | |
| 193 | #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE |
| 194 | #if (GNB_TYPE_TN == TRUE) |
| 195 | #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE TRUE |
| 196 | #else |
| 197 | #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE |
| 198 | #endif |
| 199 | #endif |
| 200 | |
| 201 | #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE |
| 202 | #if (GNB_TYPE_TN == TRUE) |
| 203 | #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE TRUE |
| 204 | #else |
| 205 | #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE |
| 206 | #endif |
| 207 | #endif |
| 208 | |
| 209 | #ifndef CFG_GNB_ALTVDDNB_SUPPORT |
| 210 | #define CFG_GNB_ALTVDDNB_SUPPORT TRUE |
| 211 | #endif |
| 212 | |
| 213 | #ifndef CFG_GNB_BAPM_SUPPORT |
| 214 | #if (GNB_TYPE_TN == TRUE) |
| 215 | #define CFG_GNB_BAPM_SUPPORT TRUE |
| 216 | #else |
| 217 | #define CFG_GNB_BAPM_SUPPORT FALSE |
| 218 | #endif |
| 219 | #endif |
| 220 | |
| 221 | #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE |
| 222 | #define CFG_UNUSED_SIMD_POWERGATING_ENABLE TRUE |
| 223 | #endif |
| 224 | |
| 225 | #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE |
| 226 | #define CFG_UNUSED_RB_POWERGATING_ENABLE FALSE |
| 227 | #endif |
| 228 | |
| 229 | #ifndef CFG_NBDPM_ENABLE |
| 230 | #define CFG_NBDPM_ENABLE TRUE |
| 231 | #endif |
| 232 | |
| 233 | #ifndef CFG_MAX_PAYLOAD_ENABLE |
| 234 | #define CFG_MAX_PAYLOAD_ENABLE TRUE |
| 235 | #endif |
| 236 | |
| 237 | #ifndef CFG_GMC_CLOCK_GATING |
| 238 | #if (GNB_TYPE_TN == TRUE) |
| 239 | #define CFG_GMC_CLOCK_GATING TRUE |
| 240 | #else |
| 241 | #define CFG_GMC_CLOCK_GATING TRUE |
| 242 | #endif |
| 243 | #endif |
| 244 | |
| 245 | #ifndef CFG_ORB_DYN_WAKE_ENABLE |
| 246 | #if (GNB_TYPE_TN == TRUE) |
| 247 | #define CFG_ORB_DYN_WAKE_ENABLE TRUE |
| 248 | #else |
| 249 | #define CFG_ORB_DYN_WAKE_ENABLE TRUE |
| 250 | #endif |
| 251 | #endif |
| 252 | |
| 253 | #ifndef CFG_LOADLINE_ENABLE |
| 254 | #define CFG_LOADLINE_ENABLE TRUE |
| 255 | #endif |
| 256 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 257 | CONST GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 258 | CFG_IGFX_AS_PCIE_EP, |
| 259 | CFG_LCLK_DEEP_SLEEP_EN, |
| 260 | CFG_LCLK_DPM_EN, |
| 261 | CFG_GMC_POWER_GATING, |
| 262 | CFG_SMU_SCLK_CLOCK_GATING_ENABLE, |
| 263 | CFG_PCIE_ASPM_BLACK_LIST_ENABLE, |
| 264 | CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT, |
| 265 | CFG_GNB_LOAD_REAL_FUSE, |
| 266 | CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, |
| 267 | CFG_GNB_PCIE_LINK_L0_POOLING, |
| 268 | CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, |
| 269 | CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, |
| 270 | CFG_GNB_PCIE_TRAINING_ALGORITHM, |
| 271 | CFG_GNB_FORCE_CABLESAFE_OFF, |
| 272 | CFG_ORB_CLOCK_GATING_ENABLE, |
| 273 | CFG_GNB_PCIE_POWERGATING_FLAGS, |
| 274 | CFG_IOC_LCLK_CLOCK_GATING_ENABLE, |
| 275 | CFG_IOC_SCLK_CLOCK_GATING_ENABLE, |
| 276 | CFG_IOMMU_L1_CLOCK_GATING_ENABLE, |
| 277 | CFG_IOMMU_L2_CLOCK_GATING_ENABLE, |
| 278 | CFG_GNB_ALTVDDNB_SUPPORT, |
| 279 | CFG_GNB_BAPM_SUPPORT, |
| 280 | CFG_UNUSED_SIMD_POWERGATING_ENABLE, |
| 281 | CFG_UNUSED_RB_POWERGATING_ENABLE, |
| 282 | CFG_NBDPM_ENABLE, |
| 283 | CFG_GMC_CLOCK_GATING, |
| 284 | CFG_MAX_PAYLOAD_ENABLE, |
| 285 | CFG_ORB_DYN_WAKE_ENABLE, |
| 286 | CFG_LOADLINE_ENABLE |
| 287 | }; |
| 288 | |
| 289 | //--------------------------------------------------------------------------------------------------- |
| 290 | // Module entries |
| 291 | //--------------------------------------------------------------------------------------------------- |
| 292 | |
| 293 | #if (AGESA_ENTRY_INIT_EARLY == TRUE) |
| 294 | //--------------------------------------------------------------------------------------------------- |
| 295 | #ifndef OPTION_NB_EARLY_INIT |
| 296 | #define OPTION_NB_EARLY_INIT TRUE |
| 297 | #endif |
| 298 | #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 299 | OPTION_GNB_FEATURE NbInitAtEarly; |
| 300 | #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtEarly}, |
| 301 | #else |
| 302 | #define OPTION_NBINITATEARLY_ENTRY |
| 303 | #endif |
| 304 | #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 305 | OPTION_GNB_FEATURE GnbEarlyInterfaceTN; |
| 306 | #define OPTION_GNBEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlyInterfaceTN}, |
| 307 | #else |
| 308 | #define OPTION_GNBEARLYINTERFACETN_ENTRY |
| 309 | #endif |
| 310 | //--------------------------------------------------------------------------------------------------- |
| 311 | // SMU init |
| 312 | #ifndef OPTION_SMU |
| 313 | #define OPTION_SMU TRUE |
| 314 | #endif |
| 315 | #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE) |
| 316 | OPTION_GNB_FEATURE F12NbSmuInitFeature; |
| 317 | #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature}, |
| 318 | #else |
| 319 | #define OPTION_F12NBSMUINITFEATURE_ENTRY |
| 320 | #endif |
| 321 | #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE) |
| 322 | OPTION_GNB_FEATURE F14NbSmuInitFeature; |
| 323 | #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature}, |
| 324 | #else |
| 325 | #define OPTION_F14NBSMUINITFEATURE_ENTRY |
| 326 | #endif |
| 327 | //--------------------------------------------------------------------------------------------------- |
| 328 | #ifndef OPTION_PCIE_CONFIG_MAP |
| 329 | #define OPTION_PCIE_CONFIG_MAP TRUE |
| 330 | #endif |
| 331 | #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) |
| 332 | OPTION_GNB_FEATURE PcieConfigurationMap; |
| 333 | #define OPTION_PCIECONFIGURATIONMAP_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieConfigurationMap}, |
| 334 | #else |
| 335 | #define OPTION_PCIECONFIGURATIONMAP_ENTRY |
| 336 | #endif |
| 337 | //--------------------------------------------------------------------------------------------------- |
| 338 | #ifndef OPTION_PCIE_EARLY_INIT |
| 339 | #define OPTION_PCIE_EARLY_INIT TRUE |
| 340 | #endif |
| 341 | #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 342 | OPTION_GNB_FEATURE PcieInitAtEarly; |
| 343 | #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEarly}, |
| 344 | #else |
| 345 | #define OPTION_PCIEINITATEARLY_ENTRY |
| 346 | #endif |
| 347 | #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 348 | OPTION_GNB_FEATURE PcieEarlyInterfaceTN; |
| 349 | #define OPTION_PCIEEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEarlyInterfaceTN}, |
| 350 | #else |
| 351 | #define OPTION_PCIEEARLYINTERFACETN_ENTRY |
| 352 | #endif |
| 353 | |
| 354 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 355 | CONST OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 356 | OPTION_NBINITATEARLY_ENTRY |
| 357 | OPTION_GNBEARLYINTERFACETN_ENTRY |
| 358 | OPTION_F12NBSMUINITFEATURE_ENTRY |
| 359 | OPTION_F14NBSMUINITFEATURE_ENTRY |
| 360 | OPTION_PCIECONFIGURATIONMAP_ENTRY |
| 361 | OPTION_PCIEINITATEARLY_ENTRY |
| 362 | OPTION_PCIEEARLYINTERFACETN_ENTRY |
| 363 | {0, NULL} |
| 364 | }; |
| 365 | |
| 366 | //--------------------------------------------------------------------------------------------------- |
| 367 | #ifndef OPTION_PCIE_CONFIG_INIT |
| 368 | #define OPTION_PCIE_CONFIG_INIT TRUE |
| 369 | #endif |
| 370 | #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) |
| 371 | OPTION_GNB_FEATURE PcieConfigurationInit; |
| 372 | #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieConfigurationInit}, |
| 373 | #else |
| 374 | #define OPTION_PCIECONFIGURATIONINIT_ENTRY |
| 375 | #endif |
| 376 | //--------------------------------------------------------------------------------------------------- |
| 377 | #ifndef OPTION_NB_EARLIER_INIT |
| 378 | #define OPTION_NB_EARLIER_INIT TRUE |
| 379 | #endif |
| 380 | #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 381 | OPTION_GNB_FEATURE GnbEarlierInterfaceTN; |
| 382 | #define OPTION_GNBEARLIERINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlierInterfaceTN}, |
| 383 | #else |
| 384 | #define OPTION_GNBEARLIERINTERFACETN_ENTRY |
| 385 | #endif |
| 386 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 387 | CONST OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 388 | OPTION_PCIECONFIGURATIONINIT_ENTRY |
| 389 | OPTION_GNBEARLIERINTERFACETN_ENTRY |
| 390 | {0, NULL} |
| 391 | }; |
| 392 | #endif |
| 393 | |
| 394 | #if (AGESA_ENTRY_INIT_POST == TRUE) |
| 395 | //--------------------------------------------------------------------------------------------------- |
| 396 | #ifndef OPTION_GFX_CONFIG_POST_INIT |
| 397 | #define OPTION_GFX_CONFIG_POST_INIT TRUE |
| 398 | #endif |
| 399 | #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) |
| 400 | OPTION_GNB_FEATURE GfxConfigPostInterface; |
| 401 | #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , GfxConfigPostInterface}, |
| 402 | #else |
| 403 | #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY |
| 404 | #endif |
| 405 | //--------------------------------------------------------------------------------------------------- |
| 406 | #ifndef OPTION_GFX_POST_INIT |
| 407 | #define OPTION_GFX_POST_INIT TRUE |
| 408 | #endif |
| 409 | #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 410 | OPTION_GNB_FEATURE GfxInitAtPost; |
| 411 | #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtPost}, |
| 412 | #else |
| 413 | #define OPTION_GFXINITATPOST_ENTRY |
| 414 | #endif |
| 415 | #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 416 | OPTION_GNB_FEATURE GfxPostInterfaceTN; |
| 417 | #define OPTION_GFXPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxPostInterfaceTN}, |
| 418 | #else |
| 419 | #define OPTION_GFXPOSTINTERFACETN_ENTRY |
| 420 | #endif |
| 421 | |
| 422 | //--------------------------------------------------------------------------------------------------- |
| 423 | #ifndef OPTION_NB_POST_INIT |
| 424 | #define OPTION_NB_POST_INIT TRUE |
| 425 | #endif |
| 426 | #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 427 | OPTION_GNB_FEATURE NbInitAtPost; |
| 428 | #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtPost}, |
| 429 | #else |
| 430 | #define OPTION_NBINITATPOST_ENTRY |
| 431 | #endif |
| 432 | #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 433 | OPTION_GNB_FEATURE GnbPostInterfaceTN; |
| 434 | #define OPTION_GNBPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbPostInterfaceTN}, |
| 435 | #else |
| 436 | #define OPTION_GNBPOSTINTERFACETN_ENTRY |
| 437 | #endif |
| 438 | |
| 439 | //--------------------------------------------------------------------------------------------------- |
| 440 | #ifndef OPTION_PCIE_POST_EALRY_INIT |
| 441 | #define OPTION_PCIE_POST_EALRY_INIT TRUE |
| 442 | #endif |
| 443 | #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 444 | OPTION_GNB_FEATURE PcieInitAtPostEarly; |
| 445 | #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPostEarly}, |
| 446 | #else |
| 447 | #define OPTION_PCIEINITATPOSTEARLY_ENTRY |
| 448 | #endif |
| 449 | #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 450 | OPTION_GNB_FEATURE PciePostEarlyInterfaceTN; |
| 451 | #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostEarlyInterfaceTN}, |
| 452 | #else |
| 453 | #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY |
| 454 | #endif |
| 455 | |
| 456 | //--------------------------------------------------------------------------------------------------- |
| 457 | #ifndef OPTION_PCIE_POST_INIT |
| 458 | #define OPTION_PCIE_POST_INIT TRUE |
| 459 | #endif |
| 460 | #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 461 | OPTION_GNB_FEATURE PcieInitAtPost; |
| 462 | #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPost}, |
| 463 | #else |
| 464 | #define OPTION_PCIEINITATPOST_ENTRY |
| 465 | #endif |
| 466 | #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 467 | OPTION_GNB_FEATURE PciePostInterfaceTN; |
| 468 | #define OPTION_PCIEPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostInterfaceTN}, |
| 469 | #else |
| 470 | #define OPTION_PCIEPOSTINTERFACETN_ENTRY |
| 471 | #endif |
| 472 | |
| 473 | //--------------------------------------------------------------------------------------------------- |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 474 | CONST OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 475 | OPTION_PCIEINITATPOSTEARLY_ENTRY |
| 476 | OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY |
| 477 | OPTION_GFXCONFIGPOSTINTERFACE_ENTRY |
| 478 | OPTION_GFXINITATPOST_ENTRY |
| 479 | OPTION_GFXPOSTINTERFACETN_ENTRY |
| 480 | {0, NULL} |
| 481 | }; |
| 482 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 483 | CONST OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 484 | OPTION_NBINITATPOST_ENTRY |
| 485 | OPTION_GNBPOSTINTERFACETN_ENTRY |
| 486 | OPTION_PCIEINITATPOST_ENTRY |
| 487 | OPTION_PCIEPOSTINTERFACETN_ENTRY |
| 488 | {0, NULL} |
| 489 | }; |
| 490 | #endif |
| 491 | |
| 492 | #if (AGESA_ENTRY_INIT_ENV == TRUE) |
| 493 | //--------------------------------------------------------------------------------------------------- |
| 494 | #ifndef OPTION_FUSE_TABLE_INIT |
| 495 | #define OPTION_FUSE_TABLE_INIT TRUE |
| 496 | #endif |
| 497 | #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 498 | OPTION_GNB_FEATURE NbFuseTableFeature; |
| 499 | #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbFuseTableFeature}, |
| 500 | #else |
| 501 | #define OPTION_NBFUSETABLEFEATURE_ENTRY |
| 502 | #endif |
| 503 | //--------------------------------------------------------------------------------------------------- |
| 504 | #ifndef OPTION_NB_ENV_INIT |
| 505 | #define OPTION_NB_ENV_INIT TRUE |
| 506 | #endif |
| 507 | #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 508 | OPTION_GNB_FEATURE NbInitAtEnv; |
| 509 | #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtEnv}, |
| 510 | #else |
| 511 | #define OPTION_NBINITATENVT_ENTRY |
| 512 | #endif |
| 513 | #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 514 | OPTION_GNB_FEATURE GnbEnvInterfaceTN; |
| 515 | #define OPTION_GNBENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEnvInterfaceTN}, |
| 516 | #else |
| 517 | #define OPTION_GNBENVINTERFACETN_ENTRY |
| 518 | #endif |
| 519 | |
| 520 | //--------------------------------------------------------------------------------------------------- |
| 521 | #ifndef OPTION_GFX_CONFIG_ENV_INIT |
| 522 | #define OPTION_GFX_CONFIG_ENV_INIT TRUE |
| 523 | #endif |
| 524 | #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) |
| 525 | OPTION_GNB_FEATURE GfxConfigEnvInterface; |
| 526 | #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN, GfxConfigEnvInterface}, |
| 527 | #else |
| 528 | #define OPTION_GFXCONFIGENVINTERFACE_ENTRY |
| 529 | #endif |
| 530 | |
| 531 | //--------------------------------------------------------------------------------------------------- |
| 532 | #ifndef OPTION_GFX_ENV_INIT |
| 533 | #define OPTION_GFX_ENV_INIT TRUE |
| 534 | #endif |
| 535 | #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 536 | OPTION_GNB_FEATURE GfxInitAtEnvPost; |
| 537 | #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtEnvPost}, |
| 538 | #else |
| 539 | #define OPTION_GFXINITATENVPOST_ENTRY |
| 540 | #endif |
| 541 | #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 542 | OPTION_GNB_FEATURE GfxEnvInterfaceTN; |
| 543 | #define OPTION_GFXENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxEnvInterfaceTN}, |
| 544 | #else |
| 545 | #define OPTION_GFXENVINTERFACETN_ENTRY |
| 546 | #endif |
| 547 | |
| 548 | //--------------------------------------------------------------------------------------------------- |
| 549 | #ifndef OPTION_POWER_GATE |
| 550 | #define OPTION_POWER_GATE TRUE |
| 551 | #endif |
| 552 | #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) |
| 553 | OPTION_GNB_FEATURE F12NbPowerGateFeature; |
| 554 | #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature}, |
| 555 | #else |
| 556 | #define OPTION_F12NBPOWERGATEFEATURE_ENTRY |
| 557 | #endif |
| 558 | #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE) |
| 559 | OPTION_GNB_FEATURE F14NbPowerGateFeature; |
| 560 | #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature}, |
| 561 | #else |
| 562 | #define OPTION_F14NBPOWERGATEFEATURE_ENTRY |
| 563 | #endif |
| 564 | //--------------------------------------------------------------------------------------------------- |
| 565 | #ifndef OPTION_PCIE_ENV_INIT |
| 566 | #define OPTION_PCIE_ENV_INIT TRUE |
| 567 | #endif |
| 568 | #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 569 | OPTION_GNB_FEATURE PcieInitAtEnv; |
| 570 | #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEnv}, |
| 571 | #else |
| 572 | #define OPTION_PCIEINITATENV_ENTRY |
| 573 | #endif |
| 574 | #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 575 | OPTION_GNB_FEATURE PcieEnvInterfaceTN; |
| 576 | #define OPTION_PCIEENVINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEnvInterfaceTN}, |
| 577 | #else |
| 578 | #define OPTION_PCIEENVINTERFACETN_ENTRY |
| 579 | #endif |
| 580 | |
| 581 | //--------------------------------------------------------------------------------------------------- |
| 582 | |
| 583 | OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { |
| 584 | OPTION_NBFUSETABLEFEATURE_ENTRY |
| 585 | OPTION_NBINITATENVT_ENTRY |
| 586 | OPTION_GNBENVINTERFACETN_ENTRY |
| 587 | OPTION_PCIEINITATENV_ENTRY |
| 588 | OPTION_PCIEENVINTERFACETN_ENTRY |
| 589 | OPTION_GFXCONFIGENVINTERFACE_ENTRY |
| 590 | OPTION_GFXINITATENVPOST_ENTRY |
| 591 | OPTION_GFXENVINTERFACETN_ENTRY |
| 592 | OPTION_F12NBPOWERGATEFEATURE_ENTRY |
| 593 | OPTION_F14NBPOWERGATEFEATURE_ENTRY |
| 594 | {0, NULL} |
| 595 | }; |
| 596 | #endif |
| 597 | |
| 598 | #if (AGESA_ENTRY_INIT_MID == TRUE) |
| 599 | //--------------------------------------------------------------------------------------------------- |
| 600 | #ifndef OPTION_GNB_CABLESAFE |
| 601 | #define OPTION_GNB_CABLESAFE TRUE |
| 602 | #endif |
| 603 | #if (OPTION_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE) |
| 604 | OPTION_GNB_FEATURE GnbCableSafeEntry; |
| 605 | #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry}, |
| 606 | #else |
| 607 | #define OPTION_GNBCABLESAFEENTRY_ENTRY |
| 608 | #endif |
| 609 | //--------------------------------------------------------------------------------------------------- |
| 610 | #ifndef OPTION_NB_LCLK_NCLK_RATIO |
| 611 | #define OPTION_NB_LCLK_NCLK_RATIO TRUE |
| 612 | #endif |
| 613 | #if (OPTION_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE) |
| 614 | OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature; |
| 615 | #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature}, |
| 616 | #else |
| 617 | #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY |
| 618 | #endif |
| 619 | //--------------------------------------------------------------------------------------------------- |
| 620 | #ifndef OPTION_NB_LCLK_DPM_INIT |
| 621 | #define OPTION_NB_LCLK_DPM_INIT TRUE |
| 622 | #endif |
| 623 | #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 624 | OPTION_GNB_FEATURE NbLclkDpmFeature; |
| 625 | #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbLclkDpmFeature}, |
| 626 | #else |
| 627 | #define OPTION_NBLCLKDPMFEATURE_ENTRY |
| 628 | #endif |
| 629 | //--------------------------------------------------------------------------------------------------- |
| 630 | #ifndef OPTION_PCIE_POWER_GATE |
| 631 | #define OPTION_PCIE_POWER_GATE TRUE |
| 632 | #endif |
| 633 | #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) |
| 634 | OPTION_GNB_FEATURE PciePowerGateFeature; |
| 635 | #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature}, |
| 636 | #else |
| 637 | #define OPTION_PCIEPOWERGATEFEATURE_ENTRY |
| 638 | #endif |
| 639 | //--------------------------------------------------------------------------------------------------- |
| 640 | #ifndef OPTION_GFX_MID_INIT |
| 641 | #define OPTION_GFX_MID_INIT TRUE |
| 642 | #endif |
| 643 | #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 644 | OPTION_GNB_FEATURE GfxInitAtMidPost; |
| 645 | #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtMidPost}, |
| 646 | #else |
| 647 | #define OPTION_GFXINITATMIDPOST_ENTRY |
| 648 | #endif |
| 649 | #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 650 | OPTION_GNB_FEATURE GfxMidInterfaceTN; |
| 651 | #define OPTION_GFXMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxMidInterfaceTN}, |
| 652 | #else |
| 653 | #define OPTION_GFXMIDINTERFACETN_ENTRY |
| 654 | #endif |
| 655 | //--------------------------------------------------------------------------------------------------- |
| 656 | #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT |
| 657 | #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE |
| 658 | #endif |
| 659 | #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 660 | OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry; |
| 661 | #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxIntegratedInfoTableEntry}, |
| 662 | #else |
| 663 | #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY |
| 664 | #endif |
| 665 | #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 666 | OPTION_GNB_FEATURE GfxIntInfoTableInterfaceTN; |
| 667 | #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxIntInfoTableInterfaceTN}, |
| 668 | #else |
| 669 | #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY |
| 670 | #endif |
| 671 | |
| 672 | //--------------------------------------------------------------------------------------------------- |
| 673 | #ifndef OPTION_PCIe_MID_INIT |
| 674 | #define OPTION_PCIe_MID_INIT TRUE |
| 675 | #endif |
| 676 | #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 677 | OPTION_GNB_FEATURE PcieInitAtMid; |
| 678 | #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtMid}, |
| 679 | #else |
| 680 | #define OPTION_PCIEINITATMID_ENTRY |
| 681 | #endif |
| 682 | #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 683 | OPTION_GNB_FEATURE PcieMidInterfaceTN; |
| 684 | #define OPTION_PCIEMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieMidInterfaceTN}, |
| 685 | #else |
| 686 | #define OPTION_PCIEMIDINTERFACETN_ENTRY |
| 687 | #endif |
| 688 | |
| 689 | //--------------------------------------------------------------------------------------------------- |
| 690 | #ifndef OPTION_NB_MID_INIT |
| 691 | #define OPTION_NB_MID_INIT TRUE |
| 692 | #endif |
| 693 | #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 694 | OPTION_GNB_FEATURE NbInitAtLatePost; |
| 695 | #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtLatePost}, |
| 696 | #else |
| 697 | #define OPTION_NBINITATLATEPOST_ENTRY |
| 698 | #endif |
| 699 | #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) |
| 700 | OPTION_GNB_FEATURE GnbMidInterfaceTN; |
| 701 | #define OPTION_GNBMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbMidInterfaceTN}, |
| 702 | #else |
| 703 | #define OPTION_GNBMIDINTERFACETN_ENTRY |
| 704 | #endif |
| 705 | //--------------------------------------------------------------------------------------------------- |
| 706 | #ifndef OPTION_GFX_CONFIG_POST_INIT |
| 707 | #define OPTION_GFX_CONFIG_POST_INIT TRUE |
| 708 | #endif |
| 709 | #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE) |
| 710 | OPTION_GNB_FEATURE GfxConfigMidInterface; |
| 711 | #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_TN | GNB_TYPE_ON, GfxConfigMidInterface}, |
| 712 | #else |
| 713 | #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY |
| 714 | #endif |
| 715 | //--------------------------------------------------------------------------------------------------- |
| 716 | |
| 717 | //--------------------------------------------------------------------------------------------------- |
| 718 | #ifndef OPTION_PCIE_CLK_PM_INTERFACE |
| 719 | #define OPTION_PCIE_CLK_PM_INTERFACE FALSE |
| 720 | #if (GNB_TYPE_ON == TRUE ) |
| 721 | #undef OPTION_PCIE_CLK_PM_INTERFACE |
| 722 | #define OPTION_PCIE_CLK_PM_INTERFACE TRUE |
| 723 | #endif |
| 724 | #if (GNB_TYPE_TN == TRUE && (OPTION_FS1_SOCKET_SUPPORT == TRUE || OPTION_FP1_SOCKET_SUPPORT == TRUE)) |
| 725 | #undef OPTION_PCIE_CLK_PM_INTERFACE |
| 726 | #define OPTION_PCIE_CLK_PM_INTERFACE TRUE |
| 727 | #endif |
| 728 | #endif |
| 729 | |
| 730 | #if (OPTION_PCIE_CLK_PM_INTERFACE == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE ) |
| 731 | OPTION_GNB_FEATURE PcieClkPmInterface; |
| 732 | #define OPTION_PCIECLKPMINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_ON, PcieClkPmInterface}, |
| 733 | #else |
| 734 | #define OPTION_PCIECLKPMINTERFACE_ENTRY |
| 735 | #endif |
| 736 | //--------------------------------------------------------------------------------------------------- |
| 737 | #ifndef OPTION_PCIE_ASPM_INTERFACE |
| 738 | #define OPTION_PCIE_ASPM_INTERFACE TRUE |
| 739 | #endif |
| 740 | #if (OPTION_PCIE_ASPM_INTERFACE == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) |
| 741 | OPTION_GNB_FEATURE PcieAspmInterface; |
| 742 | #define OPTION_PCIEASPMINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieAspmInterface}, |
| 743 | #else |
| 744 | #define OPTION_PCIEASPMINTERFACE_ENTRY |
| 745 | #endif |
| 746 | //--------------------------------------------------------------------------------------------------- |
| 747 | #ifndef OPTION_GNB_IOAPIC_INTERFACE |
| 748 | #define OPTION_GNB_IOAPIC_INTERFACE TRUE |
| 749 | #endif |
| 750 | //--------------------------------------------------------------------------------------------------- |
| 751 | OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { |
| 752 | OPTION_GFXCONFIGMIDINTERFACE_ENTRY |
| 753 | OPTION_GFXINITATMIDPOST_ENTRY |
| 754 | OPTION_GFXMIDINTERFACETN_ENTRY |
| 755 | OPTION_GFXINTEGRATEDINFOTABLE_ENTRY |
| 756 | OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY |
| 757 | OPTION_GNBCABLESAFEENTRY_ENTRY |
| 758 | OPTION_PCIEINITATMID_ENTRY |
| 759 | OPTION_PCIEMIDINTERFACETN_ENTRY |
| 760 | OPTION_NBINITATLATEPOST_ENTRY |
| 761 | OPTION_GNBMIDINTERFACETN_ENTRY |
| 762 | OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY |
| 763 | OPTION_NBLCLKDPMFEATURE_ENTRY |
| 764 | OPTION_PCIEPOWERGATEFEATURE_ENTRY |
| 765 | OPTION_PCIECLKPMINTERFACE_ENTRY |
| 766 | OPTION_PCIEASPMINTERFACE_ENTRY |
| 767 | {0, NULL} |
| 768 | }; |
| 769 | #endif |
| 770 | |
| 771 | #if (AGESA_ENTRY_INIT_LATE == TRUE) |
| 772 | //--------------------------------------------------------------------------------------------------- |
| 773 | #ifndef OPTION_ALIB |
| 774 | #define OPTION_ALIB FALSE |
| 775 | #endif |
| 776 | #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE) |
| 777 | extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo; |
| 778 | #if (GNB_TYPE_LN == TRUE) |
| 779 | #if (OPTION_FM1_SOCKET_SUPPORT == TRUE) |
| 780 | extern F_ALIB_GET PcieAlibGetBaseTableLNFM1; |
| 781 | F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableLNFM1; |
| 782 | #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo |
| 783 | #else |
| 784 | extern F_ALIB_GET PcieAlibGetBaseTableLNFS1; |
| 785 | F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableLNFS1; |
| 786 | extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo; |
| 787 | extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo; |
| 788 | extern F_ALIB_UPDATE PcieAlibBuildAcpiTableLNFS1; |
| 789 | #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \ |
| 790 | PcieAlibUpdateVoltageInfo, \ |
| 791 | PcieAlibUpdatePcieInfo, \ |
| 792 | PcieAlibBuildAcpiTableLNFS1 |
| 793 | #endif |
| 794 | #elif (GNB_TYPE_TN == TRUE) |
| 795 | #if (OPTION_FM2_SOCKET_SUPPORT == TRUE) |
| 796 | extern F_ALIB_GET PcieAlibGetBaseTableTNFM2; |
| 797 | F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFM2; |
| 798 | #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo |
| 799 | #else |
| 800 | extern F_ALIB_GET PcieAlibGetBaseTableTNFS1; |
| 801 | F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFS1; |
| 802 | extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo; |
| 803 | extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo; |
| 804 | extern F_ALIB_UPDATE PcieAlibBuildAcpiTableLNFS2; |
| 805 | #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \ |
| 806 | PcieAlibUpdateVoltageInfo, \ |
| 807 | PcieAlibUpdatePcieInfo |
| 808 | |
| 809 | #endif |
| 810 | #else |
| 811 | extern F_ALIB_GET PcieAlibGetBaseTable; |
| 812 | F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTable; |
| 813 | extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo; |
| 814 | extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo; |
| 815 | extern F_ALIB_UPDATE PcieFmAlibBuildAcpiTable; |
| 816 | #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \ |
| 817 | PcieAlibUpdateVoltageInfo, \ |
| 818 | PcieAlibUpdatePcieInfo, \ |
| 819 | PcieFmAlibBuildAcpiTable |
| 820 | #endif |
| 821 | F_ALIB_UPDATE* AlibDispatchTable [] = { |
| 822 | ALIB_CALL_TABLE, |
| 823 | NULL |
| 824 | }; |
| 825 | OPTION_GNB_FEATURE PcieAlibFeature; |
| 826 | #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN, PcieAlibFeature}, |
| 827 | #else |
| 828 | F_ALIB_GET *AlibGetBaseTable = NULL; |
| 829 | F_ALIB_UPDATE* AlibDispatchTable [] = { |
| 830 | NULL |
| 831 | }; |
| 832 | #define OPTION_PCIEALIBFEATURE_ENTRY |
| 833 | #endif |
| 834 | //--------------------------------------------------------------------------------------------------- |
| 835 | #ifndef OPTION_IOMMU_ACPI_IVRS |
| 836 | #if (CFG_IOMMU_SUPPORT == TRUE) |
| 837 | #define OPTION_IOMMU_ACPI_IVRS TRUE |
| 838 | #else |
| 839 | #define OPTION_IOMMU_ACPI_IVRS FALSE |
| 840 | #endif |
| 841 | #endif |
| 842 | #if (OPTION_IOMMU_ACPI_IVRS == TRUE) && (GNB_TYPE_TN == TRUE ) |
| 843 | OPTION_GNB_FEATURE GnbIommuIvrsTable; |
| 844 | #define OPTIONIOMMUACPIIVRSLATE_ENTRY {AMD_FAMILY_TN, GnbIommuIvrsTable}, |
| 845 | #else |
| 846 | #define OPTIONIOMMUACPIIVRSLATE_ENTRY |
| 847 | #endif |
| 848 | #if (CFG_IOMMU_SUPPORT == TRUE) && (GNB_TYPE_TN == TRUE ) |
| 849 | OPTION_GNB_FEATURE GnbIommuScratchMemoryRangeInterface; |
| 850 | #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY {AMD_FAMILY_TN , GnbIommuScratchMemoryRangeInterface}, |
| 851 | #else |
| 852 | #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY |
| 853 | #endif |
| 854 | //--------------------------------------------------------------------------------------------------- |
| 855 | OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { |
| 856 | OPTION_PCIEALIBFEATURE_ENTRY |
| 857 | OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY |
| 858 | OPTIONIOMMUACPIIVRSLATE_ENTRY |
| 859 | {0, NULL} |
| 860 | }; |
| 861 | #endif |
| 862 | |
| 863 | #if (AGESA_ENTRY_INIT_S3SAVE == TRUE) |
| 864 | //--------------------------------------------------------------------------------------------------- |
| 865 | #ifndef OPTION_GFX_INIT_SVIEW |
| 866 | #define OPTION_GFX_INIT_SVIEW TRUE |
| 867 | #endif |
| 868 | #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE) |
| 869 | OPTION_GNB_FEATURE GfxInitSview; |
| 870 | #define OPTION_GFXINITSVIEW_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_TN, GfxInitSview}, |
| 871 | #else |
| 872 | #define OPTION_GFXINITSVIEW_ENTRY |
| 873 | #endif |
| 874 | |
| 875 | OPTION_GNB_CONFIGURATION GnbS3SaveFeatureTable[] = { |
| 876 | OPTION_GFXINITSVIEW_ENTRY |
| 877 | {0, NULL} |
| 878 | }; |
| 879 | #endif |
| 880 | #if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) |
| 881 | S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script; |
| 882 | S3_DISPATCH_FUNCTION PcieLateRestoreS3Script; |
| 883 | S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script; |
| 884 | #define GNB_S3_DISPATCH_FUNCTION_TABLE \ |
| 885 | {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \ |
| 886 | {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \ |
| 887 | {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script}, |
| 888 | #endif |
| 889 | |
| 890 | |
| 891 | #if (GNB_TYPE_TN == TRUE ) |
| 892 | S3_DISPATCH_FUNCTION GnbSmuServiceRequestV4S3Script; |
| 893 | S3_DISPATCH_FUNCTION GnbLibStallS3Script; |
| 894 | #define PCIELATERESTORETN |
| 895 | #define GFXSCLKRESTORETN |
| 896 | #if (GNB_TYPE_TN == TRUE) |
| 897 | S3_DISPATCH_FUNCTION PcieLateRestoreInitTNS3Script; |
| 898 | S3_DISPATCH_FUNCTION GfxRequestSclkTNS3Script; |
| 899 | #undef PCIELATERESTORETN |
| 900 | #define PCIELATERESTORETN {PcieLateRestoreTNS3Script_ID, PcieLateRestoreInitTNS3Script}, |
| 901 | #undef GFXSCLKRESTORETN |
| 902 | #define GFXSCLKRESTORETN {GfxRequestSclkTNS3Script_ID, GfxRequestSclkTNS3Script }, |
| 903 | #endif |
| 904 | #define GNB_S3_DISPATCH_FUNCTION_TABLE \ |
| 905 | {GnbSmuServiceRequestV4S3Script_ID, GnbSmuServiceRequestV4S3Script}, \ |
| 906 | PCIELATERESTORETN \ |
| 907 | GFXSCLKRESTORETN \ |
| 908 | {GnbLibStallS3Script_ID, GnbLibStallS3Script}, |
| 909 | /*these three line should be 1261-1263*/ |
| 910 | |
| 911 | |
| 912 | #endif |
| 913 | |
| 914 | #endif |
| 915 | #endif // _OPTION_GNB_INSTALL_H_ |