Angel Pons | 47f26db | 2020-04-05 13:22:34 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 2 | |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 3 | #include <bootmode.h> |
Kyösti Mälkki | 9c5a9bb | 2019-08-17 05:28:38 +0300 | [diff] [blame] | 4 | #include <boot/coreboot_tables.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 5 | #include <soc/gpio.h> |
Kyösti Mälkki | 9a3bde0 | 2021-11-06 16:13:15 +0200 | [diff] [blame^] | 6 | #include <types.h> |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 7 | #include <vendorcode/google/chromeos/chromeos.h> |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 8 | |
Aaron Durbin | 063c873 | 2013-10-28 11:24:53 -0500 | [diff] [blame] | 9 | /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ |
| 10 | #define WP_STATUS_PAD 36 |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 11 | |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 12 | void fill_lb_gpios(struct lb_gpios *gpios) |
| 13 | { |
Julius Werner | c445b4f | 2016-03-31 17:27:05 -0700 | [diff] [blame] | 14 | struct lb_gpio chromeos_gpios[] = { |
Julius Werner | c445b4f | 2016-03-31 17:27:05 -0700 | [diff] [blame] | 15 | {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, |
| 16 | {-1, ACTIVE_HIGH, 0, "power"}, |
| 17 | {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, |
| 18 | }; |
| 19 | lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 20 | } |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 21 | |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 22 | int get_write_protect_state(void) |
| 23 | { |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 24 | /* |
| 25 | * The vboot loader queries this function in romstage. The GPIOs have |
| 26 | * not been set up yet as that configuration is done in ramstage. The |
| 27 | * hardware defaults to an input but there is a 20K pulldown. Externally |
| 28 | * there is a 10K pullup. Disable the internal pull in romstage so that |
| 29 | * there isn't any ambiguity in the reading. |
| 30 | */ |
Kyösti Mälkki | 2dba294 | 2019-08-18 18:30:40 +0300 | [diff] [blame] | 31 | if (ENV_ROMSTAGE) |
| 32 | ssus_disable_internal_pull(WP_STATUS_PAD); |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 33 | |
Aaron Durbin | 063c873 | 2013-10-28 11:24:53 -0500 | [diff] [blame] | 34 | /* WP is enabled when the pin is reading high. */ |
| 35 | return ssus_get_gpio(WP_STATUS_PAD); |
Aaron Durbin | c625d09 | 2013-10-04 16:00:07 -0500 | [diff] [blame] | 36 | } |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 37 | |
| 38 | static const struct cros_gpio cros_gpios[] = { |
| 39 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 40 | CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), |
| 41 | }; |
| 42 | |
| 43 | void mainboard_chromeos_acpi_generate(void) |
| 44 | { |
| 45 | chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); |
| 46 | } |