Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #ifndef _SOC_APOLLOLAKE_CHIP_H_ |
| 19 | #define _SOC_APOLLOLAKE_CHIP_H_ |
| 20 | |
Furquan Shaikh | 6e37e90 | 2016-07-28 13:44:53 -0700 | [diff] [blame] | 21 | #include <soc/gpe.h> |
Harsha Priya | d9fc5fb | 2016-07-06 12:00:49 -0700 | [diff] [blame] | 22 | #include <soc/gpio_defs.h> |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 23 | #include <soc/gpio.h> |
| 24 | #include <soc/intel/common/lpss_i2c.h> |
| 25 | #include <device/i2c.h> |
Shaunak Saha | 5b6c5a5 | 2016-06-07 02:06:28 -0700 | [diff] [blame] | 26 | #include <soc/pm.h> |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 27 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 28 | #define CLKREQ_DISABLED 0xf |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 29 | #define APOLLOLAKE_I2C_DEV_MAX 8 |
| 30 | |
| 31 | struct apollolake_i2c_config { |
| 32 | /* Bus should be enabled prior to ramstage with temporary base */ |
| 33 | int early_init; |
| 34 | /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ |
| 35 | enum i2c_speed speed; |
| 36 | /* Specific bus speed configuration */ |
| 37 | struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT]; |
| 38 | }; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 39 | |
Alexandru Gagniuc | 3aa34a8 | 2016-04-04 10:47:49 -0700 | [diff] [blame] | 40 | /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ |
| 41 | enum serirq_mode { |
| 42 | SERIRQ_QUIET, |
| 43 | SERIRQ_CONTINUOUS, |
| 44 | SERIRQ_OFF, |
| 45 | }; |
| 46 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 47 | struct soc_intel_apollolake_config { |
| 48 | /* |
| 49 | * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has |
| 50 | * four CLKREQ inputs, but six root ports. Root ports without an |
| 51 | * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" |
| 52 | */ |
| 53 | uint8_t pcie_rp0_clkreq_pin; |
| 54 | uint8_t pcie_rp1_clkreq_pin; |
| 55 | uint8_t pcie_rp2_clkreq_pin; |
| 56 | uint8_t pcie_rp3_clkreq_pin; |
| 57 | uint8_t pcie_rp4_clkreq_pin; |
| 58 | uint8_t pcie_rp5_clkreq_pin; |
Alexandru Gagniuc | 3aa34a8 | 2016-04-04 10:47:49 -0700 | [diff] [blame] | 59 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 60 | /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. |
| 61 | * [6:0] SDR mode Number of dealy elements.Each = 125pSec. |
| 62 | */ |
| 63 | uint32_t emmc_tx_cmd_cntl; |
| 64 | |
| 65 | /* [14:8] HS400 mode Number of dealy elements.Each = 125pSec. |
| 66 | * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. |
| 67 | */ |
| 68 | uint32_t emmc_tx_data_cntl1; |
| 69 | |
| 70 | /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. |
| 71 | * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. |
| 72 | * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. |
| 73 | * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. |
| 74 | */ |
| 75 | uint32_t emmc_tx_data_cntl2; |
| 76 | |
| 77 | /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. |
| 78 | * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. |
| 79 | * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. |
| 80 | * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. |
| 81 | */ |
| 82 | uint32_t emmc_rx_cmd_data_cntl1; |
| 83 | |
| 84 | /* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. |
| 85 | * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. |
| 86 | */ |
| 87 | uint32_t emmc_rx_strobe_cntl; |
| 88 | |
| 89 | /* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. |
| 90 | * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. |
| 91 | */ |
| 92 | uint32_t emmc_rx_cmd_data_cntl2; |
| 93 | |
Alexandru Gagniuc | 3aa34a8 | 2016-04-04 10:47:49 -0700 | [diff] [blame] | 94 | /* Configure serial IRQ (SERIRQ) line. */ |
| 95 | enum serirq_mode serirq_mode; |
Hannah Williams | 483004f | 2016-03-28 14:45:59 -0700 | [diff] [blame] | 96 | |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 97 | /* I2C bus configuration */ |
| 98 | struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX]; |
Shaunak Saha | 5b6c5a5 | 2016-06-07 02:06:28 -0700 | [diff] [blame] | 99 | |
| 100 | uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 101 | uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 102 | uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 103 | |
| 104 | /* Configure LPSS S0ix Enable */ |
| 105 | uint8_t lpss_s0ix_enable; |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 106 | |
| 107 | /* Enable DPTF support */ |
| 108 | int dptf_enable; |
Aaron Durbin | 41a3fa6 | 2016-08-25 15:42:04 -0500 | [diff] [blame] | 109 | |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 110 | /* Configure Audio clk gate and power gate |
| 111 | * IOSF-SB port ID 92 offset 0x530 [5] and [3] |
| 112 | */ |
| 113 | uint8_t hdaudio_clk_gate_enable; |
| 114 | uint8_t hdaudio_pwr_gate_enable; |
| 115 | uint8_t hdaudio_bios_config_lockdown; |
| 116 | |
Aaron Durbin | 41a3fa6 | 2016-08-25 15:42:04 -0500 | [diff] [blame] | 117 | /* SLP S3 minimum assertion width. */ |
| 118 | int slp_s3_assertion_width_usecs; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 119 | |
| 120 | /* GPIO pin for PERST_0 */ |
| 121 | uint16_t prt0_gpio; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ |