Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 2 | |
| 3 | #include <types.h> |
| 4 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <cpu/x86/cache.h> |
| 8 | #include <cpu/x86/smm.h> |
| 9 | #include <device/pci_def.h> |
| 10 | #include "i82801dx.h" |
| 11 | |
| 12 | #define DEBUG_SMI |
| 13 | |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 14 | /* I830M */ |
| 15 | #define SMRAM 0x90 |
| 16 | #define D_OPEN (1 << 6) |
| 17 | #define D_CLS (1 << 5) |
| 18 | #define D_LCK (1 << 4) |
| 19 | #define G_SMRANE (1 << 3) |
| 20 | #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) |
| 21 | |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 22 | /* While we read PMBASE dynamically in case it changed, let's |
| 23 | * initialize it with a sane value |
| 24 | */ |
| 25 | u16 pmbase = PMBASE_ADDR; |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 26 | |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 27 | /** |
| 28 | * @brief read and clear PM1_STS |
| 29 | * @return PM1_STS register |
| 30 | */ |
| 31 | static u16 reset_pm1_status(void) |
| 32 | { |
| 33 | u16 reg16; |
| 34 | |
| 35 | reg16 = inw(pmbase + PM1_STS); |
| 36 | /* set status bits are cleared by writing 1 to them */ |
| 37 | outw(reg16, pmbase + PM1_STS); |
| 38 | |
| 39 | return reg16; |
| 40 | } |
| 41 | |
| 42 | static void dump_pm1_status(u16 pm1_sts) |
| 43 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 44 | printk(BIOS_SPEW, "PM1_STS: "); |
| 45 | if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); |
| 46 | if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); |
| 47 | if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); |
| 48 | if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); |
| 49 | if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); |
| 50 | if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); |
| 51 | if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); |
| 52 | if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); |
| 53 | printk(BIOS_SPEW, "\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 54 | int reg16 = inw(pmbase + PM1_EN); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 55 | printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | /** |
| 59 | * @brief read and clear SMI_STS |
| 60 | * @return SMI_STS register |
| 61 | */ |
| 62 | static u32 reset_smi_status(void) |
| 63 | { |
| 64 | u32 reg32; |
| 65 | |
| 66 | reg32 = inl(pmbase + SMI_STS); |
| 67 | /* set status bits are cleared by writing 1 to them */ |
| 68 | outl(reg32, pmbase + SMI_STS); |
| 69 | |
| 70 | return reg32; |
| 71 | } |
| 72 | |
| 73 | static void dump_smi_status(u32 smi_sts) |
| 74 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 75 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 76 | if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); |
| 77 | if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); |
| 78 | if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); |
| 79 | if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); |
| 80 | if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); |
| 81 | if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); |
| 82 | if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); |
| 83 | if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); |
| 84 | if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); |
| 85 | if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); |
| 86 | if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); |
| 87 | if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); |
| 88 | if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); |
| 89 | if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); |
| 90 | if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); |
| 91 | if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); |
| 92 | if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); |
| 93 | if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); |
| 94 | if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); |
| 95 | if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); |
| 96 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 97 | } |
| 98 | |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 99 | /** |
| 100 | * @brief read and clear GPE0_STS |
| 101 | * @return GPE0_STS register |
| 102 | */ |
| 103 | static u32 reset_gpe0_status(void) |
| 104 | { |
| 105 | u32 reg32; |
| 106 | |
| 107 | reg32 = inl(pmbase + GPE0_STS); |
| 108 | /* set status bits are cleared by writing 1 to them */ |
| 109 | outl(reg32, pmbase + GPE0_STS); |
| 110 | |
| 111 | return reg32; |
| 112 | } |
| 113 | |
| 114 | static void dump_gpe0_status(u32 gpe0_sts) |
| 115 | { |
| 116 | int i; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 117 | printk(BIOS_DEBUG, "GPE0_STS: "); |
Konstantin Aladyshev | 62f8083 | 2013-03-07 04:04:27 +0400 | [diff] [blame] | 118 | for (i=31; i>= 16; i--) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 119 | if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 120 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 121 | if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); |
| 122 | if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); |
| 123 | if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); |
| 124 | if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); |
| 125 | if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); |
| 126 | if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); |
| 127 | if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); |
| 128 | if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); |
| 129 | if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); |
| 130 | if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); |
| 131 | if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); |
| 132 | if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); |
| 133 | if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); |
| 134 | if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); |
| 135 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 136 | } |
| 137 | |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 138 | /** |
| 139 | * @brief read and clear TCOx_STS |
| 140 | * @return TCOx_STS registers |
| 141 | */ |
| 142 | static u32 reset_tco_status(void) |
| 143 | { |
| 144 | u32 tcobase = pmbase + 0x60; |
| 145 | u32 reg32; |
| 146 | |
| 147 | reg32 = inl(tcobase + 0x04); |
| 148 | /* set status bits are cleared by writing 1 to them */ |
| 149 | outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS |
| 150 | if (reg32 & (1 << 18)) |
| 151 | outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS |
| 152 | |
| 153 | return reg32; |
| 154 | } |
| 155 | |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 156 | static void dump_tco_status(u32 tco_sts) |
| 157 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 158 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 159 | if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); |
| 160 | if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); |
| 161 | if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); |
| 162 | if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); |
| 163 | if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); |
| 164 | if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); |
| 165 | if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); |
| 166 | if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); |
| 167 | if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); |
| 168 | if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); |
| 169 | if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); |
| 170 | if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); |
| 171 | if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); |
| 172 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 173 | } |
| 174 | |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 175 | /** |
| 176 | * @brief Set the EOS bit |
| 177 | */ |
| 178 | void southbridge_smi_set_eos(void) |
| 179 | { |
| 180 | u8 reg8; |
| 181 | |
| 182 | reg8 = inb(pmbase + SMI_EN); |
| 183 | reg8 |= EOS; |
| 184 | outb(reg8, pmbase + SMI_EN); |
| 185 | } |
| 186 | |
| 187 | static void busmaster_disable_on_bus(int bus) |
| 188 | { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 189 | int slot, func; |
| 190 | unsigned int val; |
| 191 | unsigned char hdr; |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 192 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 193 | for (slot = 0; slot < 0x20; slot++) { |
| 194 | for (func = 0; func < 8; func++) { |
Elyes HAOUAS | 2f2191a | 2020-04-28 19:59:30 +0200 | [diff] [blame] | 195 | u16 reg16; |
Antonello Dettori | f9aac2f | 2016-09-03 10:45:33 +0200 | [diff] [blame] | 196 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 197 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 198 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 199 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 200 | if (val == 0xffffffff || val == 0x00000000 || |
| 201 | val == 0x0000ffff || val == 0xffff0000) |
| 202 | continue; |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 203 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 204 | /* Disable Bus Mastering for this one device */ |
Elyes HAOUAS | 2f2191a | 2020-04-28 19:59:30 +0200 | [diff] [blame] | 205 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 206 | reg16 &= ~PCI_COMMAND_MASTER; |
| 207 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 208 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 209 | /* If this is a bridge, then follow it. */ |
| 210 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 211 | hdr &= 0x7f; |
| 212 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
| 213 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
| 214 | unsigned int buses; |
| 215 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 216 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 217 | } |
| 218 | } |
| 219 | } |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 220 | } |
| 221 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 222 | static void southbridge_smi_sleep(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 223 | { |
| 224 | u8 reg8; |
| 225 | u32 reg32; |
| 226 | u8 slp_typ; |
| 227 | /* FIXME: the power state on boot should be read from |
| 228 | * CMOS or even better from GNVS. Right now it's hard |
| 229 | * coded at compile time. |
| 230 | */ |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 231 | u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 232 | |
| 233 | /* First, disable further SMIs */ |
| 234 | reg8 = inb(pmbase + SMI_EN); |
| 235 | reg8 &= ~SLP_SMI_EN; |
| 236 | outb(reg8, pmbase + SMI_EN); |
| 237 | |
| 238 | /* Figure out SLP_TYP */ |
| 239 | reg32 = inl(pmbase + PM1_CNT); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 240 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | 671909b | 2016-07-13 23:24:36 -0500 | [diff] [blame] | 241 | slp_typ = acpi_sleep_from_pm1(reg32); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 242 | |
| 243 | /* Next, do the deed. |
| 244 | */ |
| 245 | |
| 246 | switch (slp_typ) { |
Aaron Durbin | 671909b | 2016-07-13 23:24:36 -0500 | [diff] [blame] | 247 | case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; |
| 248 | case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; |
| 249 | case ACPI_S3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 250 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 251 | /* Invalidate the cache before going to S3 */ |
| 252 | wbinvd(); |
| 253 | break; |
Aaron Durbin | 671909b | 2016-07-13 23:24:36 -0500 | [diff] [blame] | 254 | case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; |
| 255 | case ACPI_S5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 256 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 257 | |
| 258 | outl(0, pmbase + GPE0_EN); |
| 259 | |
| 260 | /* Should we keep the power state after a power loss? |
| 261 | * In case the setting is "ON" or "OFF" we don't have |
| 262 | * to do anything. But if it's "KEEP" we have to switch |
| 263 | * to "OFF" before entering S5. |
| 264 | */ |
| 265 | if (s5pwr == MAINBOARD_POWER_KEEP) { |
| 266 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
| 267 | reg8 |= 1; |
| 268 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
| 269 | } |
| 270 | |
| 271 | /* also iterates over all bridges on bus 0 */ |
| 272 | busmaster_disable_on_bus(0); |
| 273 | break; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 274 | default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | /* Write back to the SLP register to cause the originally intended |
| 278 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 279 | * sleep happen. |
| 280 | */ |
| 281 | outl(reg32 | SLP_EN, pmbase + PM1_CNT); |
| 282 | |
| 283 | /* In most sleep states, the code flow of this function ends at |
| 284 | * the line above. However, if we entered sleep state S1 and wake |
| 285 | * up again, we will continue to execute code in this function. |
| 286 | */ |
| 287 | reg32 = inl(pmbase + PM1_CNT); |
| 288 | if (reg32 & SCI_EN) { |
| 289 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 290 | reg32 &= ~(SLP_EN | SLP_TYP); |
| 291 | outl(reg32, pmbase + PM1_CNT); |
| 292 | } |
| 293 | } |
| 294 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 295 | static void southbridge_smi_apmc(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 296 | { |
| 297 | u32 pmctrl; |
| 298 | u8 reg8; |
| 299 | |
Kyösti Mälkki | 9a1620f | 2021-01-08 13:27:33 +0200 | [diff] [blame^] | 300 | reg8 = apm_get_apmc(); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 301 | switch (reg8) { |
Sven Schnelle | f4dc1a7 | 2011-06-05 11:33:41 +0200 | [diff] [blame] | 302 | case APM_CNT_CST_CONTROL: |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 303 | /* Calling this function seems to cause |
| 304 | * some kind of race condition in Linux |
| 305 | * and causes a kernel oops |
| 306 | */ |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 307 | break; |
Sven Schnelle | f4dc1a7 | 2011-06-05 11:33:41 +0200 | [diff] [blame] | 308 | case APM_CNT_PST_CONTROL: |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 309 | /* Calling this function seems to cause |
| 310 | * some kind of race condition in Linux |
| 311 | * and causes a kernel oops |
| 312 | */ |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 313 | break; |
Sven Schnelle | f4dc1a7 | 2011-06-05 11:33:41 +0200 | [diff] [blame] | 314 | case APM_CNT_ACPI_DISABLE: |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 315 | pmctrl = inl(pmbase + PM1_CNT); |
| 316 | pmctrl &= ~SCI_EN; |
| 317 | outl(pmctrl, pmbase + PM1_CNT); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 318 | break; |
Sven Schnelle | f4dc1a7 | 2011-06-05 11:33:41 +0200 | [diff] [blame] | 319 | case APM_CNT_ACPI_ENABLE: |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 320 | pmctrl = inl(pmbase + PM1_CNT); |
| 321 | pmctrl |= SCI_EN; |
| 322 | outl(pmctrl, pmbase + PM1_CNT); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 323 | break; |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 324 | } |
| 325 | } |
| 326 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 327 | static void southbridge_smi_pm1(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 328 | { |
| 329 | u16 pm1_sts; |
| 330 | |
| 331 | pm1_sts = reset_pm1_status(); |
| 332 | dump_pm1_status(pm1_sts); |
| 333 | |
| 334 | /* While OSPM is not active, poweroff immediately |
| 335 | * on a power button event. |
| 336 | */ |
| 337 | if (pm1_sts & PWRBTN_STS) { |
| 338 | // power button pressed |
| 339 | u32 reg32; |
| 340 | reg32 = (7 << 10) | (1 << 13); |
| 341 | outl(reg32, pmbase + PM1_CNT); |
| 342 | } |
| 343 | } |
| 344 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 345 | static void southbridge_smi_gpe0(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 346 | { |
| 347 | u32 gpe0_sts; |
| 348 | |
| 349 | gpe0_sts = reset_gpe0_status(); |
| 350 | dump_gpe0_status(gpe0_sts); |
| 351 | } |
| 352 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 353 | static void southbridge_smi_gpi(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 354 | { |
| 355 | u16 reg16; |
| 356 | reg16 = inw(pmbase + ALT_GP_SMI_STS); |
| 357 | outl(reg16, pmbase + ALT_GP_SMI_STS); |
| 358 | |
| 359 | reg16 &= inw(pmbase + ALT_GP_SMI_EN); |
| 360 | |
Kyösti Mälkki | 48b3dbc | 2014-12-29 19:36:50 +0200 | [diff] [blame] | 361 | mainboard_smi_gpi(reg16); |
| 362 | |
| 363 | if (reg16) |
| 364 | printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 365 | } |
| 366 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 367 | static void southbridge_smi_mc(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 368 | { |
| 369 | u32 reg32; |
| 370 | |
| 371 | reg32 = inl(pmbase + SMI_EN); |
| 372 | |
| 373 | /* Are periodic SMIs enabled? */ |
| 374 | if ((reg32 & MCSMI_EN) == 0) |
| 375 | return; |
| 376 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 377 | printk(BIOS_DEBUG, "Microcontroller SMI.\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 378 | } |
| 379 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 380 | static void southbridge_smi_tco(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 381 | { |
| 382 | u32 tco_sts; |
| 383 | |
| 384 | tco_sts = reset_tco_status(); |
| 385 | |
| 386 | /* Any TCO event? */ |
| 387 | if (!tco_sts) |
| 388 | return; |
| 389 | |
| 390 | if (tco_sts & (1 << 8)) { // BIOSWR |
| 391 | u8 bios_cntl; |
| 392 | |
| 393 | bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); |
| 394 | |
| 395 | if (bios_cntl & 1) { |
| 396 | /* BWE is RW, so the SMI was caused by a |
| 397 | * write to BWE, not by a write to the BIOS |
| 398 | */ |
| 399 | |
| 400 | /* This is the place where we notice someone |
| 401 | * is trying to tinker with the BIOS. We are |
| 402 | * trying to be nice and just ignore it. A more |
| 403 | * resolute answer would be to power down the |
| 404 | * box. |
| 405 | */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 406 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 407 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); |
| 408 | } /* No else for now? */ |
| 409 | } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ |
| 410 | /* Handle TCO timeout */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 411 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
Jacob Garber | 7eb8eed | 2019-04-03 09:18:32 -0600 | [diff] [blame] | 412 | } else { |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 413 | dump_tco_status(tco_sts); |
| 414 | } |
| 415 | } |
| 416 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 417 | static void southbridge_smi_periodic(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 418 | { |
| 419 | u32 reg32; |
| 420 | |
| 421 | reg32 = inl(pmbase + SMI_EN); |
| 422 | |
| 423 | /* Are periodic SMIs enabled? */ |
| 424 | if ((reg32 & PERIODIC_EN) == 0) |
| 425 | return; |
| 426 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 427 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 428 | } |
| 429 | |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 430 | typedef void (*smi_handler_t)(void); |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 431 | |
Stefan Reinauer | 348a1ba | 2010-03-17 01:51:11 +0000 | [diff] [blame] | 432 | smi_handler_t southbridge_smi[32] = { |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 433 | NULL, // [0] reserved |
| 434 | NULL, // [1] reserved |
| 435 | NULL, // [2] BIOS_STS |
| 436 | NULL, // [3] LEGACY_USB_STS |
| 437 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 438 | southbridge_smi_apmc, // [5] APM_STS |
| 439 | NULL, // [6] SWSMI_TMR_STS |
| 440 | NULL, // [7] reserved |
| 441 | southbridge_smi_pm1, // [8] PM1_STS |
| 442 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 443 | southbridge_smi_gpi, // [10] GPI_STS |
| 444 | southbridge_smi_mc, // [11] MCSMI_STS |
| 445 | NULL, // [12] DEVMON_STS |
| 446 | southbridge_smi_tco, // [13] TCO_STS |
| 447 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 448 | NULL, // [15] SERIRQ_SMI_STS |
| 449 | NULL, // [16] SMBUS_SMI_STS |
| 450 | NULL, // [17] LEGACY_USB2_STS |
| 451 | NULL, // [18] INTEL_USB2_STS |
| 452 | NULL, // [19] reserved |
| 453 | NULL, // [20] PCI_EXP_SMI_STS |
Kyösti Mälkki | f4617c0 | 2020-06-28 17:46:39 +0300 | [diff] [blame] | 454 | NULL, // [21] MONITOR_STS |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 455 | NULL, // [22] reserved |
| 456 | NULL, // [23] reserved |
| 457 | NULL, // [24] reserved |
| 458 | NULL, // [25] EL_SMI_STS |
| 459 | NULL, // [26] SPI_STS |
| 460 | NULL, // [27] reserved |
| 461 | NULL, // [28] reserved |
| 462 | NULL, // [29] reserved |
| 463 | NULL, // [30] reserved |
| 464 | NULL // [31] reserved |
| 465 | }; |
| 466 | |
| 467 | /** |
| 468 | * @brief Interrupt handler for SMI# |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 469 | */ |
Kyösti Mälkki | 1ef039b | 2019-08-10 15:32:03 +0300 | [diff] [blame] | 470 | void southbridge_smi_handler(void) |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 471 | { |
| 472 | int i, dump = 0; |
| 473 | u32 smi_sts; |
| 474 | |
| 475 | /* Update global variable pmbase */ |
| 476 | pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; |
| 477 | |
| 478 | /* We need to clear the SMI status registers, or we won't see what's |
| 479 | * happening in the following calls. |
| 480 | */ |
| 481 | smi_sts = reset_smi_status(); |
| 482 | |
| 483 | /* Filter all non-enabled SMI events */ |
| 484 | // FIXME Double check, this clears MONITOR |
| 485 | // smi_sts &= inl(pmbase + SMI_EN); |
| 486 | |
| 487 | /* Call SMI sub handler for each of the status bits */ |
| 488 | for (i = 0; i < 31; i++) { |
| 489 | if (smi_sts & (1 << i)) { |
Kyösti Mälkki | b987282 | 2019-08-10 15:47:29 +0300 | [diff] [blame] | 490 | if (southbridge_smi[i]) { |
| 491 | southbridge_smi[i](); |
| 492 | } else { |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 493 | printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 494 | "handler available.\n", i); |
| 495 | dump = 1; |
| 496 | } |
| 497 | } |
| 498 | } |
| 499 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 500 | if (dump) { |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 501 | dump_smi_status(smi_sts); |
| 502 | } |
Stefan Reinauer | 800379f | 2010-03-01 08:34:19 +0000 | [diff] [blame] | 503 | } |