Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <chip.h> |
| 4 | #include <cpu/intel/turbo.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci_def.h> |
| 7 | #include <option.h> |
| 8 | #include <types.h> |
| 9 | #include <variants.h> |
| 10 | |
| 11 | void devtree_update(void) |
| 12 | { |
| 13 | config_t *cfg = config_of_soc(); |
| 14 | |
| 15 | struct soc_power_limits_config *soc_conf_2core = |
| 16 | &cfg->power_limits_config[POWER_LIMITS_U_2_CORE]; |
| 17 | |
| 18 | struct soc_power_limits_config *soc_conf_4core = |
| 19 | &cfg->power_limits_config[POWER_LIMITS_U_4_CORE]; |
| 20 | |
| 21 | struct device *nic_dev = pcidev_on_root(0x14, 3); |
Sean Rhodes | 1b66bba | 2021-11-28 08:34:53 +0000 | [diff] [blame] | 22 | struct device *tbt_pci_dev = pcidev_on_root(0x07, 0); |
| 23 | struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2); |
| 24 | |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 25 | |
| 26 | /* Update PL1 & PL2 based on CMOS settings */ |
Angel Pons | 4b9ac2c9 | 2021-12-18 13:26:09 +0100 | [diff] [blame] | 27 | switch (get_power_profile(PP_POWER_SAVER)) { |
| 28 | case PP_POWER_SAVER: |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 29 | disable_turbo(); |
Sean Rhodes | 99d2d62 | 2022-05-26 21:04:10 +0100 | [diff] [blame^] | 30 | soc_conf_2core->tdp_pl1_override = 15; |
| 31 | soc_conf_4core->tdp_pl1_override = 15; |
| 32 | soc_conf_2core->tdp_pl2_override = 15; |
| 33 | soc_conf_4core->tdp_pl2_override = 15; |
| 34 | cfg->tcc_offset = 20; |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 35 | break; |
Angel Pons | 4b9ac2c9 | 2021-12-18 13:26:09 +0100 | [diff] [blame] | 36 | case PP_BALANCED: |
Sean Rhodes | 99d2d62 | 2022-05-26 21:04:10 +0100 | [diff] [blame^] | 37 | soc_conf_2core->tdp_pl1_override = 15; |
| 38 | soc_conf_4core->tdp_pl1_override = 15; |
| 39 | soc_conf_2core->tdp_pl2_override = 25; |
| 40 | soc_conf_4core->tdp_pl2_override = 25; |
| 41 | cfg->tcc_offset = 15; |
Angel Pons | 4b9ac2c9 | 2021-12-18 13:26:09 +0100 | [diff] [blame] | 42 | break; |
| 43 | case PP_PERFORMANCE: |
Sean Rhodes | 99d2d62 | 2022-05-26 21:04:10 +0100 | [diff] [blame^] | 44 | soc_conf_2core->tdp_pl1_override = 28; |
| 45 | soc_conf_4core->tdp_pl1_override = 28; |
| 46 | soc_conf_2core->tdp_pl2_override = 40; |
| 47 | soc_conf_4core->tdp_pl2_override = 40; |
| 48 | cfg->tcc_offset = 10; |
Angel Pons | 4b9ac2c9 | 2021-12-18 13:26:09 +0100 | [diff] [blame] | 49 | break; |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 50 | } |
| 51 | |
| 52 | /* Enable/Disable Wireless based on CMOS settings */ |
| 53 | if (get_uint_option("wireless", 1) == 0) |
| 54 | nic_dev->enabled = 0; |
| 55 | |
| 56 | /* Enable/Disable Webcam based on CMOS settings */ |
| 57 | if (get_uint_option("webcam", 1) == 0) |
| 58 | cfg->usb2_ports[3].enable = 0; |
Sean Rhodes | 1b66bba | 2021-11-28 08:34:53 +0000 | [diff] [blame] | 59 | |
| 60 | /* Enable/Disable Thunderbolt based on CMOS settings */ |
| 61 | if (get_uint_option("thunderbolt", 1) == 0) { |
| 62 | cfg->UsbTcPortEn = 0; |
| 63 | cfg->TcssXhciEn = 0; |
| 64 | cfg->TcssD3ColdDisable = 0; |
| 65 | tbt_pci_dev->enabled = 0; |
| 66 | tbt_dma_dev->enabled = 0; |
| 67 | } |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 68 | } |