Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 23 | #include <arch/acpi.h> |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 24 | #include <bootstate.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 25 | #include <cbmem.h> |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 26 | #include <console/console.h> |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 27 | #include <cpu/x86/smm.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 28 | #include <device/device.h> |
| 29 | #include <device/pci.h> |
| 30 | #include <device/pci_ids.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 31 | #include <pc80/mc146818rtc.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 32 | #include <romstage_handoff.h> |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 33 | #include <drivers/uart/uart8250reg.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 34 | |
| 35 | #include <baytrail/iomap.h> |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 36 | #include <baytrail/irq.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 37 | #include <baytrail/lpc.h> |
| 38 | #include <baytrail/nvs.h> |
| 39 | #include <baytrail/pci_devs.h> |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 40 | #include <baytrail/pmc.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 41 | #include <baytrail/ramstage.h> |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 42 | #include <baytrail/spi.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 43 | #include "chip.h" |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 44 | |
| 45 | static inline void |
| 46 | add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) |
| 47 | { |
| 48 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 49 | } |
| 50 | |
| 51 | static void sc_add_mmio_resources(device_t dev) |
| 52 | { |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 53 | add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 54 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 55 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 56 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 57 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 58 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 59 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 60 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 64 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 65 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 66 | |
| 67 | static inline int io_range_in_default(int base, int size) |
| 68 | { |
| 69 | /* Does it start above the range? */ |
| 70 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 71 | return 0; |
| 72 | |
| 73 | /* Is it entirely contained? */ |
| 74 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 75 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 76 | return 1; |
| 77 | |
| 78 | /* This will return not in range for partial overlaps. */ |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | /* |
| 83 | * Note: this function assumes there is no overlap with the default LPC device's |
| 84 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 85 | */ |
| 86 | static void sc_add_io_resource(device_t dev, int base, int size, int index) |
| 87 | { |
| 88 | struct resource *res; |
| 89 | |
| 90 | if (io_range_in_default(base, size)) |
| 91 | return; |
| 92 | |
| 93 | res = new_resource(dev, index); |
| 94 | res->base = base; |
| 95 | res->size = size; |
| 96 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 97 | } |
| 98 | |
| 99 | static void sc_add_io_resources(device_t dev) |
| 100 | { |
| 101 | struct resource *res; |
| 102 | |
| 103 | /* Add the default claimed IO range for the LPC device. */ |
| 104 | res = new_resource(dev, 0); |
| 105 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 106 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 107 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 108 | |
| 109 | /* GPIO */ |
| 110 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); |
| 111 | |
| 112 | /* ACPI */ |
| 113 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); |
| 114 | } |
| 115 | |
| 116 | static void sc_read_resources(device_t dev) |
| 117 | { |
| 118 | /* Get the normal PCI resources of this device. */ |
| 119 | pci_dev_read_resources(dev); |
| 120 | |
| 121 | /* Add non-standard MMIO resources. */ |
| 122 | sc_add_mmio_resources(dev); |
| 123 | |
| 124 | /* Add IO resources. */ |
| 125 | sc_add_io_resources(dev); |
| 126 | } |
| 127 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 128 | static void sc_rtc_init(void) |
| 129 | { |
| 130 | uint32_t gen_pmcon1; |
| 131 | int rtc_fail; |
| 132 | struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 133 | |
| 134 | if (ps != NULL) { |
| 135 | gen_pmcon1 = ps->gen_pmcon1; |
| 136 | } else { |
| 137 | gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); |
| 138 | } |
| 139 | |
| 140 | rtc_fail = !!(gen_pmcon1 & RPS); |
| 141 | |
| 142 | if (rtc_fail) { |
| 143 | printk(BIOS_DEBUG, "RTC failure.\n"); |
| 144 | } |
| 145 | |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 146 | cmos_init(rtc_fail); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 147 | } |
| 148 | |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 149 | /* |
| 150 | * The UART hardware loses power while in suspend. Because of this the kernel |
| 151 | * can hang because it doesn't re-initialize serial ports it is using for |
| 152 | * consoles at resume time. The following function configures the UART |
| 153 | * if the hardware is enabled though it may not be the correct baud rate |
| 154 | * or configuration. This is definitely a hack, but it helps the kernel |
| 155 | * along. |
| 156 | */ |
| 157 | static void com1_configure_resume(device_t dev) |
| 158 | { |
| 159 | const uint16_t port = 0x3f8; |
| 160 | |
| 161 | /* Is the UART I/O port eanbled? */ |
| 162 | if (!(pci_read_config32(dev, UART_CONT) & 1)) |
| 163 | return; |
| 164 | |
| 165 | /* Disable interrupts */ |
| 166 | outb(0x0, port + UART8250_IER); |
| 167 | |
| 168 | /* Enable FIFOs */ |
| 169 | outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR); |
| 170 | |
| 171 | /* assert DTR and RTS so the other end is happy */ |
| 172 | outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR); |
| 173 | |
| 174 | /* DLAB on */ |
| 175 | outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR); |
| 176 | |
| 177 | /* Set Baud Rate Divisor. 1 ==> 115200 Baud */ |
| 178 | outb(1, port + UART8250_DLL); |
| 179 | outb(0, port + UART8250_DLM); |
| 180 | |
| 181 | /* Set to 3 for 8N1 */ |
| 182 | outb(3, port + UART8250_LCR); |
| 183 | } |
| 184 | |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 185 | static void sc_init(device_t dev) |
| 186 | { |
| 187 | int i; |
| 188 | const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; |
| 189 | const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 190 | const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1; |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 191 | const unsigned long actl = ILB_BASE_ADDRESS + ACTL; |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 192 | const struct baytrail_irq_route *ir = &global_baytrail_irq_route; |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 193 | struct soc_intel_baytrail_config *config = dev->chip_info; |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 194 | |
| 195 | /* Set up the PIRQ PIC routing based on static config. */ |
| 196 | for (i = 0; i < NUM_PIRQS; i++) { |
| 197 | write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]); |
| 198 | } |
| 199 | /* Set up the per device PIRQ routing base on static config. */ |
| 200 | for (i = 0; i < NUM_IR_DEVS; i++) { |
| 201 | write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); |
| 202 | } |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 203 | |
| 204 | /* Route SCI to IRQ9 */ |
| 205 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 206 | |
| 207 | sc_rtc_init(); |
| 208 | |
| 209 | if (config->disable_slp_x_stretch_sus_fail) { |
| 210 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
| 211 | write32(gen_pmcon1, |
| 212 | read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 213 | } else { |
| 214 | write32(gen_pmcon1, |
| 215 | read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
| 216 | } |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 217 | |
| 218 | if (acpi_slp_type == 3) |
| 219 | com1_configure_resume(dev); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 220 | } |
| 221 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 222 | /* |
| 223 | * Common code for the south cluster devices. |
| 224 | */ |
| 225 | |
| 226 | /* Set bit in function disble register to hide this device. */ |
| 227 | static void sc_disable_devfn(device_t dev) |
| 228 | { |
| 229 | const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; |
| 230 | const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; |
| 231 | uint32_t mask = 0; |
| 232 | uint32_t mask2 = 0; |
| 233 | |
| 234 | switch (dev->path.pci.devfn) { |
| 235 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 236 | mask |= SDIO_DIS; |
| 237 | break; |
| 238 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 239 | mask |= SD_DIS; |
| 240 | break; |
| 241 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 242 | mask |= SATA_DIS; |
| 243 | break; |
| 244 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 245 | mask |= XHCI_DIS; |
| 246 | /* Disable super speed PHY when XHCI is not available. */ |
| 247 | mask2 |= USH_SS_PHY_DIS; |
| 248 | break; |
| 249 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 250 | mask |= LPE_DIS; |
| 251 | break; |
| 252 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 253 | mask |= MMC_DIS; |
| 254 | break; |
| 255 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 256 | mask |= SIO_DMA1_DIS; |
| 257 | break; |
| 258 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 259 | mask |= I2C1_DIS; |
| 260 | break; |
| 261 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 262 | mask |= I2C1_DIS; |
| 263 | break; |
| 264 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 265 | mask |= I2C3_DIS; |
| 266 | break; |
| 267 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 268 | mask |= I2C4_DIS; |
| 269 | break; |
| 270 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 271 | mask |= I2C5_DIS; |
| 272 | break; |
| 273 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 274 | mask |= I2C6_DIS; |
| 275 | break; |
| 276 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 277 | mask |= I2C7_DIS; |
| 278 | break; |
| 279 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
| 280 | mask |= TXE_DIS; |
| 281 | break; |
| 282 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 283 | mask |= HDA_DIS; |
| 284 | break; |
| 285 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 286 | mask |= PCIE_PORT1_DIS; |
| 287 | break; |
| 288 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 289 | mask |= PCIE_PORT2_DIS; |
| 290 | break; |
| 291 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 292 | mask |= PCIE_PORT3_DIS; |
| 293 | break; |
| 294 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 295 | mask |= PCIE_PORT4_DIS; |
| 296 | break; |
| 297 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 298 | mask |= EHCI_DIS; |
| 299 | break; |
| 300 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 301 | mask |= SIO_DMA2_DIS; |
| 302 | break; |
| 303 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 304 | mask |= PWM1_DIS; |
| 305 | break; |
| 306 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 307 | mask |= PWM2_DIS; |
| 308 | break; |
| 309 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 310 | mask |= HSUART1_DIS; |
| 311 | break; |
| 312 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 313 | mask |= HSUART2_DIS; |
| 314 | break; |
| 315 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 316 | mask |= SPI_DIS; |
| 317 | break; |
| 318 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 319 | mask2 |= SMBUS_DIS; |
| 320 | break; |
| 321 | } |
| 322 | |
| 323 | if (mask != 0) { |
| 324 | write32(func_dis, read32(func_dis) | mask); |
| 325 | /* Ensure posted write hits. */ |
| 326 | read32(func_dis); |
| 327 | } |
| 328 | |
| 329 | if (mask2 != 0) { |
| 330 | write32(func_dis2, read32(func_dis2) | mask2); |
| 331 | /* Ensure posted write hits. */ |
| 332 | read32(func_dis2); |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | static inline void set_d3hot_bits(device_t dev, int offset) |
| 337 | { |
| 338 | uint32_t reg8; |
| 339 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 340 | reg8 = pci_read_config8(dev, offset + 4); |
| 341 | reg8 |= 0x3; |
| 342 | pci_write_config8(dev, offset + 4, reg8); |
| 343 | } |
| 344 | |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 345 | /* Parts of the audio subsystem are powered by the HDA device. Therefore, one |
| 346 | * cannot put HDA into D3Hot. Instead perform this workaround to make some of |
| 347 | * the audio paths work for LPE audio. */ |
| 348 | static void hda_work_around(device_t dev) |
| 349 | { |
| 350 | unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; |
| 351 | |
| 352 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 353 | pci_write_config8(dev, 0x43, 0xd7); |
| 354 | |
| 355 | /* Need to set bit 0 of GCTL to take the device out of reset. However, |
| 356 | * that requires setting up the 64-bit BAR. */ |
| 357 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 358 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
| 359 | pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
| 360 | write32(gctl, read32(gctl) | 0x1); |
| 361 | pci_write_config8(dev, PCI_COMMAND, 0); |
| 362 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 363 | } |
| 364 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 365 | static int place_device_in_d3hot(device_t dev) |
| 366 | { |
| 367 | unsigned offset; |
| 368 | |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 369 | /* Parts of the HDA block are used for LPE audio as well. |
| 370 | * Therefore assume the HDA will never be put into D3Hot. */ |
| 371 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 372 | hda_work_around(dev); |
| 373 | return 0; |
| 374 | } |
| 375 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 376 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 377 | |
| 378 | if (offset != 0) { |
| 379 | set_d3hot_bits(dev, offset); |
| 380 | return 0; |
| 381 | } |
| 382 | |
| 383 | /* For some reason some of the devices don't have the capability |
| 384 | * pointer set correctly. Work around this by hard coding the offset. */ |
| 385 | switch (dev->path.pci.devfn) { |
| 386 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 387 | offset = 0x80; |
| 388 | break; |
| 389 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 390 | offset = 0x80; |
| 391 | break; |
| 392 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 393 | offset = 0x80; |
| 394 | break; |
| 395 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 396 | offset = 0x80; |
| 397 | break; |
| 398 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 399 | offset = 0x80; |
| 400 | break; |
| 401 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 402 | offset = 0x80; |
| 403 | break; |
| 404 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 405 | offset = 0x80; |
| 406 | break; |
| 407 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 408 | offset = 0x80; |
| 409 | break; |
| 410 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 411 | offset = 0x80; |
| 412 | break; |
| 413 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 414 | offset = 0x80; |
| 415 | break; |
| 416 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 417 | offset = 0x80; |
| 418 | break; |
| 419 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 420 | offset = 0x80; |
| 421 | break; |
| 422 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 423 | offset = 0x80; |
| 424 | break; |
| 425 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 426 | offset = 0x80; |
| 427 | break; |
| 428 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 429 | offset = 0x80; |
| 430 | break; |
| 431 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 432 | offset = 0x80; |
| 433 | break; |
| 434 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 435 | offset = 0x80; |
| 436 | break; |
| 437 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 438 | offset = 0x80; |
| 439 | break; |
| 440 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 441 | offset = 0x70; |
| 442 | break; |
| 443 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 444 | offset = 0x70; |
| 445 | break; |
| 446 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 447 | offset = 0x70; |
| 448 | break; |
| 449 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 450 | offset = 0x50; |
| 451 | break; |
| 452 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 453 | offset = 0x50; |
| 454 | break; |
| 455 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
Aaron Durbin | 1eae3ee | 2013-10-30 17:08:59 -0500 | [diff] [blame] | 456 | /* TXE cannot be placed in D3Hot. */ |
| 457 | return 0; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 458 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 459 | offset = 0xa0; |
| 460 | break; |
| 461 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 462 | offset = 0xa0; |
| 463 | break; |
| 464 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 465 | offset = 0xa0; |
| 466 | break; |
| 467 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 468 | offset = 0xa0; |
| 469 | break; |
| 470 | } |
| 471 | |
| 472 | if (offset != 0) { |
| 473 | set_d3hot_bits(dev, offset); |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | return -1; |
| 478 | } |
| 479 | |
| 480 | /* Common PCI device function disable. */ |
| 481 | void southcluster_enable_dev(device_t dev) |
| 482 | { |
| 483 | uint32_t reg32; |
| 484 | |
| 485 | if (!dev->enabled) { |
| 486 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 487 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 488 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 489 | dev_path(dev), slot, func); |
| 490 | |
| 491 | /* Ensure memory, io, and bus master are all disabled */ |
| 492 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 493 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 494 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 495 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 496 | |
| 497 | /* Place device in D3Hot */ |
| 498 | if (place_device_in_d3hot(dev) < 0) { |
| 499 | printk(BIOS_WARNING, |
| 500 | "Could not place %02x.%01x into D3Hot. " |
| 501 | "Keeping device visible.\n", slot, func); |
| 502 | return; |
| 503 | } |
| 504 | /* Disable this device if possible */ |
| 505 | sc_disable_devfn(dev); |
| 506 | } else { |
| 507 | /* Enable SERR */ |
| 508 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 509 | reg32 |= PCI_COMMAND_SERR; |
| 510 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 511 | } |
| 512 | } |
| 513 | |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 514 | static struct device_operations device_ops = { |
| 515 | .read_resources = sc_read_resources, |
| 516 | .set_resources = pci_dev_set_resources, |
| 517 | .enable_resources = NULL, |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 518 | .init = sc_init, |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 519 | .enable = southcluster_enable_dev, |
Duncan Laurie | 5d53554 | 2013-10-31 10:10:20 -0700 | [diff] [blame] | 520 | .scan_bus = scan_static_bus, |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 521 | .ops_pci = &soc_pci_ops, |
| 522 | }; |
| 523 | |
| 524 | static const struct pci_driver southcluster __pci_driver = { |
| 525 | .ops = &device_ops, |
| 526 | .vendor = PCI_VENDOR_ID_INTEL, |
| 527 | .device = LPC_DEVID, |
| 528 | }; |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 529 | |
| 530 | int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) |
| 531 | { |
| 532 | return -1; |
| 533 | } |
| 534 | |
| 535 | static void finalize_chipset(void *unused) |
| 536 | { |
| 537 | const unsigned long bcr = SPI_BASE_ADDRESS + BCR; |
| 538 | const unsigned long gcs = RCBA_BASE_ADDRESS + GCS; |
| 539 | const unsigned long gen_pmcon2 = PMC_BASE_ADDRESS + GEN_PMCON2; |
| 540 | const unsigned long etr = PMC_BASE_ADDRESS + ETR; |
| 541 | const unsigned long spi = SPI_BASE_ADDRESS; |
| 542 | struct spi_config cfg; |
| 543 | |
| 544 | /* Set the lock enable on the BIOS control register. */ |
| 545 | write32(bcr, read32(bcr) | BCR_LE); |
| 546 | |
| 547 | /* Set BIOS lock down bit controlling boot block size and swapping. */ |
| 548 | write32(gcs, read32(gcs) | BILD); |
| 549 | |
| 550 | /* Lock sleep stretching policy and set SMI lock. */ |
| 551 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 552 | |
| 553 | /* Set the CF9 lock. */ |
| 554 | write32(etr, read32(etr) | CF9LOCK); |
| 555 | |
| 556 | if (mainboard_get_spi_config(&cfg) < 0) { |
| 557 | printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); |
| 558 | } else { |
| 559 | write16(spi + PREOP, cfg.preop); |
| 560 | write16(spi + OPTYPE, cfg.optype); |
| 561 | write32(spi + OPMENU0, cfg.opmenu[0]); |
| 562 | write32(spi + OPMENU1, cfg.opmenu[1]); |
| 563 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 564 | write32(spi + UVSCC, cfg.uvscc); |
| 565 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 566 | } |
| 567 | |
| 568 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 569 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 570 | } |
| 571 | |
| 572 | BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { |
| 573 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, |
| 574 | finalize_chipset, NULL), |
| 575 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, |
| 576 | finalize_chipset, NULL), |
| 577 | }; |