Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 23 | #include <console/console.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <romstage_handoff.h> |
| 28 | |
| 29 | #include <baytrail/iomap.h> |
| 30 | #include <baytrail/lpc.h> |
| 31 | #include <baytrail/nvs.h> |
| 32 | #include <baytrail/pci_devs.h> |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 33 | #include <baytrail/pmc.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 34 | #include <baytrail/ramstage.h> |
| 35 | |
| 36 | static inline void |
| 37 | add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) |
| 38 | { |
| 39 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 40 | } |
| 41 | |
| 42 | static void sc_add_mmio_resources(device_t dev) |
| 43 | { |
| 44 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, 1024); |
| 45 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, 16 * 1024); |
| 46 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, 1024); |
| 47 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, 1024); |
| 48 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, 1024 * 1024); |
| 49 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, 2048); |
| 50 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, 1024); |
| 51 | } |
| 52 | |
| 53 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 54 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 55 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 56 | |
| 57 | static inline int io_range_in_default(int base, int size) |
| 58 | { |
| 59 | /* Does it start above the range? */ |
| 60 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 61 | return 0; |
| 62 | |
| 63 | /* Is it entirely contained? */ |
| 64 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 65 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 66 | return 1; |
| 67 | |
| 68 | /* This will return not in range for partial overlaps. */ |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * Note: this function assumes there is no overlap with the default LPC device's |
| 74 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 75 | */ |
| 76 | static void sc_add_io_resource(device_t dev, int base, int size, int index) |
| 77 | { |
| 78 | struct resource *res; |
| 79 | |
| 80 | if (io_range_in_default(base, size)) |
| 81 | return; |
| 82 | |
| 83 | res = new_resource(dev, index); |
| 84 | res->base = base; |
| 85 | res->size = size; |
| 86 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 87 | } |
| 88 | |
| 89 | static void sc_add_io_resources(device_t dev) |
| 90 | { |
| 91 | struct resource *res; |
| 92 | |
| 93 | /* Add the default claimed IO range for the LPC device. */ |
| 94 | res = new_resource(dev, 0); |
| 95 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 96 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 97 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 98 | |
| 99 | /* GPIO */ |
| 100 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); |
| 101 | |
| 102 | /* ACPI */ |
| 103 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); |
| 104 | } |
| 105 | |
| 106 | static void sc_read_resources(device_t dev) |
| 107 | { |
| 108 | /* Get the normal PCI resources of this device. */ |
| 109 | pci_dev_read_resources(dev); |
| 110 | |
| 111 | /* Add non-standard MMIO resources. */ |
| 112 | sc_add_mmio_resources(dev); |
| 113 | |
| 114 | /* Add IO resources. */ |
| 115 | sc_add_io_resources(dev); |
| 116 | } |
| 117 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 118 | /* |
| 119 | * Common code for the south cluster devices. |
| 120 | */ |
| 121 | |
| 122 | /* Set bit in function disble register to hide this device. */ |
| 123 | static void sc_disable_devfn(device_t dev) |
| 124 | { |
| 125 | const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; |
| 126 | const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; |
| 127 | uint32_t mask = 0; |
| 128 | uint32_t mask2 = 0; |
| 129 | |
| 130 | switch (dev->path.pci.devfn) { |
| 131 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 132 | mask |= SDIO_DIS; |
| 133 | break; |
| 134 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 135 | mask |= SD_DIS; |
| 136 | break; |
| 137 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 138 | mask |= SATA_DIS; |
| 139 | break; |
| 140 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 141 | mask |= XHCI_DIS; |
| 142 | /* Disable super speed PHY when XHCI is not available. */ |
| 143 | mask2 |= USH_SS_PHY_DIS; |
| 144 | break; |
| 145 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 146 | mask |= LPE_DIS; |
| 147 | break; |
| 148 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 149 | mask |= MMC_DIS; |
| 150 | break; |
| 151 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 152 | mask |= SIO_DMA1_DIS; |
| 153 | break; |
| 154 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 155 | mask |= I2C1_DIS; |
| 156 | break; |
| 157 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 158 | mask |= I2C1_DIS; |
| 159 | break; |
| 160 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 161 | mask |= I2C3_DIS; |
| 162 | break; |
| 163 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 164 | mask |= I2C4_DIS; |
| 165 | break; |
| 166 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 167 | mask |= I2C5_DIS; |
| 168 | break; |
| 169 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 170 | mask |= I2C6_DIS; |
| 171 | break; |
| 172 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 173 | mask |= I2C7_DIS; |
| 174 | break; |
| 175 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
| 176 | mask |= TXE_DIS; |
| 177 | break; |
| 178 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 179 | mask |= HDA_DIS; |
| 180 | break; |
| 181 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 182 | mask |= PCIE_PORT1_DIS; |
| 183 | break; |
| 184 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 185 | mask |= PCIE_PORT2_DIS; |
| 186 | break; |
| 187 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 188 | mask |= PCIE_PORT3_DIS; |
| 189 | break; |
| 190 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 191 | mask |= PCIE_PORT4_DIS; |
| 192 | break; |
| 193 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 194 | mask |= EHCI_DIS; |
| 195 | break; |
| 196 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 197 | mask |= SIO_DMA2_DIS; |
| 198 | break; |
| 199 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 200 | mask |= PWM1_DIS; |
| 201 | break; |
| 202 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 203 | mask |= PWM2_DIS; |
| 204 | break; |
| 205 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 206 | mask |= HSUART1_DIS; |
| 207 | break; |
| 208 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 209 | mask |= HSUART2_DIS; |
| 210 | break; |
| 211 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 212 | mask |= SPI_DIS; |
| 213 | break; |
| 214 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 215 | mask2 |= SMBUS_DIS; |
| 216 | break; |
| 217 | } |
| 218 | |
| 219 | if (mask != 0) { |
| 220 | write32(func_dis, read32(func_dis) | mask); |
| 221 | /* Ensure posted write hits. */ |
| 222 | read32(func_dis); |
| 223 | } |
| 224 | |
| 225 | if (mask2 != 0) { |
| 226 | write32(func_dis2, read32(func_dis2) | mask2); |
| 227 | /* Ensure posted write hits. */ |
| 228 | read32(func_dis2); |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | static inline void set_d3hot_bits(device_t dev, int offset) |
| 233 | { |
| 234 | uint32_t reg8; |
| 235 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 236 | reg8 = pci_read_config8(dev, offset + 4); |
| 237 | reg8 |= 0x3; |
| 238 | pci_write_config8(dev, offset + 4, reg8); |
| 239 | } |
| 240 | |
| 241 | static int place_device_in_d3hot(device_t dev) |
| 242 | { |
| 243 | unsigned offset; |
| 244 | |
| 245 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 246 | |
| 247 | if (offset != 0) { |
| 248 | set_d3hot_bits(dev, offset); |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | /* For some reason some of the devices don't have the capability |
| 253 | * pointer set correctly. Work around this by hard coding the offset. */ |
| 254 | switch (dev->path.pci.devfn) { |
| 255 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 256 | offset = 0x80; |
| 257 | break; |
| 258 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 259 | offset = 0x80; |
| 260 | break; |
| 261 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 262 | offset = 0x80; |
| 263 | break; |
| 264 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 265 | offset = 0x80; |
| 266 | break; |
| 267 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 268 | offset = 0x80; |
| 269 | break; |
| 270 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 271 | offset = 0x80; |
| 272 | break; |
| 273 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 274 | offset = 0x80; |
| 275 | break; |
| 276 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 277 | offset = 0x80; |
| 278 | break; |
| 279 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 280 | offset = 0x80; |
| 281 | break; |
| 282 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 283 | offset = 0x80; |
| 284 | break; |
| 285 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 286 | offset = 0x80; |
| 287 | break; |
| 288 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 289 | offset = 0x80; |
| 290 | break; |
| 291 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 292 | offset = 0x80; |
| 293 | break; |
| 294 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 295 | offset = 0x80; |
| 296 | break; |
| 297 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 298 | offset = 0x80; |
| 299 | break; |
| 300 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 301 | offset = 0x80; |
| 302 | break; |
| 303 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 304 | offset = 0x80; |
| 305 | break; |
| 306 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 307 | offset = 0x80; |
| 308 | break; |
| 309 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 310 | offset = 0x70; |
| 311 | break; |
| 312 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 313 | offset = 0x70; |
| 314 | break; |
| 315 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 316 | offset = 0x70; |
| 317 | break; |
| 318 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 319 | offset = 0x50; |
| 320 | break; |
| 321 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 322 | offset = 0x50; |
| 323 | break; |
| 324 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
| 325 | break; |
| 326 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 327 | offset = 0xa0; |
| 328 | break; |
| 329 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 330 | offset = 0xa0; |
| 331 | break; |
| 332 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 333 | offset = 0xa0; |
| 334 | break; |
| 335 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 336 | offset = 0xa0; |
| 337 | break; |
| 338 | } |
| 339 | |
| 340 | if (offset != 0) { |
| 341 | set_d3hot_bits(dev, offset); |
| 342 | return 0; |
| 343 | } |
| 344 | |
| 345 | return -1; |
| 346 | } |
| 347 | |
| 348 | /* Common PCI device function disable. */ |
| 349 | void southcluster_enable_dev(device_t dev) |
| 350 | { |
| 351 | uint32_t reg32; |
| 352 | |
| 353 | if (!dev->enabled) { |
| 354 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 355 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 356 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 357 | dev_path(dev), slot, func); |
| 358 | |
| 359 | /* Ensure memory, io, and bus master are all disabled */ |
| 360 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 361 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 362 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 363 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 364 | |
| 365 | /* Place device in D3Hot */ |
| 366 | if (place_device_in_d3hot(dev) < 0) { |
| 367 | printk(BIOS_WARNING, |
| 368 | "Could not place %02x.%01x into D3Hot. " |
| 369 | "Keeping device visible.\n", slot, func); |
| 370 | return; |
| 371 | } |
| 372 | /* Disable this device if possible */ |
| 373 | sc_disable_devfn(dev); |
| 374 | } else { |
| 375 | /* Enable SERR */ |
| 376 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 377 | reg32 |= PCI_COMMAND_SERR; |
| 378 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 379 | } |
| 380 | } |
| 381 | |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 382 | static struct device_operations device_ops = { |
| 383 | .read_resources = sc_read_resources, |
| 384 | .set_resources = pci_dev_set_resources, |
| 385 | .enable_resources = NULL, |
| 386 | .init = NULL, |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 387 | .enable = southcluster_enable_dev, |
Duncan Laurie | 5d53554 | 2013-10-31 10:10:20 -0700 | [diff] [blame^] | 388 | .scan_bus = scan_static_bus, |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 389 | .ops_pci = &soc_pci_ops, |
| 390 | }; |
| 391 | |
| 392 | static const struct pci_driver southcluster __pci_driver = { |
| 393 | .ops = &device_ops, |
| 394 | .vendor = PCI_VENDOR_ID_INTEL, |
| 395 | .device = LPC_DEVID, |
| 396 | }; |