Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This is a ramstage driver for the Intel Management Engine found in the |
| 24 | * 6-series chipset. It handles the required boot-time messages over the |
| 25 | * MMIO-based Management Engine Interface to tell the ME that the BIOS is |
| 26 | * finished with POST. Additional messages are defined for debug but are |
| 27 | * not used unless the console loglevel is high enough. |
| 28 | */ |
| 29 | |
| 30 | #include <arch/acpi.h> |
| 31 | #include <arch/hlt.h> |
| 32 | #include <arch/io.h> |
| 33 | #include <console/console.h> |
| 34 | #include <device/pci_ids.h> |
| 35 | #include <device/pci_def.h> |
| 36 | #include <string.h> |
| 37 | #include <delay.h> |
| 38 | |
| 39 | #ifdef __SMM__ |
| 40 | # include <arch/romcc_io.h> |
| 41 | # include <northbridge/intel/sandybridge/pcie_config.c> |
| 42 | #else |
| 43 | # include <device/device.h> |
| 44 | # include <device/pci.h> |
| 45 | #endif |
| 46 | |
| 47 | #include "me.h" |
| 48 | #include "pch.h" |
| 49 | |
| 50 | #if CONFIG_CHROMEOS |
| 51 | #include <vendorcode/google/chromeos/chromeos.h> |
Stefan Reinauer | 49058c0 | 2012-06-11 14:13:09 -0700 | [diff] [blame] | 52 | #include <vendorcode/google/chromeos/gnvs.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 53 | #endif |
| 54 | |
| 55 | #ifndef __SMM__ |
| 56 | /* Path that the BIOS should take based on ME state */ |
| 57 | static const char *me_bios_path_values[] = { |
| 58 | [ME_NORMAL_BIOS_PATH] = "Normal", |
| 59 | [ME_S3WAKE_BIOS_PATH] = "S3 Wake", |
| 60 | [ME_ERROR_BIOS_PATH] = "Error", |
| 61 | [ME_RECOVERY_BIOS_PATH] = "Recovery", |
| 62 | [ME_DISABLE_BIOS_PATH] = "Disable", |
| 63 | [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", |
| 64 | }; |
| 65 | static int intel_me_read_mbp(me_bios_payload *mbp_data); |
| 66 | #endif |
| 67 | |
| 68 | /* MMIO base address for MEI interface */ |
| 69 | static u32 mei_base_address; |
| 70 | |
| 71 | #if CONFIG_DEBUG_INTEL_ME |
| 72 | static void mei_dump(void *ptr, int dword, int offset, const char *type) |
| 73 | { |
| 74 | struct mei_csr *csr; |
| 75 | |
| 76 | printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); |
| 77 | |
| 78 | switch (offset) { |
| 79 | case MEI_H_CSR: |
| 80 | case MEI_ME_CSR_HA: |
| 81 | csr = ptr; |
| 82 | if (!csr) { |
| 83 | printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); |
| 84 | break; |
| 85 | } |
| 86 | printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " |
| 87 | "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, |
| 88 | csr->buffer_read_ptr, csr->buffer_write_ptr, |
| 89 | csr->ready, csr->reset, csr->interrupt_generate, |
| 90 | csr->interrupt_status, csr->interrupt_enable); |
| 91 | break; |
| 92 | case MEI_ME_CB_RW: |
| 93 | case MEI_H_CB_WW: |
| 94 | printk(BIOS_SPEW, "CB: 0x%08x\n", dword); |
| 95 | break; |
| 96 | default: |
| 97 | printk(BIOS_SPEW, "0x%08x\n", offset); |
| 98 | break; |
| 99 | } |
| 100 | } |
| 101 | #else |
| 102 | # define mei_dump(ptr,dword,offset,type) do {} while (0) |
| 103 | #endif |
| 104 | |
| 105 | /* |
| 106 | * ME/MEI access helpers using memcpy to avoid aliasing. |
| 107 | */ |
| 108 | |
| 109 | static inline void mei_read_dword_ptr(void *ptr, int offset) |
| 110 | { |
| 111 | u32 dword = read32(mei_base_address + offset); |
| 112 | memcpy(ptr, &dword, sizeof(dword)); |
| 113 | mei_dump(ptr, dword, offset, "READ"); |
| 114 | } |
| 115 | |
| 116 | static inline void mei_write_dword_ptr(void *ptr, int offset) |
| 117 | { |
| 118 | u32 dword = 0; |
| 119 | memcpy(&dword, ptr, sizeof(dword)); |
| 120 | write32(mei_base_address + offset, dword); |
| 121 | mei_dump(ptr, dword, offset, "WRITE"); |
| 122 | } |
| 123 | |
| 124 | #ifndef __SMM__ |
| 125 | static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) |
| 126 | { |
| 127 | u32 dword = pci_read_config32(dev, offset); |
| 128 | memcpy(ptr, &dword, sizeof(dword)); |
| 129 | mei_dump(ptr, dword, offset, "PCI READ"); |
| 130 | } |
| 131 | #endif |
| 132 | |
| 133 | static inline void read_host_csr(struct mei_csr *csr) |
| 134 | { |
| 135 | mei_read_dword_ptr(csr, MEI_H_CSR); |
| 136 | } |
| 137 | |
| 138 | static inline void write_host_csr(struct mei_csr *csr) |
| 139 | { |
| 140 | mei_write_dword_ptr(csr, MEI_H_CSR); |
| 141 | } |
| 142 | |
| 143 | static inline void read_me_csr(struct mei_csr *csr) |
| 144 | { |
| 145 | mei_read_dword_ptr(csr, MEI_ME_CSR_HA); |
| 146 | } |
| 147 | |
| 148 | static inline void write_cb(u32 dword) |
| 149 | { |
| 150 | write32(mei_base_address + MEI_H_CB_WW, dword); |
| 151 | mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); |
| 152 | } |
| 153 | |
| 154 | static inline u32 read_cb(void) |
| 155 | { |
| 156 | u32 dword = read32(mei_base_address + MEI_ME_CB_RW); |
| 157 | mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); |
| 158 | return dword; |
| 159 | } |
| 160 | |
| 161 | /* Wait for ME ready bit to be asserted */ |
| 162 | static int mei_wait_for_me_ready(void) |
| 163 | { |
| 164 | struct mei_csr me; |
| 165 | unsigned try = ME_RETRY; |
| 166 | |
| 167 | while (try--) { |
| 168 | read_me_csr(&me); |
| 169 | if (me.ready) |
| 170 | return 0; |
| 171 | udelay(ME_DELAY); |
| 172 | } |
| 173 | |
| 174 | printk(BIOS_ERR, "ME: failed to become ready\n"); |
| 175 | return -1; |
| 176 | } |
| 177 | |
| 178 | static void mei_reset(void) |
| 179 | { |
| 180 | struct mei_csr host; |
| 181 | |
| 182 | if (mei_wait_for_me_ready() < 0) |
| 183 | return; |
| 184 | |
| 185 | /* Reset host and ME circular buffers for next message */ |
| 186 | read_host_csr(&host); |
| 187 | host.reset = 1; |
| 188 | host.interrupt_generate = 1; |
| 189 | write_host_csr(&host); |
| 190 | |
| 191 | if (mei_wait_for_me_ready() < 0) |
| 192 | return; |
| 193 | |
| 194 | /* Re-init and indicate host is ready */ |
| 195 | read_host_csr(&host); |
| 196 | host.interrupt_generate = 1; |
| 197 | host.ready = 1; |
| 198 | host.reset = 0; |
| 199 | write_host_csr(&host); |
| 200 | } |
| 201 | |
| 202 | static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, |
| 203 | void *req_data) |
| 204 | { |
| 205 | struct mei_csr host; |
| 206 | unsigned ndata, n; |
| 207 | u32 *data; |
| 208 | |
| 209 | /* Number of dwords to write, ignoring MKHI */ |
| 210 | ndata = mei->length >> 2; |
| 211 | |
| 212 | /* Pad non-dword aligned request message length */ |
| 213 | if (mei->length & 3) |
| 214 | ndata++; |
| 215 | if (!ndata) { |
| 216 | printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); |
| 217 | return -1; |
| 218 | } |
| 219 | ndata++; /* Add MEI header */ |
| 220 | |
| 221 | /* |
| 222 | * Make sure there is still room left in the circular buffer. |
| 223 | * Reset the buffer pointers if the requested message will not fit. |
| 224 | */ |
| 225 | read_host_csr(&host); |
| 226 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 227 | printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); |
| 228 | mei_reset(); |
| 229 | read_host_csr(&host); |
| 230 | } |
| 231 | |
| 232 | /* |
| 233 | * This implementation does not handle splitting large messages |
| 234 | * across multiple transactions. Ensure the requested length |
| 235 | * will fit in the available circular buffer depth. |
| 236 | */ |
| 237 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 238 | printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", |
| 239 | ndata + 2, host.buffer_depth); |
| 240 | return -1; |
| 241 | } |
| 242 | |
| 243 | /* Write MEI header */ |
| 244 | mei_write_dword_ptr(mei, MEI_H_CB_WW); |
| 245 | ndata--; |
| 246 | |
| 247 | /* Write MKHI header */ |
| 248 | mei_write_dword_ptr(mkhi, MEI_H_CB_WW); |
| 249 | ndata--; |
| 250 | |
| 251 | /* Write message data */ |
| 252 | data = req_data; |
| 253 | for (n = 0; n < ndata; ++n) |
| 254 | write_cb(*data++); |
| 255 | |
| 256 | /* Generate interrupt to the ME */ |
| 257 | read_host_csr(&host); |
| 258 | host.interrupt_generate = 1; |
| 259 | write_host_csr(&host); |
| 260 | |
| 261 | /* Make sure ME is ready after sending request data */ |
| 262 | return mei_wait_for_me_ready(); |
| 263 | } |
| 264 | |
| 265 | static int mei_recv_msg(struct mkhi_header *mkhi, |
| 266 | void *rsp_data, int rsp_bytes) |
| 267 | { |
| 268 | struct mei_header mei_rsp; |
| 269 | struct mkhi_header mkhi_rsp; |
| 270 | struct mei_csr me, host; |
| 271 | unsigned ndata, n/*, me_data_len*/; |
| 272 | unsigned expected; |
| 273 | u32 *data; |
| 274 | |
| 275 | /* Total number of dwords to read from circular buffer */ |
| 276 | expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; |
| 277 | if (rsp_bytes & 3) |
| 278 | expected++; |
| 279 | |
| 280 | /* |
| 281 | * The interrupt status bit does not appear to indicate that the |
| 282 | * message has actually been received. Instead we wait until the |
| 283 | * expected number of dwords are present in the circular buffer. |
| 284 | */ |
| 285 | for (n = ME_RETRY; n; --n) { |
| 286 | read_me_csr(&me); |
| 287 | if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) |
| 288 | break; |
| 289 | udelay(ME_DELAY); |
| 290 | } |
| 291 | if (!n) { |
| 292 | printk(BIOS_ERR, "ME: timeout waiting for data: expected " |
| 293 | "%u, available %u\n", expected, |
| 294 | me.buffer_write_ptr - me.buffer_read_ptr); |
| 295 | return -1; |
| 296 | } |
| 297 | |
| 298 | /* Read and verify MEI response header from the ME */ |
| 299 | mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); |
| 300 | if (!mei_rsp.is_complete) { |
| 301 | printk(BIOS_ERR, "ME: response is not complete\n"); |
| 302 | return -1; |
| 303 | } |
| 304 | |
| 305 | /* Handle non-dword responses and expect at least MKHI header */ |
| 306 | ndata = mei_rsp.length >> 2; |
| 307 | if (mei_rsp.length & 3) |
| 308 | ndata++; |
| 309 | if (ndata != (expected - 1)) { |
| 310 | printk(BIOS_ERR, "ME: response is missing data %d != %d\n", |
| 311 | ndata, (expected - 1)); |
| 312 | return -1; |
| 313 | } |
| 314 | |
| 315 | /* Read and verify MKHI response header from the ME */ |
| 316 | mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); |
| 317 | if (!mkhi_rsp.is_response || |
| 318 | mkhi->group_id != mkhi_rsp.group_id || |
| 319 | mkhi->command != mkhi_rsp.command) { |
| 320 | printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," |
| 321 | "command %u ?= %u, is_response %u\n", mkhi->group_id, |
| 322 | mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, |
| 323 | mkhi_rsp.is_response); |
| 324 | return -1; |
| 325 | } |
| 326 | ndata--; /* MKHI header has been read */ |
| 327 | |
| 328 | /* Make sure caller passed a buffer with enough space */ |
| 329 | if (ndata != (rsp_bytes >> 2)) { |
| 330 | printk(BIOS_ERR, "ME: not enough room in response buffer: " |
| 331 | "%u != %u\n", ndata, rsp_bytes >> 2); |
| 332 | return -1; |
| 333 | } |
| 334 | |
| 335 | /* Read response data from the circular buffer */ |
| 336 | data = rsp_data; |
| 337 | for (n = 0; n < ndata; ++n) |
| 338 | *data++ = read_cb(); |
| 339 | |
| 340 | /* Tell the ME that we have consumed the response */ |
| 341 | read_host_csr(&host); |
| 342 | host.interrupt_status = 1; |
| 343 | host.interrupt_generate = 1; |
| 344 | write_host_csr(&host); |
| 345 | |
| 346 | return mei_wait_for_me_ready(); |
| 347 | } |
| 348 | |
| 349 | static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, |
| 350 | void *req_data, void *rsp_data, int rsp_bytes) |
| 351 | { |
| 352 | if (mei_send_msg(mei, mkhi, req_data) < 0) |
| 353 | return -1; |
| 354 | if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) |
| 355 | return -1; |
| 356 | return 0; |
| 357 | } |
| 358 | |
| 359 | /* Send END OF POST message to the ME */ |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame^] | 360 | static int mkhi_end_of_post(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 361 | { |
| 362 | struct mkhi_header mkhi = { |
| 363 | .group_id = MKHI_GROUP_ID_GEN, |
| 364 | .command = MKHI_END_OF_POST, |
| 365 | }; |
| 366 | struct mei_header mei = { |
| 367 | .is_complete = 1, |
| 368 | .host_address = MEI_HOST_ADDRESS, |
| 369 | .client_address = MEI_ADDRESS_MKHI, |
| 370 | .length = sizeof(mkhi), |
| 371 | }; |
| 372 | |
| 373 | u32 eop_ack; |
| 374 | |
| 375 | /* Send request and wait for response */ |
| 376 | printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); |
| 377 | if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { |
| 378 | printk(BIOS_ERR, "ME: END OF POST message failed\n"); |
| 379 | return -1; |
| 380 | } |
| 381 | |
| 382 | printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); |
| 383 | return 0; |
| 384 | } |
| 385 | |
| 386 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) |
| 387 | static inline void print_cap(const char *name, int state) |
| 388 | { |
| 389 | printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", |
| 390 | name, state ? " en" : "dis"); |
| 391 | } |
| 392 | |
| 393 | static void me_print_fw_version(mbp_fw_version_name *vers_name) |
| 394 | { |
| 395 | if (!vers_name->major_version) { |
| 396 | printk(BIOS_ERR, "ME: mbp missing version report\n"); |
| 397 | return; |
| 398 | } |
| 399 | |
| 400 | printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", |
| 401 | vers_name->major_version, vers_name->minor_version, |
| 402 | vers_name->hotfix_version, vers_name->build_version); |
| 403 | } |
| 404 | |
| 405 | /* Get ME Firmware Capabilities */ |
| 406 | static int mkhi_get_fwcaps(mefwcaps_sku *cap) |
| 407 | { |
| 408 | u32 rule_id = 0; |
| 409 | struct me_fwcaps cap_msg; |
| 410 | struct mkhi_header mkhi = { |
| 411 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 412 | .command = MKHI_FWCAPS_GET_RULE, |
| 413 | }; |
| 414 | struct mei_header mei = { |
| 415 | .is_complete = 1, |
| 416 | .host_address = MEI_HOST_ADDRESS, |
| 417 | .client_address = MEI_ADDRESS_MKHI, |
| 418 | .length = sizeof(mkhi) + sizeof(rule_id), |
| 419 | }; |
| 420 | |
| 421 | /* Send request and wait for response */ |
| 422 | if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) |
| 423 | < 0) { |
| 424 | printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); |
| 425 | return -1; |
| 426 | } |
| 427 | *cap = cap_msg.caps_sku; |
| 428 | return 0; |
| 429 | } |
| 430 | |
| 431 | /* Get ME Firmware Capabilities */ |
| 432 | static void me_print_fwcaps(mbp_fw_caps *caps_section) |
| 433 | { |
| 434 | mefwcaps_sku *cap = &caps_section->fw_capabilities; |
| 435 | if (!caps_section->available) { |
| 436 | printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); |
| 437 | if (mkhi_get_fwcaps(cap)) |
| 438 | return; |
| 439 | } |
| 440 | |
| 441 | print_cap("Full Network manageability", cap->full_net); |
| 442 | print_cap("Regular Network manageability", cap->std_net); |
| 443 | print_cap("Manageability", cap->manageability); |
| 444 | print_cap("Small business technology", cap->small_business); |
| 445 | print_cap("Level III manageability", cap->l3manageability); |
| 446 | print_cap("IntelR Anti-Theft (AT)", cap->intel_at); |
| 447 | print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); |
| 448 | print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); |
| 449 | print_cap("ICC Over Clocking", cap->icc_over_clocking); |
| 450 | print_cap("Protected Audio Video Path (PAVP)", cap->pavp); |
| 451 | print_cap("IPV6", cap->ipv6); |
| 452 | print_cap("KVM Remote Control (KVM)", cap->kvm); |
| 453 | print_cap("Outbreak Containment Heuristic (OCH)", cap->och); |
| 454 | print_cap("Virtual LAN (VLAN)", cap->vlan); |
| 455 | print_cap("TLS", cap->tls); |
| 456 | print_cap("Wireless LAN (WLAN)", cap->wlan); |
| 457 | } |
| 458 | #endif |
| 459 | |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame^] | 460 | #if CONFIG_CHROMEOS && 0 /* DISABLED */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 461 | /* Tell ME to issue a global reset */ |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame^] | 462 | static int mkhi_global_reset(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 463 | { |
| 464 | struct me_global_reset reset = { |
| 465 | .request_origin = GLOBAL_RESET_BIOS_POST, |
| 466 | .reset_type = CBM_RR_GLOBAL_RESET, |
| 467 | }; |
| 468 | struct mkhi_header mkhi = { |
| 469 | .group_id = MKHI_GROUP_ID_CBM, |
| 470 | .command = MKHI_GLOBAL_RESET, |
| 471 | }; |
| 472 | struct mei_header mei = { |
| 473 | .is_complete = 1, |
| 474 | .length = sizeof(mkhi) + sizeof(reset), |
| 475 | .host_address = MEI_HOST_ADDRESS, |
| 476 | .client_address = MEI_ADDRESS_MKHI, |
| 477 | }; |
| 478 | |
| 479 | /* Send request and wait for response */ |
| 480 | printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); |
| 481 | if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { |
| 482 | /* No response means reset will happen shortly... */ |
| 483 | hlt(); |
| 484 | } |
| 485 | |
| 486 | /* If the ME responded it rejected the reset request */ |
| 487 | printk(BIOS_ERR, "ME: Global Reset failed\n"); |
| 488 | return -1; |
| 489 | } |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame^] | 490 | #endif |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 491 | |
| 492 | #ifdef __SMM__ |
| 493 | |
Stefan Reinauer | 998f3a2 | 2012-06-11 15:15:46 -0700 | [diff] [blame^] | 494 | void intel_me8_finalize_smm(void) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 495 | { |
| 496 | struct me_hfs hfs; |
| 497 | u32 reg32; |
| 498 | |
| 499 | mei_base_address = |
| 500 | pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; |
| 501 | |
| 502 | /* S3 path will have hidden this device already */ |
| 503 | if (!mei_base_address || mei_base_address == 0xfffffff0) |
| 504 | return; |
| 505 | |
| 506 | /* Make sure ME is in a mode that expects EOP */ |
| 507 | reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); |
| 508 | memcpy(&hfs, ®32, sizeof(u32)); |
| 509 | |
| 510 | /* Abort and leave device alone if not normal mode */ |
| 511 | if (hfs.fpt_bad || |
| 512 | hfs.working_state != ME_HFS_CWS_NORMAL || |
| 513 | hfs.operation_mode != ME_HFS_MODE_NORMAL) |
| 514 | return; |
| 515 | |
| 516 | /* Try to send EOP command so ME stops accepting other commands */ |
| 517 | mkhi_end_of_post(); |
| 518 | |
| 519 | /* Make sure IO is disabled */ |
| 520 | reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); |
| 521 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 522 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 523 | pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); |
| 524 | |
| 525 | /* Hide the PCI device */ |
| 526 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 527 | } |
| 528 | |
| 529 | #else /* !__SMM__ */ |
| 530 | |
| 531 | /* Determine the path that we should take based on ME status */ |
| 532 | static me_bios_path intel_me_path(device_t dev) |
| 533 | { |
| 534 | me_bios_path path = ME_DISABLE_BIOS_PATH; |
| 535 | struct me_hfs hfs; |
| 536 | struct me_gmes gmes; |
| 537 | |
| 538 | #if CONFIG_HAVE_ACPI_RESUME |
| 539 | /* S3 wake skips all MKHI messages */ |
| 540 | if (acpi_slp_type == 3) { |
| 541 | return ME_S3WAKE_BIOS_PATH; |
| 542 | } |
| 543 | #endif |
| 544 | |
| 545 | pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); |
| 546 | pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); |
| 547 | |
| 548 | /* Check and dump status */ |
| 549 | intel_me_status(&hfs, &gmes); |
| 550 | |
| 551 | /* Check for valid firmware */ |
| 552 | if (hfs.fpt_bad) |
| 553 | return ME_ERROR_BIOS_PATH; |
| 554 | |
| 555 | /* Check Current Working State */ |
| 556 | switch (hfs.working_state) { |
| 557 | case ME_HFS_CWS_NORMAL: |
| 558 | path = ME_NORMAL_BIOS_PATH; |
| 559 | /* check if the MBP is ready */ |
| 560 | if (!gmes.mbp_rdy) { |
| 561 | printk(BIOS_CRIT, "%s: mbp is not ready!\n", |
| 562 | __FUNCTION__); |
| 563 | return ME_ERROR_BIOS_PATH; |
| 564 | } |
| 565 | break; |
| 566 | case ME_HFS_CWS_REC: |
| 567 | path = ME_RECOVERY_BIOS_PATH; |
| 568 | break; |
| 569 | default: |
| 570 | path = ME_DISABLE_BIOS_PATH; |
| 571 | break; |
| 572 | } |
| 573 | |
| 574 | /* Check Current Operation Mode */ |
| 575 | switch (hfs.operation_mode) { |
| 576 | case ME_HFS_MODE_NORMAL: |
| 577 | break; |
| 578 | case ME_HFS_MODE_DEBUG: |
| 579 | case ME_HFS_MODE_DIS: |
| 580 | case ME_HFS_MODE_OVER_JMPR: |
| 581 | case ME_HFS_MODE_OVER_MEI: |
| 582 | default: |
| 583 | path = ME_DISABLE_BIOS_PATH; |
| 584 | break; |
| 585 | } |
| 586 | |
| 587 | /* Check for any error code */ |
| 588 | if (hfs.error_code) |
| 589 | path = ME_ERROR_BIOS_PATH; |
| 590 | |
| 591 | return path; |
| 592 | } |
| 593 | |
| 594 | /* Prepare ME for MEI messages */ |
| 595 | static int intel_mei_setup(device_t dev) |
| 596 | { |
| 597 | struct resource *res; |
| 598 | struct mei_csr host; |
| 599 | u32 reg32; |
| 600 | |
| 601 | /* Find the MMIO base for the ME interface */ |
| 602 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 603 | if (!res || res->base == 0 || res->size == 0) { |
| 604 | printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); |
| 605 | return -1; |
| 606 | } |
| 607 | mei_base_address = res->base; |
| 608 | |
| 609 | /* Ensure Memory and Bus Master bits are set */ |
| 610 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 611 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 612 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 613 | |
| 614 | /* Clean up status for next message */ |
| 615 | read_host_csr(&host); |
| 616 | host.interrupt_generate = 1; |
| 617 | host.ready = 1; |
| 618 | host.reset = 0; |
| 619 | write_host_csr(&host); |
| 620 | |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | /* Read the Extend register hash of ME firmware */ |
| 625 | static int intel_me_extend_valid(device_t dev) |
| 626 | { |
| 627 | struct me_heres status; |
Stefan Reinauer | 49058c0 | 2012-06-11 14:13:09 -0700 | [diff] [blame] | 628 | u32 extend[8] = {0}; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 629 | int i, count = 0; |
| 630 | |
| 631 | pci_read_dword_ptr(dev, &status, PCI_ME_HERES); |
| 632 | if (!status.extend_feature_present) { |
| 633 | printk(BIOS_ERR, "ME: Extend Feature not present\n"); |
| 634 | return -1; |
| 635 | } |
| 636 | |
| 637 | if (!status.extend_reg_valid) { |
| 638 | printk(BIOS_ERR, "ME: Extend Register not valid\n"); |
| 639 | return -1; |
| 640 | } |
| 641 | |
| 642 | switch (status.extend_reg_algorithm) { |
| 643 | case PCI_ME_EXT_SHA1: |
| 644 | count = 5; |
| 645 | printk(BIOS_DEBUG, "ME: Extend SHA-1: "); |
| 646 | break; |
| 647 | case PCI_ME_EXT_SHA256: |
| 648 | count = 8; |
| 649 | printk(BIOS_DEBUG, "ME: Extend SHA-256: "); |
| 650 | break; |
| 651 | default: |
| 652 | printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", |
| 653 | status.extend_reg_algorithm); |
| 654 | return -1; |
| 655 | } |
| 656 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 657 | for (i = 0; i < count; ++i) { |
Stefan Reinauer | 49058c0 | 2012-06-11 14:13:09 -0700 | [diff] [blame] | 658 | extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); |
| 659 | printk(BIOS_DEBUG, "%08x", extend[i]); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 660 | } |
| 661 | printk(BIOS_DEBUG, "\n"); |
| 662 | |
Stefan Reinauer | 49058c0 | 2012-06-11 14:13:09 -0700 | [diff] [blame] | 663 | #if CONFIG_CHROMEOS |
| 664 | /* Save hash in NVS for the OS to verify */ |
| 665 | chromeos_set_me_hash(extend, count); |
| 666 | #endif |
| 667 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 668 | return 0; |
| 669 | } |
| 670 | |
| 671 | /* Hide the ME virtual PCI devices */ |
| 672 | static void intel_me_hide(device_t dev) |
| 673 | { |
| 674 | dev->enabled = 0; |
| 675 | pch_enable(dev); |
| 676 | } |
| 677 | |
| 678 | /* Check whether ME is present and do basic init */ |
| 679 | static void intel_me_init(device_t dev) |
| 680 | { |
| 681 | me_bios_path path = intel_me_path(dev); |
| 682 | me_bios_payload mbp_data; |
| 683 | |
| 684 | /* Do initial setup and determine the BIOS path */ |
| 685 | printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); |
| 686 | |
| 687 | switch (path) { |
| 688 | case ME_S3WAKE_BIOS_PATH: |
| 689 | intel_me_hide(dev); |
| 690 | break; |
| 691 | |
| 692 | case ME_NORMAL_BIOS_PATH: |
| 693 | /* Validate the extend register */ |
| 694 | if (intel_me_extend_valid(dev) < 0) |
| 695 | break; /* TODO: force recovery mode */ |
| 696 | |
| 697 | /* Prepare MEI MMIO interface */ |
| 698 | if (intel_mei_setup(dev) < 0) |
| 699 | break; |
| 700 | |
| 701 | if(intel_me_read_mbp(&mbp_data)) |
| 702 | break; |
| 703 | |
| 704 | #if CONFIG_CHROMEOS && 0 /* DISABLED */ |
| 705 | /* |
| 706 | * Unlock ME in recovery mode. |
| 707 | */ |
| 708 | if (recovery_mode_enabled()) { |
| 709 | /* Unlock ME flash region */ |
| 710 | mkhi_hmrfpo_enable(); |
| 711 | |
| 712 | /* Issue global reset */ |
| 713 | mkhi_global_reset(); |
| 714 | return; |
| 715 | } |
| 716 | #endif |
| 717 | |
| 718 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 719 | me_print_fw_version(&mbp_data.fw_version_name); |
| 720 | me_print_fwcaps(&mbp_data.fw_caps_sku); |
| 721 | #endif |
| 722 | /* Tell ME that BIOS is done */ |
| 723 | mkhi_end_of_post(); |
| 724 | /* Hide the virtual PCI device */ |
| 725 | intel_me_hide(dev); |
| 726 | break; |
| 727 | |
| 728 | case ME_ERROR_BIOS_PATH: |
| 729 | case ME_RECOVERY_BIOS_PATH: |
| 730 | case ME_DISABLE_BIOS_PATH: |
| 731 | case ME_FIRMWARE_UPDATE_BIOS_PATH: |
| 732 | /* |
| 733 | * TODO(dlaurie) Force recovery mode if ME is unhappy? |
| 734 | */ |
| 735 | break; |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 740 | { |
| 741 | if (!vendor || !device) { |
| 742 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 743 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 744 | } else { |
| 745 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 746 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 747 | } |
| 748 | } |
| 749 | |
| 750 | static struct pci_operations pci_ops = { |
| 751 | .set_subsystem = set_subsystem, |
| 752 | }; |
| 753 | |
| 754 | static struct device_operations device_ops = { |
| 755 | .read_resources = pci_dev_read_resources, |
| 756 | .set_resources = pci_dev_set_resources, |
| 757 | .enable_resources = pci_dev_enable_resources, |
| 758 | .init = intel_me_init, |
| 759 | .scan_bus = scan_static_bus, |
| 760 | .ops_pci = &pci_ops, |
| 761 | }; |
| 762 | |
| 763 | static const struct pci_driver intel_me __pci_driver = { |
| 764 | .ops = &device_ops, |
| 765 | .vendor = PCI_VENDOR_ID_INTEL, |
| 766 | .device = 0x1e3a, |
| 767 | }; |
| 768 | |
| 769 | /****************************************************************************** |
| 770 | * */ |
| 771 | static u32 me_to_host_words_pending(void) |
| 772 | { |
| 773 | struct mei_csr me; |
| 774 | read_me_csr(&me); |
| 775 | if (!me.ready) |
| 776 | return 0; |
| 777 | return (me.buffer_write_ptr - me.buffer_read_ptr) & |
| 778 | (me.buffer_depth - 1); |
| 779 | } |
| 780 | |
| 781 | #if 0 |
| 782 | /* This function is not yet being used, keep it in for the future. */ |
| 783 | static u32 host_to_me_words_room(void) |
| 784 | { |
| 785 | struct mei_csr csr; |
| 786 | |
| 787 | read_me_csr(&csr); |
| 788 | if (!csr.ready) |
| 789 | return 0; |
| 790 | |
| 791 | read_host_csr(&csr); |
| 792 | return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & |
| 793 | (csr.buffer_depth - 1); |
| 794 | } |
| 795 | #endif |
| 796 | /* |
| 797 | * mbp seems to be following its own flow, let's retrieve it in a dedicated |
| 798 | * function. |
| 799 | */ |
| 800 | static int intel_me_read_mbp(me_bios_payload *mbp_data) |
| 801 | { |
| 802 | mbp_header mbp_hdr; |
| 803 | mbp_item_header mbp_item_hdr; |
| 804 | u32 me2host_pending; |
| 805 | u32 mbp_item_id; |
| 806 | struct mei_csr host; |
| 807 | |
| 808 | me2host_pending = me_to_host_words_pending(); |
| 809 | if (!me2host_pending) { |
| 810 | printk(BIOS_ERR, "ME: no mbp data!\n"); |
| 811 | return -1; |
| 812 | } |
| 813 | |
| 814 | /* we know for sure that at least the header is there */ |
| 815 | mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); |
| 816 | |
| 817 | if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || |
| 818 | (me2host_pending < mbp_hdr.mbp_size)) { |
| 819 | printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" |
| 820 | " buffer contains %d words\n", |
| 821 | mbp_hdr.num_entries, mbp_hdr.mbp_size, |
| 822 | me2host_pending); |
| 823 | return -1; |
| 824 | } |
| 825 | |
| 826 | me2host_pending--; |
| 827 | memset(mbp_data, 0, sizeof(*mbp_data)); |
| 828 | |
| 829 | while (mbp_hdr.num_entries--) { |
| 830 | u32* copy_addr; |
| 831 | u32 copy_size, buffer_room; |
| 832 | void *p; |
| 833 | |
| 834 | if (!me2host_pending) { |
| 835 | printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", |
| 836 | mbp_hdr.num_entries + 1); |
| 837 | return -1; |
| 838 | } |
| 839 | |
| 840 | mei_read_dword_ptr(&mbp_item_hdr, MEI_ME_CB_RW); |
| 841 | |
| 842 | if (mbp_item_hdr.length > me2host_pending) { |
| 843 | printk(BIOS_ERR, "ME: insufficient mbp data %d " |
| 844 | "entries to go!\n", |
| 845 | mbp_hdr.num_entries + 1); |
| 846 | return -1; |
| 847 | } |
| 848 | |
| 849 | me2host_pending -= mbp_item_hdr.length; |
| 850 | |
| 851 | mbp_item_id = (((u32)mbp_item_hdr.item_id) << 8) + |
| 852 | mbp_item_hdr.app_id; |
| 853 | |
| 854 | copy_size = mbp_item_hdr.length - 1; |
| 855 | |
| 856 | #define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \ |
| 857 | buffer_room = sizeof(mbp_data->field) / sizeof(u32); \ |
| 858 | break; \ |
| 859 | } |
| 860 | |
| 861 | p = &mbp_item_hdr; |
| 862 | printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); |
| 863 | |
| 864 | switch(mbp_item_id) { |
| 865 | case 0x101: |
| 866 | SET_UP_COPY(fw_version_name); |
| 867 | |
| 868 | case 0x102: |
| 869 | SET_UP_COPY(icc_profile); |
| 870 | |
| 871 | case 0x103: |
| 872 | SET_UP_COPY(at_state); |
| 873 | |
| 874 | case 0x201: |
| 875 | mbp_data->fw_caps_sku.available = 1; |
| 876 | SET_UP_COPY(fw_caps_sku.fw_capabilities); |
| 877 | |
| 878 | case 0x301: |
| 879 | SET_UP_COPY(rom_bist_data); |
| 880 | |
| 881 | case 0x401: |
| 882 | SET_UP_COPY(platform_key); |
| 883 | |
| 884 | case 0x501: |
| 885 | mbp_data->fw_plat_type.available = 1; |
| 886 | SET_UP_COPY(fw_plat_type.rule_data); |
| 887 | |
| 888 | case 0x601: |
| 889 | SET_UP_COPY(mfsintegrity); |
| 890 | |
| 891 | default: |
| 892 | printk(BIOS_ERR, "ME: unknown mbp item id 0x%x!!!\n", |
| 893 | mbp_item_id); |
| 894 | return -1; |
| 895 | } |
| 896 | |
| 897 | if (buffer_room != copy_size) { |
| 898 | printk(BIOS_ERR, "ME: buffer room %d != %d copy size" |
| 899 | " for item 0x%x!!!\n", |
| 900 | buffer_room, copy_size, mbp_item_id); |
| 901 | return -1; |
| 902 | } |
| 903 | while(copy_size--) |
| 904 | *copy_addr++ = read_cb(); |
| 905 | } |
| 906 | |
| 907 | read_host_csr(&host); |
| 908 | host.interrupt_generate = 1; |
| 909 | write_host_csr(&host); |
| 910 | |
| 911 | { |
| 912 | int cntr = 0; |
| 913 | while(host.interrupt_generate) { |
| 914 | read_host_csr(&host); |
| 915 | cntr++; |
| 916 | } |
| 917 | printk(BIOS_SPEW, "ME: mbp read OK after %d cycles\n", cntr); |
| 918 | } |
| 919 | |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | #endif /* !__SMM__ */ |