Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* NOTE: This handler assumes the SMM window goes from 0xa0000 |
| 18 | * to 0xaffff. In fact, at least on Intel Core CPUs (i945 chipset) |
| 19 | * the SMM window is 128K big, covering 0xa0000 to 0xbffff. |
| 20 | * So there is a lot of potential for growth in here. Let's stick |
| 21 | * to 64k if we can though. |
| 22 | */ |
| 23 | |
Elyes HAOUAS | a9473ec | 2018-10-24 15:55:53 +0200 | [diff] [blame] | 24 | #include <cpu/x86/lapic_def.h> |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 25 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 26 | /* |
| 27 | * +--------------------------------+ 0xaffff |
| 28 | * | Save State Map Node 0 | |
| 29 | * | Save State Map Node 1 | |
| 30 | * | Save State Map Node 2 | |
| 31 | * | Save State Map Node 3 | |
| 32 | * | ... | |
| 33 | * +--------------------------------+ 0xaf000 |
| 34 | * | | |
| 35 | * | | |
| 36 | * | | |
| 37 | * +--------------------------------+ 0xa8400 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 38 | * | SMM Entry Node 0 (+ stack) | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 39 | * +--------------------------------+ 0xa8000 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 40 | * | SMM Entry Node 1 (+ stack) | |
| 41 | * | SMM Entry Node 2 (+ stack) | |
| 42 | * | SMM Entry Node 3 (+ stack) | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 43 | * | ... | |
| 44 | * +--------------------------------+ 0xa7400 |
| 45 | * | | |
| 46 | * | SMM Handler | |
| 47 | * | | |
| 48 | * +--------------------------------+ 0xa0000 |
| 49 | * |
| 50 | */ |
| 51 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 52 | /* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG |
| 53 | * at which smm_handler_start lives. At the moment the handler |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 54 | * lives right at 0xa0000, so the offset is 0. |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 55 | */ |
| 56 | |
| 57 | #define SMM_HANDLER_OFFSET 0x0000 |
| 58 | |
| 59 | /* initially SMM is some sort of real mode. Let gcc know |
| 60 | * how to treat the SMM handler stub |
| 61 | */ |
| 62 | |
| 63 | .section ".handler", "a", @progbits |
| 64 | |
| 65 | .code16 |
| 66 | |
| 67 | /** |
| 68 | * SMM code to enable protected mode and jump to the |
| 69 | * C-written function void smi_handler(u32 smm_revision) |
| 70 | * |
| 71 | * All the bad magic is not all that bad after all. |
| 72 | */ |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 73 | #define SMM_START 0xa0000 |
| 74 | #define SMM_END 0xb0000 |
| 75 | #if SMM_END <= SMM_START |
| 76 | #error invalid SMM configuration |
| 77 | #endif |
Aaron Durbin | e73dae4 | 2015-03-29 22:16:55 -0500 | [diff] [blame] | 78 | .global smm_handler_start |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 79 | smm_handler_start: |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 80 | #if IS_ENABLED(CONFIG_SMM_LAPIC_REMAP_MITIGATION) |
| 81 | /* Check if the LAPIC register block overlaps with SMM. |
| 82 | * This block needs to work without data accesses because they |
| 83 | * may be routed into the LAPIC register block. |
| 84 | * Code accesses, on the other hand, are never routed to LAPIC, |
| 85 | * which is what makes this work in the first place. |
| 86 | */ |
| 87 | mov $LAPIC_BASE_MSR, %ecx |
| 88 | rdmsr |
| 89 | and $(~0xfff), %eax |
| 90 | sub $(SMM_START), %eax |
| 91 | cmp $(SMM_END - SMM_START), %eax |
| 92 | ja untampered_lapic |
| 93 | 1: |
| 94 | /* emit "Crash" on serial */ |
| 95 | mov $(CONFIG_TTYS0_BASE), %dx |
| 96 | mov $'C', %al |
| 97 | out %al, (%dx) |
| 98 | mov $'r', %al |
| 99 | out %al, (%dx) |
| 100 | mov $'a', %al |
| 101 | out %al, (%dx) |
| 102 | mov $'s', %al |
| 103 | out %al, (%dx) |
| 104 | mov $'h', %al |
| 105 | out %al, (%dx) |
| 106 | /* now crash for real */ |
| 107 | ud2 |
| 108 | untampered_lapic: |
| 109 | #endif |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 110 | movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx |
Edward O'Callaghan | 4e2294b | 2017-01-08 19:14:42 +1100 | [diff] [blame] | 111 | lgdtl %cs:(%bx) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 112 | |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 113 | movl %cr0, %eax |
| 114 | andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ |
| 115 | orl $0x60000001, %eax /* CD, NW, PE = 1 */ |
| 116 | movl %eax, %cr0 |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 117 | |
| 118 | /* Enable protected mode */ |
Edward O'Callaghan | 4e2294b | 2017-01-08 19:14:42 +1100 | [diff] [blame] | 119 | ljmpl $0x08, $1f |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 120 | |
| 121 | .code32 |
| 122 | 1: |
Stefan Reinauer | 3128685 | 2011-10-15 11:23:04 -0700 | [diff] [blame] | 123 | /* flush the cache after disabling it */ |
| 124 | wbinvd |
| 125 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 126 | /* Use flat data segment */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 127 | movw $0x10, %ax |
| 128 | movw %ax, %ds |
| 129 | movw %ax, %es |
| 130 | movw %ax, %ss |
| 131 | movw %ax, %fs |
| 132 | movw %ax, %gs |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 133 | |
| 134 | /* Get this CPU's LAPIC ID */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 135 | movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi |
| 136 | movl (%esi), %ecx |
| 137 | shr $24, %ecx |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 138 | |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 139 | /* This is an ugly hack, and we should find a way to read the CPU index |
| 140 | * without relying on the LAPIC ID. |
| 141 | */ |
Kyösti Mälkki | 6acaca7 | 2017-07-25 15:12:12 +0300 | [diff] [blame] | 142 | #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 143 | /* LAPIC IDs start from 0x10; map that to the proper core index */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 144 | subl $0x10, %ecx |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 145 | #endif |
| 146 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 147 | /* calculate stack offset by multiplying the APIC ID |
| 148 | * by 1024 (0x400), and save that offset in ebp. |
| 149 | */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 150 | shl $10, %ecx |
| 151 | movl %ecx, %ebp |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 152 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 153 | /* We put the stack for each core right above |
| 154 | * its SMM entry point. Core 0 starts at 0xa8000, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 155 | * we spare 0x10 bytes for the jump to be sure. |
| 156 | */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 157 | movl $0xa8010, %eax |
| 158 | subl %ecx, %eax /* subtract offset, see above */ |
| 159 | movl %eax, %ebx /* Save bottom of stack in ebx */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 160 | |
| 161 | #define SMM_STACK_SIZE (0x400 - 0x10) |
| 162 | /* clear stack */ |
| 163 | cld |
| 164 | movl %eax, %edi |
| 165 | movl $(SMM_STACK_SIZE >> 2), %ecx |
| 166 | xorl %eax, %eax |
| 167 | rep stosl |
| 168 | |
| 169 | /* set new stack */ |
| 170 | addl $SMM_STACK_SIZE, %ebx |
| 171 | movl %ebx, %esp |
| 172 | |
| 173 | /* Get SMM revision */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 174 | movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ |
| 175 | subl %ebp, %ebx /* subtract core X offset */ |
| 176 | movl (%ebx), %eax |
| 177 | pushl %eax |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 178 | |
| 179 | /* Call 32bit C handler */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 180 | call smi_handler |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 181 | |
| 182 | /* To return, just do rsm. It will "clean up" protected mode */ |
| 183 | rsm |
| 184 | |
| 185 | .code16 |
| 186 | |
| 187 | .align 4, 0xff |
| 188 | |
| 189 | smm_gdtptr16: |
| 190 | .word smm_gdt_end - smm_gdt - 1 |
| 191 | .long smm_gdt - smm_handler_start + 0xa0000 + SMM_HANDLER_OFFSET |
| 192 | |
| 193 | .code32 |
| 194 | |
| 195 | smm_gdt: |
| 196 | /* The first GDT entry can not be used. Keep it zero */ |
| 197 | .long 0x00000000, 0x00000000 |
| 198 | |
| 199 | /* gdt selector 0x08, flat code segment */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 200 | .word 0xffff, 0x0000 |
| 201 | .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 202 | |
| 203 | /* gdt selector 0x10, flat data segment */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 204 | .word 0xffff, 0x0000 |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 205 | .byte 0x00, 0x93, 0xcf, 0x00 |
| 206 | |
| 207 | smm_gdt_end: |
| 208 | |
| 209 | |
| 210 | .section ".jumptable", "a", @progbits |
| 211 | |
| 212 | /* This is the SMM jump table. All cores use the same SMM handler |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 213 | * for simplicity. But SMM Entry needs to be different due to the |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 214 | * save state area. The jump table makes sure all CPUs jump into the |
| 215 | * real handler on SMM entry. |
| 216 | */ |
| 217 | |
| 218 | /* This code currently supports up to 4 CPU cores. If more than 4 CPU cores |
| 219 | * shall be used, below table has to be updated, as well as smm.ld |
| 220 | */ |
| 221 | |
| 222 | /* GNU AS/LD will always generate code that assumes CS is 0xa000. In reality |
| 223 | * CS will be set to SMM_BASE[19:4] though. Knowing that the smm handler is the |
| 224 | * first thing in the ASEG, we do a far jump here, to set CS to 0xa000. |
| 225 | */ |
| 226 | |
| 227 | .code16 |
| 228 | jumptable: |
| 229 | /* core 3 */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 230 | ljmp $0xa000, $SMM_HANDLER_OFFSET |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 231 | .align 1024, 0x00 |
| 232 | /* core 2 */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 233 | ljmp $0xa000, $SMM_HANDLER_OFFSET |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 234 | .align 1024, 0x00 |
| 235 | /* core 1 */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 236 | ljmp $0xa000, $SMM_HANDLER_OFFSET |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 237 | .align 1024, 0x00 |
| 238 | /* core 0 */ |
Elyes HAOUAS | 9981df3 | 2018-12-22 09:26:28 +0100 | [diff] [blame^] | 239 | ljmp $0xa000, $SMM_HANDLER_OFFSET |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 240 | .align 1024, 0x00 |