Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de> |
| 6 | * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> |
| 7 | * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
Patrick Rudolph | 9bd6015 | 2018-05-04 09:01:38 +0200 | [diff] [blame] | 21 | #include <console/console.h> |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 22 | #include <device/device.h> |
| 23 | #include <device/pnp.h> |
Patrick Rudolph | 9bd6015 | 2018-05-04 09:01:38 +0200 | [diff] [blame] | 24 | #include <option.h> |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 25 | #include <pc80/keyboard.h> |
| 26 | #include <stdlib.h> |
| 27 | #include <superio/conf_mode.h> |
| 28 | |
| 29 | #include "npcd378.h" |
| 30 | |
Patrick Rudolph | 9bd6015 | 2018-05-04 09:01:38 +0200 | [diff] [blame] | 31 | uint8_t npcd378_hwm_read(const uint16_t iobase, const uint16_t reg) |
| 32 | { |
| 33 | outb((reg >> 8) & 0xf, iobase + 0xff); |
| 34 | uint8_t reg8 = inb(iobase + (reg & 0xff)); |
| 35 | if (reg8 == 0xff) |
| 36 | reg8 = inb(iobase + (reg & 0xff)); |
| 37 | |
| 38 | outb(0, iobase + 0xff); |
| 39 | return reg8; |
| 40 | } |
| 41 | |
| 42 | void npcd378_hwm_write(const uint16_t iobase, const uint16_t reg, |
| 43 | const uint8_t val) |
| 44 | { |
| 45 | outb((reg >> 8) & 0xf, iobase + 0xff); |
| 46 | outb(val, iobase + (reg & 0xff)); |
| 47 | |
| 48 | outb(0, iobase + 0xff); |
| 49 | } |
| 50 | |
| 51 | void npcd378_hwm_write_start(const uint16_t iobase) |
| 52 | { |
| 53 | u8 reg8 = npcd378_hwm_read(iobase, NPCD837_HWM_WRITE_LOCK_CTRL); |
| 54 | reg8 &= ~NPCD837_HWM_WRITE_LOCK_BIT; |
| 55 | npcd378_hwm_write(iobase, NPCD837_HWM_WRITE_LOCK_CTRL, reg8); |
| 56 | } |
| 57 | |
| 58 | void npcd378_hwm_write_finished(const uint16_t iobase) |
| 59 | { |
| 60 | u8 reg8 = npcd378_hwm_read(iobase, NPCD837_HWM_WRITE_LOCK_CTRL); |
| 61 | reg8 |= NPCD837_HWM_WRITE_LOCK_BIT; |
| 62 | npcd378_hwm_write(iobase, NPCD837_HWM_WRITE_LOCK_CTRL, reg8); |
| 63 | } |
| 64 | |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 65 | static void npcd378_init(struct device *dev) |
| 66 | { |
Patrick Rudolph | 9bd6015 | 2018-05-04 09:01:38 +0200 | [diff] [blame] | 67 | struct resource *res; |
| 68 | uint8_t pwm, fan_lvl; |
| 69 | |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 70 | if (!dev->enabled) |
| 71 | return; |
| 72 | |
| 73 | switch (dev->path.pnp.device) { |
Patrick Rudolph | 9bd6015 | 2018-05-04 09:01:38 +0200 | [diff] [blame] | 74 | /* TODO: Might potentially need code for FDC etc. */ |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 75 | case NPCD378_KBC: |
| 76 | pc_keyboard_init(PROBE_AUX_DEVICE); |
| 77 | break; |
Patrick Rudolph | 9bd6015 | 2018-05-04 09:01:38 +0200 | [diff] [blame] | 78 | case NPCD378_HWM: |
| 79 | res = find_resource(dev, PNP_IDX_IO0); |
| 80 | if (!res || !res->base) { |
| 81 | printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n", |
| 82 | NPCD378_HWM); |
| 83 | break; |
| 84 | } |
| 85 | |
| 86 | npcd378_hwm_write_start(res->base); |
| 87 | |
| 88 | if (!get_option(&fan_lvl, "psu_fan_lvl") || fan_lvl > 7) |
| 89 | fan_lvl = 3; |
| 90 | |
| 91 | pwm = NPCD378_HWM_PSU_FAN_MIN + |
| 92 | (NPCD378_HWM_PSU_FAN_MAX - NPCD378_HWM_PSU_FAN_MIN) * |
| 93 | fan_lvl / 7; |
| 94 | |
| 95 | /* Set PSU fan PWM lvl */ |
| 96 | npcd378_hwm_write(res->base, NPCD378_HWM_PSU_FAN_PWM_CTRL, pwm); |
| 97 | printk(BIOS_INFO, "NPCD378: PSU fan PWM 0x%02x\n", pwm); |
| 98 | |
| 99 | npcd378_hwm_write_finished(res->base); |
| 100 | break; |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 101 | } |
| 102 | } |
| 103 | |
| 104 | static struct device_operations ops = { |
| 105 | .read_resources = pnp_read_resources, |
| 106 | .set_resources = pnp_set_resources, |
| 107 | .enable_resources = pnp_enable_resources, |
| 108 | .enable = pnp_alt_enable, |
| 109 | .init = npcd378_init, |
| 110 | .ops_pnp_mode = &pnp_conf_mode_8787_aa, |
| 111 | }; |
| 112 | |
| 113 | static struct pnp_info pnp_dev_info[] = { |
Felix Held | 9911d64 | 2018-07-06 20:55:53 +0200 | [diff] [blame^] | 114 | { NULL, NPCD378_FDC, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, }, |
| 115 | { NULL, NPCD378_PP, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, }, |
| 116 | { NULL, NPCD378_SP1, PNP_IO0|PNP_IRQ0, 0x0ff8, }, |
| 117 | { NULL, NPCD378_SP2, PNP_IO0|PNP_IRQ0, 0x0ff8, }, |
| 118 | { NULL, NPCD378_PWR, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0| |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 119 | PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7| |
| 120 | PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, |
| 121 | 0x0ff8, 0x0ff8}, |
Felix Held | 9911d64 | 2018-07-06 20:55:53 +0200 | [diff] [blame^] | 122 | { NULL, NPCD378_AUX, PNP_IRQ0, 0x0fff, 0x0fff, }, |
| 123 | { NULL, NPCD378_KBC, PNP_IO0|PNP_IO1|PNP_IRQ0, |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 124 | 0x0fff, 0x0fff, }, |
Felix Held | 9911d64 | 2018-07-06 20:55:53 +0200 | [diff] [blame^] | 125 | { NULL, NPCD378_WDT1, PNP_IO0|PNP_MSC8|PNP_MSC9| |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 126 | PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, 0x0ff8}, |
Felix Held | 9911d64 | 2018-07-06 20:55:53 +0200 | [diff] [blame^] | 127 | { NULL, NPCD378_HWM, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3| |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 128 | PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_IRQ0, 0x0ff8}, |
Felix Held | 9911d64 | 2018-07-06 20:55:53 +0200 | [diff] [blame^] | 129 | { NULL, NPCD378_GPIO_PP_OD, PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3| |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 130 | PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_MSC8|PNP_MSC9|PNP_MSCA| |
| 131 | PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE}, |
Felix Held | 9911d64 | 2018-07-06 20:55:53 +0200 | [diff] [blame^] | 132 | { NULL, NPCD378_I2C, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0| |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 133 | PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7| |
| 134 | PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, |
| 135 | 0x0ff8, 0x0ff8}, |
Felix Held | 9911d64 | 2018-07-06 20:55:53 +0200 | [diff] [blame^] | 136 | { NULL, NPCD378_SUSPEND, PNP_IO0, 0x0ff8 }, |
| 137 | { NULL, NPCD378_GPIOA, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3| |
Patrick Rudolph | 4576600 | 2018-03-27 15:58:38 +0200 | [diff] [blame] | 138 | PNP_MSC4, 0x0ff8}, |
| 139 | }; |
| 140 | |
| 141 | static void enable_dev(struct device *dev) |
| 142 | { |
| 143 | pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); |
| 144 | } |
| 145 | |
| 146 | struct chip_operations superio_nuvoton_npcd378_ops = { |
| 147 | CHIP_NAME("NUVOTON NPCD378 Super I/O") |
| 148 | .enable_dev = enable_dev, |
| 149 | }; |