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review.coreboot.org / coreboot / 98fcc09cf9955e24376d15f6fe13f02545547276 / . / src / southbridge / amd / sr5650 / cmn.h
blob: e94fcddc864f2bf7febfab94f88afb732d5e1467 [file] [log] [blame]
Zheng Bao98fcc092011-03-27 16:39:58 +0000[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __SR5650_CMN_H__
21#define __SR5650_CMN_H__
22
23#define NBMISC_INDEX 0x60
24#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
25#define NBMC_INDEX 0xE8
26#define NBPCIE_INDEX 0xE0
27#define EXT_CONF_BASE_ADDRESS 0xE0000000
28#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
29
30static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
31{
32 pci_write_config32(dev, index_reg, index);
33 return pci_read_config32(dev, index_reg + 0x4);
34}
35
36static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
37{
38 pci_write_config32(dev, index_reg, index);
39 pci_write_config32(dev, index_reg + 0x4, data);
40}
41
42static inline u32 nbmisc_read_index(device_t nb_dev, u32 index)
43{
44 return nb_read_index((nb_dev), NBMISC_INDEX, (index));
45}
46
47static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
48{
49 nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
50}
51
52static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
53 u32 val)
54{
55 u32 reg_old, reg;
56 reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
57 reg &= ~mask;
58 reg |= val;
59 if (reg != reg_old) {
60 nbmisc_write_index(nb_dev, reg_pos, reg);
61 }
62}
63
64static inline u32 htiu_read_index(device_t nb_dev, u32 index)
65{
66 return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
67}
68
69static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data)
70{
71 nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
72}
73
74static inline u32 nbmc_read_index(device_t nb_dev, u32 index)
75{
76 return nb_read_index((nb_dev), NBMC_INDEX, (index));
77}
78
79static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
80{
81 nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
82}
83
84static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
85 u32 val)
86{
87 u32 reg_old, reg;
88 reg = reg_old = htiu_read_index(nb_dev, reg_pos);
89 reg &= ~mask;
90 reg |= val;
91 if (reg != reg_old) {
92 htiu_write_index(nb_dev, reg_pos, reg);
93 }
94}
95
96static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
97 u32 val)
98{
99 u32 reg_old, reg;
100 reg = reg_old = pci_read_config32(nb_dev, reg_pos);
101 reg &= ~mask;
102 reg |= val;
103 if (reg != reg_old) {
104 pci_write_config32(nb_dev, reg_pos, reg);
105 }
106}
107
108static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
109 u8 val)
110{
111 u8 reg_old, reg;
112 reg = reg_old = pci_read_config8(nb_dev, reg_pos);
113 reg &= ~mask;
114 reg |= val;
115 if (reg != reg_old) {
116 pci_write_config8(nb_dev, reg_pos, reg);
117 }
118}
119
120static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
121 u32 val)
122{
123 u32 reg_old, reg;
124 reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
125 reg &= ~mask;
126 reg |= val;
127 if (reg != reg_old) {
128 nbmc_write_index(nb_dev, reg_pos, reg);
129 }
130}
131
132static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
133{
134 u32 reg_old, reg;
135 reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
136 reg &= ~mask;
137 reg |= val;
138 if (reg != reg_old) {
139 nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
140 }
141}
142#endif /* __SR5650_CMN_H__ */