blob: e38f845042807860295d60d47dc7f71979422b6a [file] [log] [blame]
Pavel Sayekat98d5a862019-07-01 19:53:29 +06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 * Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
6 * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
7 * Copyright (C) 2015 Matt DeVillier <matt.devillier@gmail.com>
8 * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot@gmail.com>
9* Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <device/device.h>
23#include <device/pnp.h>
24#include <pc80/keyboard.h>
25#include <stdlib.h>
26#include <superio/conf_mode.h>
27
28#include "nct5539d.h"
29
30
31static void nct5539d_init(struct device *dev)
32{
33 if (!dev->enabled)
34 return;
35
36 switch (dev->path.pnp.device) {
37 case NCT5539D_KBC:
38 pc_keyboard_init(NO_AUX_DEVICE);
39 break;
40 }
41}
42
43static struct device_operations ops = {
44 .read_resources = pnp_read_resources,
45 .set_resources = pnp_set_resources,
46 .enable_resources = pnp_enable_resources,
47 .enable = pnp_alt_enable,
48 .init = nct5539d_init,
49 .ops_pnp_mode = &pnp_conf_mode_8787_aa,
50};
51
52static struct pnp_info pnp_dev_info[] = {
53 { NULL, NCT5539D_SP1, PNP_IO0 | PNP_IRQ0,
54 0x0ff8, },
55 { NULL, NCT5539D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
56 0x0fff, 0x0fff, },
57 { NULL, NCT5539D_CIR, PNP_IO0 | PNP_IRQ0,
58 0x0ff8, },
59 { NULL, NCT5539D_ACPI},
60 { NULL, NCT5539D_HWM_FPLED, PNP_IO0 | PNP_IRQ0,
61 0x0ffe, 0x0ffe, },
62 { NULL, NCT5539D_WDT2},
63 { NULL, NCT5539D_CIRWUP, PNP_IO0 | PNP_IRQ0,
64 0x0ff8, },
65 { NULL, NCT5539D_GPIO_PP_OD},
66 { NULL, NCT5539D_WDT1},
67 { NULL, NCT5539D_WDT3},
68 { NULL, NCT5539D_GPIOBASE, PNP_IO0,
69 0x0ff8, },
70 { NULL, NCT5539D_GPIO0},
71 { NULL, NCT5539D_GPIO2},
72 { NULL, NCT5539D_GPIO3},
73 { NULL, NCT5539D_GPIO4},
74 { NULL, NCT5539D_GPIO5},
75 { NULL, NCT5539D_GPIO7},
76 { NULL, NCT5539D_GPIO8},
77 { NULL, NCT5539D_GPIO_PSO},
78 { NULL, NCT5539D_SWEC},
79 { NULL, NCT5539D_FLED},
80 { NULL, NCT5539D_DS5},
81 { NULL, NCT5539D_DS3},
82};
83
84static void enable_dev(struct device *dev)
85{
86 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
87}
88
89struct chip_operations superio_nuvoton_nct5539d_ops = {
90 CHIP_NAME("NUVOTON NCT5539D Super I/O")
91 .enable_dev = enable_dev,
92};