Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 16 | #include <cbmem.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <stdint.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 22 | #include <stdlib.h> |
| 23 | #include <string.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 24 | #include <cpu/cpu.h> |
| 25 | #include <boot/tables.h> |
| 26 | #include <arch/acpi.h> |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 27 | #include <cpu/intel/smm/gen1/smi.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 28 | #include "chip.h" |
| 29 | #include "gm45.h" |
Vladimir Serbinenko | 06667a5 | 2014-08-12 09:07:13 +0200 | [diff] [blame] | 30 | #include "arch/acpi.h" |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 31 | |
Vladimir Serbinenko | 8c22057 | 2014-08-16 14:18:21 +0200 | [diff] [blame] | 32 | /* Reserve segments A and B: |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 33 | * |
| 34 | * 0xa0000 - 0xbffff: legacy VGA |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 35 | */ |
| 36 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
Vladimir Serbinenko | 8c22057 | 2014-08-16 14:18:21 +0200 | [diff] [blame] | 37 | static const int legacy_hole_size_k = 128; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 38 | |
| 39 | static int decode_pcie_bar(u32 *const base, u32 *const len) |
| 40 | { |
| 41 | *base = 0; |
| 42 | *len = 0; |
| 43 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 44 | struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 45 | if (!dev) |
| 46 | return 0; |
| 47 | |
| 48 | const u32 pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); |
| 49 | |
| 50 | if (!(pciexbar_reg & (1 << 0))) |
| 51 | return 0; |
| 52 | |
| 53 | switch ((pciexbar_reg >> 1) & 3) { |
| 54 | case 0: /* 256MB */ |
| 55 | *base = pciexbar_reg & (0x0f << 28); |
| 56 | *len = 256 * 1024 * 1024; |
| 57 | return 1; |
| 58 | case 1: /* 128M */ |
| 59 | *base = pciexbar_reg & (0x1f << 27); |
| 60 | *len = 128 * 1024 * 1024; |
| 61 | return 1; |
| 62 | case 2: /* 64M */ |
| 63 | *base = pciexbar_reg & (0x3f << 26); |
| 64 | *len = 64 * 1024 * 1024; |
| 65 | return 1; |
| 66 | } |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 71 | static void mch_domain_read_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 72 | { |
| 73 | u64 tom, touud; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 74 | u32 tomk, tolud, uma_sizek = 0, delta_cbmem; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 75 | u32 pcie_config_base, pcie_config_size; |
| 76 | |
| 77 | /* Total Memory 2GB example: |
| 78 | * |
| 79 | * 00000000 0000MB-2014MB 2014MB RAM (writeback) |
| 80 | * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached) |
| 81 | * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached) |
| 82 | * 80000000 2048MB TOLUD |
| 83 | * 80000000 2048MB TOM |
| 84 | * |
| 85 | * Total Memory 4GB example: |
| 86 | * |
| 87 | * 00000000 0000MB-3038MB 3038MB RAM (writeback) |
| 88 | * bde00000 3038MB-3040MB 2MB GFX GTT (uncached) |
| 89 | * be000000 3040MB-3072MB 32MB GFX UMA (uncached) |
| 90 | * be000000 3072MB TOLUD |
| 91 | * 100000000 4096MB TOM |
| 92 | * 100000000 4096MB-5120MB 1024MB RAM (writeback) |
| 93 | * 140000000 5120MB TOUUD |
| 94 | */ |
| 95 | |
| 96 | pci_domain_read_resources(dev); |
| 97 | |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 98 | struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 99 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 100 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 101 | touud = pci_read_config16(mch, D0F0_TOUUD); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 102 | touud <<= 20; |
| 103 | |
| 104 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 105 | tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 106 | tolud <<= 16; |
| 107 | |
| 108 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 109 | tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 110 | tom <<= 27; |
| 111 | |
| 112 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 113 | touud, tolud, tom); |
| 114 | |
| 115 | tomk = tolud >> 10; |
| 116 | |
| 117 | /* Graphics memory comes next */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 118 | const u16 ggc = pci_read_config16(mch, D0F0_GGC); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 119 | if (!(ggc & 2)) { |
| 120 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 121 | |
| 122 | /* Graphics memory */ |
| 123 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 124 | printk(BIOS_DEBUG, "%uM UMA, ", gms_sizek >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 125 | tomk -= gms_sizek; |
| 126 | |
| 127 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 128 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 129 | printk(BIOS_DEBUG, "%uM GTT", gsm_sizek >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 130 | tomk -= gsm_sizek; |
| 131 | |
| 132 | uma_sizek = gms_sizek + gsm_sizek; |
| 133 | } |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 134 | const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 135 | const u32 tseg_sizek = decode_tseg_size(esmramc); |
| 136 | printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10); |
| 137 | tomk -= tseg_sizek; |
| 138 | uma_sizek += tseg_sizek; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 139 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 140 | /* cbmem_top can be shifted downwards due to alignment. |
| 141 | Mark the region between cbmem_top and tomk as unusable */ |
| 142 | delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); |
| 143 | tomk -= delta_cbmem; |
| 144 | uma_sizek += delta_cbmem; |
| 145 | |
| 146 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", |
| 147 | delta_cbmem); |
| 148 | |
Nico Huber | ca3e121 | 2017-10-02 20:07:53 +0200 | [diff] [blame] | 149 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 150 | |
| 151 | /* Report the memory regions */ |
| 152 | ram_resource(dev, 3, 0, legacy_hole_base_k); |
| 153 | ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, |
Nico Huber | ca3e121 | 2017-10-02 20:07:53 +0200 | [diff] [blame] | 154 | (tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 155 | |
| 156 | /* |
| 157 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 158 | * is remapped above TOM, TOUUD will account for both |
| 159 | */ |
| 160 | touud >>= 10; /* Convert to KB */ |
| 161 | if (touud > 4096 * 1024) { |
| 162 | ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); |
| 163 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
| 164 | (touud >> 10) - 4096); |
| 165 | } |
| 166 | |
| 167 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " |
| 168 | "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); |
| 169 | /* Don't use uma_resource() as our UMA touches the PCI hole. */ |
| 170 | fixed_mem_resource(dev, 6, tomk, uma_sizek, IORESOURCE_RESERVE); |
| 171 | |
| 172 | if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { |
| 173 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 174 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 175 | fixed_mem_resource(dev, 7, pcie_config_base >> 10, |
| 176 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 177 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 178 | } |
| 179 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 180 | static void mch_domain_set_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 181 | { |
| 182 | struct resource *resource; |
| 183 | int i; |
| 184 | |
| 185 | for (i = 3; i < 8; ++i) { |
| 186 | /* Report read resources. */ |
Vladimir Serbinenko | 40412c6 | 2014-11-12 00:09:20 +0100 | [diff] [blame] | 187 | resource = probe_resource(dev, i); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 188 | if (resource) |
| 189 | report_resource_stored(dev, resource, ""); |
| 190 | } |
| 191 | |
| 192 | assign_resources(dev->link_list); |
| 193 | } |
| 194 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 195 | static void mch_domain_init(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 196 | { |
| 197 | u32 reg32; |
| 198 | |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 199 | struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 200 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 201 | /* Enable SERR */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 202 | reg32 = pci_read_config32(mch, PCI_COMMAND); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 203 | reg32 |= PCI_COMMAND_SERR; |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 204 | pci_write_config32(mch, PCI_COMMAND, reg32); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 205 | } |
| 206 | |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 207 | static const char *northbridge_acpi_name(const struct device *dev) |
| 208 | { |
| 209 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 210 | return "PCI0"; |
| 211 | |
| 212 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 213 | return NULL; |
| 214 | |
| 215 | switch (dev->path.pci.devfn) { |
| 216 | case PCI_DEVFN(0, 0): |
| 217 | return "MCHC"; |
| 218 | } |
| 219 | |
| 220 | return NULL; |
| 221 | } |
| 222 | |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 223 | void northbridge_write_smram(u8 smram) |
| 224 | { |
Arthur Heymans | 48fa922 | 2018-11-19 13:08:01 +0100 | [diff] [blame] | 225 | struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 226 | |
| 227 | if (dev == NULL) |
| 228 | die("could not find pci 00:00.0!\n"); |
| 229 | |
| 230 | pci_write_config8(dev, D0F0_SMRAM, smram); |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | /* |
| 234 | * Really doesn't belong here but will go away with parallel mp init, |
| 235 | * so let it be here for a while... |
| 236 | */ |
| 237 | int cpu_get_apic_id_map(int *apic_id_map) |
| 238 | { |
| 239 | unsigned int i; |
| 240 | |
| 241 | /* Logical processors (threads) per core */ |
| 242 | const struct cpuid_result cpuid1 = cpuid(1); |
| 243 | /* Read number of cores. */ |
| 244 | const char cores = (cpuid1.ebx >> 16) & 0xf; |
| 245 | |
| 246 | /* TODO in parallel MP cpuid(1).ebx */ |
| 247 | for (i = 0; i < cores; i++) |
| 248 | apic_id_map[i] = i; |
| 249 | |
| 250 | return cores; |
| 251 | } |
| 252 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 253 | static struct device_operations pci_domain_ops = { |
| 254 | .read_resources = mch_domain_read_resources, |
| 255 | .set_resources = mch_domain_set_resources, |
| 256 | .enable_resources = NULL, |
| 257 | .init = mch_domain_init, |
| 258 | .scan_bus = pci_domain_scan_bus, |
Vladimir Serbinenko | 33769a5 | 2014-08-30 22:39:20 +0200 | [diff] [blame] | 259 | .write_acpi_tables = northbridge_write_acpi_tables, |
| 260 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 261 | .acpi_name = northbridge_acpi_name, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 262 | }; |
| 263 | |
| 264 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 265 | static void cpu_bus_init(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 266 | { |
| 267 | initialize_cpus(dev->link_list); |
| 268 | } |
| 269 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 270 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 271 | .read_resources = DEVICE_NOOP, |
| 272 | .set_resources = DEVICE_NOOP, |
| 273 | .enable_resources = DEVICE_NOOP, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 274 | .init = cpu_bus_init, |
| 275 | .scan_bus = 0, |
| 276 | }; |
| 277 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 278 | static void enable_dev(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 279 | { |
| 280 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 281 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 282 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 283 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 284 | dev->ops = &cpu_bus_ops; |
| 285 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | static void gm45_init(void *const chip_info) |
| 289 | { |
| 290 | int dev, fn, bit_base; |
| 291 | |
| 292 | struct device *const d0f0 = dev_find_slot(0, 0); |
| 293 | |
| 294 | /* Hide internal functions based on devicetree info. */ |
| 295 | for (dev = 3; dev > 0; --dev) { |
| 296 | switch (dev) { |
| 297 | case 3: /* ME */ |
| 298 | fn = 3; |
| 299 | bit_base = 6; |
| 300 | break; |
| 301 | case 2: /* IGD */ |
| 302 | fn = 1; |
| 303 | bit_base = 3; |
| 304 | break; |
| 305 | case 1: /* PEG */ |
| 306 | fn = 0; |
| 307 | bit_base = 1; |
| 308 | break; |
| 309 | } |
| 310 | for (; fn >= 0; --fn) { |
| 311 | const struct device *const d = |
| 312 | dev_find_slot(0, PCI_DEVFN(dev, fn)); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 313 | if (!d || d->enabled) continue; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 314 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 315 | pci_write_config32(d0f0, D0F0_DEVEN, |
| 316 | deven & ~(1 << (bit_base + fn))); |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 321 | if (!(deven & (0xf << 6))) |
| 322 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 323 | } |
| 324 | |
| 325 | struct chip_operations northbridge_intel_gm45_ops = { |
| 326 | CHIP_NAME("Intel GM45 Northbridge") |
| 327 | .enable_dev = enable_dev, |
| 328 | .init = gm45_init, |
| 329 | }; |