Tim Crawford | 930dbc0 | 2023-05-16 12:41:31 -0600 | [diff] [blame] | 1 | chip soc/intel/alderlake |
| 2 | device domain 0 on |
| 3 | subsystemid 0x1558 0x5630 inherit |
| 4 | |
| 5 | device ref xhci on |
Felix Singer | 983b169 | 2023-10-26 16:14:34 +0200 | [diff] [blame^] | 6 | register "usb2_ports" = "{ |
| 7 | [2] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 (USB 3.1 Gen2) */ |
| 8 | [4] = USB2_PORT_MID(OC_SKIP), /* Type-A (USB 3.1 Gen2) */ |
| 9 | [5] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC2 (USB 3.1 Gen2) */ |
| 10 | [6] = USB2_PORT_MID(OC_SKIP), /* Finger */ |
| 11 | [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ |
| 12 | [8] = USB2_PORT_MID(OC_SKIP), /* Type-A */ |
| 13 | [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ |
| 14 | }" |
| 15 | register "usb3_ports" = "{ |
| 16 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A (USB 3.1 Gen2) */ |
| 17 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC2 */ |
| 18 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 */ |
| 19 | [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 */ |
| 20 | }" |
Tim Crawford | 930dbc0 | 2023-05-16 12:41:31 -0600 | [diff] [blame] | 21 | end |
| 22 | |
| 23 | device ref i2c0 on |
| 24 | # Touchpad I2C bus |
| 25 | register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" |
| 26 | chip drivers/i2c/hid |
| 27 | register "generic.hid" = ""ELAN0412"" |
| 28 | register "generic.desc" = ""ELAN Touchpad"" |
| 29 | register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" |
| 30 | register "generic.detect" = "1" |
| 31 | register "hid_desc_reg_offset" = "0x01" |
| 32 | device i2c 15 on end |
| 33 | end |
| 34 | chip drivers/i2c/hid |
| 35 | register "generic.hid" = ""FTCS1000"" |
| 36 | register "generic.desc" = ""FocalTech Touchpad"" |
| 37 | register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" |
| 38 | register "generic.detect" = "1" |
| 39 | register "hid_desc_reg_offset" = "0x01" |
| 40 | device i2c 38 on end |
| 41 | end |
| 42 | end |
| 43 | |
| 44 | device ref pcie5_0 on |
| 45 | # CPU PCIe RP#2 x8, Clock 3 (GPU) |
| 46 | register "cpu_pcie_rp[CPU_RP(2)]" = "{ |
| 47 | .clk_src = 3, |
| 48 | .clk_req = 3, |
| 49 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 50 | }" |
| 51 | end |
| 52 | device ref pcie4_0 on |
| 53 | # CPU RP#1 x4, Clock 0 (SSD0) |
| 54 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 55 | .clk_src = 0, |
| 56 | .clk_req = 0, |
| 57 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 58 | }" |
| 59 | end |
| 60 | device ref pcie_rp5 on |
| 61 | # PCH RP#5 x4, Clock 1 (SSD1) |
| 62 | register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| 63 | .clk_src = 1, |
| 64 | .clk_req = 1, |
| 65 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 66 | }" |
| 67 | end |
| 68 | device ref pcie_rp9 on |
| 69 | # PCH RP#9 x1, Clock 6 (GLAN) |
| 70 | register "pch_pcie_rp[PCH_RP(9)]" = "{ |
| 71 | .clk_src = 6, |
| 72 | .clk_req = 6, |
| 73 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 74 | }" |
| 75 | device pci 00.0 on end |
| 76 | end |
| 77 | device ref pcie_rp10 on |
| 78 | # PCH RP#10 x1, Clock 2 (WLAN) |
| 79 | register "pch_pcie_rp[PCH_RP(10)]" = "{ |
| 80 | .clk_src = 2, |
| 81 | .clk_req = 2, |
| 82 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 83 | }" |
| 84 | end |
| 85 | device ref pcie_rp11 on |
| 86 | # PCH RP#11 x1, Clock 5 (CARD) |
| 87 | register "pch_pcie_rp[PCH_RP(11)]" = "{ |
| 88 | .clk_src = 5, |
| 89 | .clk_req = 5, |
| 90 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 91 | }" |
| 92 | end |
| 93 | end |
| 94 | end |