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review.coreboot.org / coreboot / 97e21d3e956ea2657a63fb98c22548f9fd52afef / . / src / northbridge / intel / haswell / chip.h
blob: 99102b67707c0e65df7875cd44718545eaa30d4c [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]2
Iru Caid7ee9dd2016-02-24 15:03:58 +0800[diff] [blame]3#ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H
4#define NORTHBRIDGE_INTEL_HASWELL_CHIP_H
5
Michael Niewöhner97e21d32020-12-28 00:49:33 +0100[diff] [blame^]6#include <drivers/intel/gma/gma.h>
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +0100[diff] [blame]7
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]8/*
9 * Digital Port Hotplug Enable:
Angel Pons1db5bc72020-01-15 00:49:03 +0100[diff] [blame]10 * 0x04 = Enabled, 2ms short pulse
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]11 * 0x05 = Enabled, 4.5ms short pulse
Angel Pons1db5bc72020-01-15 00:49:03 +0100[diff] [blame]12 * 0x06 = Enabled, 6ms short pulse
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]13 * 0x07 = Enabled, 100ms short pulse
14 */
15struct northbridge_intel_haswell_config {
16 u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
17 u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
18 u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
19
Michael Niewöhner97e21d32020-12-28 00:49:33 +0100[diff] [blame^]20 /* IGD panel configuration */
21 struct i915_gpu_panel_config panel_cfg;
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +0100[diff] [blame]22
Tristan Corrick1a73eb02018-10-31 02:27:29 +1300[diff] [blame]23 bool gpu_ddi_e_connected;
24
Angel Pons8aab7872020-07-04 01:24:59 +0200[diff] [blame]25 bool ec_present;
26
27 bool dq_pins_interleaved;
28
29 bool usb_xhci_on_resume;
30
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +0100[diff] [blame]31 struct i915_gpu_controller_info gfx;
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]32};
33
Iru Caid7ee9dd2016-02-24 15:03:58 +0800[diff] [blame]34#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */