Rex-BC Chen | 9c098e2 | 2021-06-29 09:44:31 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2 | |
| 3 | //----------------------------------------------------------------------------- |
| 4 | // Include files |
| 5 | //----------------------------------------------------------------------------- |
| 6 | #include "dramc_common.h" |
| 7 | #include "dramc_int_global.h" |
| 8 | #include "x_hal_io.h" |
| 9 | #include "sv_c_data_traffic.h" |
| 10 | #if (FOR_DV_SIMULATION_USED == 0) |
| 11 | #include "dramc_top.h" |
| 12 | #endif |
| 13 | |
| 14 | #define BITMAP_BITS_MAX 128 |
| 15 | |
| 16 | #define MAX_CLK_PI_DELAY 31 |
| 17 | |
| 18 | #define PASS_RANGE_NA 0x7fff |
| 19 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 20 | #define DIE_NUM_MAX 1 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 21 | static U8 fgwrlevel_done = 0; |
| 22 | |
| 23 | #if __ETT__ |
| 24 | U8 gETT_WHILE_1_flag = 1; |
| 25 | #endif |
| 26 | //#define CBT_NEW_PAT_DEBUG |
| 27 | |
| 28 | U8 u1MR01Value[FSP_MAX]; |
| 29 | U8 u1MR02Value[FSP_MAX]; |
| 30 | U8 u1MR03Value[FSP_MAX]; |
| 31 | U8 u1MR11Value[FSP_MAX]; |
| 32 | U8 u1MR18Value[FSP_MAX]; |
| 33 | U8 u1MR19Value[FSP_MAX]; |
| 34 | U8 u1MR20Value[FSP_MAX]; |
| 35 | U8 u1MR21Value[FSP_MAX]; |
| 36 | U8 u1MR22Value[FSP_MAX]; |
| 37 | U8 u1MR51Value[FSP_MAX]; |
| 38 | |
| 39 | U8 u1MR04Value[RANK_MAX]; |
| 40 | U8 u1MR13Value[RANK_MAX]; |
| 41 | U8 u1MR26Value[RANK_MAX]; |
| 42 | U8 u1MR30Value[RANK_MAX]; |
| 43 | |
| 44 | U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; |
| 45 | U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; |
| 46 | U16 gu2MR0_Value[RANK_MAX] = {0xffff, 0xffff}; |
| 47 | |
| 48 | #if PINMUX_AUTO_TEST_PER_BIT_RX |
| 49 | S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; |
| 50 | #endif |
| 51 | #if PINMUX_AUTO_TEST_PER_BIT_TX |
| 52 | S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; |
| 53 | #endif |
| 54 | #if PINMUX_AUTO_TEST_PER_BIT_CA |
| 55 | S16 gFinalCAPerbitFirstPass[CHANNEL_NUM][RANK_MAX][CATRAINING_NUM_LP4]; |
| 56 | #endif |
| 57 | |
| 58 | #ifdef FOR_HQA_TEST_USED |
| 59 | U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX]; |
| 60 | U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10]; |
| 61 | U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; |
| 62 | U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; |
| 63 | U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX]; |
| 64 | U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX]; |
| 65 | U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX]; |
| 66 | S8 gFinalClkDuty[CHANNEL_NUM]; |
| 67 | U32 gFinalClkDutyMinMax[CHANNEL_NUM][2]; |
| 68 | S8 gFinalDQSDuty[CHANNEL_NUM][DQS_BYTE_NUMBER]; |
| 69 | U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_BYTE_NUMBER][2]; |
| 70 | #endif |
| 71 | |
| 72 | U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX]; |
| 73 | U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2]; |
| 74 | U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX]; |
| 75 | |
| 76 | #if defined(RELEASE) |
| 77 | U8 gEye_Scan_color_flag = 0; |
| 78 | U8 gCBT_EYE_Scan_flag = 0; |
| 79 | U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1; |
| 80 | U8 gRX_EYE_Scan_flag = 0; |
| 81 | U8 gRX_EYE_Scan_only_higheset_freq_flag = 1; |
| 82 | U8 gTX_EYE_Scan_flag = 1; |
| 83 | U8 gTX_EYE_Scan_only_higheset_freq_flag = 1; |
| 84 | U8 gEye_Scan_unterm_highest_flag = 0; |
| 85 | #elif (CFG_DRAM_LOG_TO_STORAGE) |
| 86 | U8 gEye_Scan_color_flag = 0; |
| 87 | U8 gCBT_EYE_Scan_flag = 0; |
| 88 | U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1; |
| 89 | U8 gRX_EYE_Scan_flag = 1; |
| 90 | U8 gRX_EYE_Scan_only_higheset_freq_flag = 1; |
| 91 | U8 gTX_EYE_Scan_flag = 1; |
| 92 | U8 gTX_EYE_Scan_only_higheset_freq_flag = 1; |
| 93 | U8 gEye_Scan_unterm_highest_flag = 0; |
| 94 | #else |
| 95 | U8 gEye_Scan_color_flag = 1; |
| 96 | U8 gCBT_EYE_Scan_flag = 0; |
| 97 | U8 gCBT_EYE_Scan_only_higheset_freq_flag = 1; |
| 98 | U8 gRX_EYE_Scan_flag = 0; |
| 99 | U8 gRX_EYE_Scan_only_higheset_freq_flag = 1; |
| 100 | U8 gTX_EYE_Scan_flag = 0; |
| 101 | U8 gTX_EYE_Scan_only_higheset_freq_flag = 1; |
| 102 | U8 gEye_Scan_unterm_highest_flag = 0; |
| 103 | #endif |
| 104 | |
| 105 | #ifdef DEVIATION |
| 106 | U8 gSetSpecificedVref_Enable[3]={0}; |
| 107 | U8 gSetSpecificedVref_Type=0; |
| 108 | U8 gSetSpecificedVref_All_ChRk[3]={0}; |
| 109 | U8 gSetSpecificedVref_Channel[3]={0}; |
| 110 | U8 gSetSpecificedVref_Rank[3]={0}; |
| 111 | S8 gSetSpecificedVref_Vref_Offset[3]={0}; |
| 112 | #endif |
| 113 | |
| 114 | #ifdef FOR_HQA_REPORT_USED |
| 115 | #if CFG_DRAM_LOG_TO_STORAGE |
| 116 | U8 gHQALog_flag = 1; |
| 117 | #else |
| 118 | U8 gHQALog_flag = 0; |
| 119 | #endif |
| 120 | U16 gHQALOG_RX_delay_cell_ps_075V = 0; |
| 121 | U8 gHQALog_SLT_BIN[DRAM_DFS_SRAM_MAX] = {0}; |
| 122 | #endif |
| 123 | |
| 124 | #if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND) |
| 125 | U32 u4DQM_MCK_RK1_backup; |
| 126 | U32 u4DQM_UI_RK1_backup; |
| 127 | U32 u4DQM_PI_RK1_backup[2]; |
| 128 | U32 u4DQ_MCK_RK1_backup; |
| 129 | U32 u4DQ_UI_RK1_backup; |
| 130 | U32 u4DQ_PI_RK1_backup[2]; |
| 131 | #endif |
| 132 | |
| 133 | #if SIMULATION_RX_DVS |
| 134 | U8 u1DVS_increase[RANK_MAX][DQS_BYTE_NUMBER]; |
| 135 | #endif |
| 136 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 137 | //static U8 gu1DieNum[RANK_MAX]; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 138 | static S32 CATrain_CmdDelay[CHANNEL_NUM][RANK_MAX]; |
| 139 | static U32 CATrain_CsDelay[CHANNEL_NUM][RANK_MAX]; |
| 140 | //static S8 iFirstCAPass[RANK_MAX][DIE_NUM_MAX][CATRAINING_NUM]; |
| 141 | //static S8 iLastCAPass[RANK_MAX][DIE_NUM_MAX][CATRAINING_NUM]; |
| 142 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 143 | static S32 wrlevel_dqs_final_delay[RANK_MAX][DQS_BYTE_NUMBER]; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 144 | //static U16 u2rx_window_sum; |
| 145 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 146 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 147 | U8 gFinalRXVrefDQForSpeedUp[CHANNEL_NUM][RANK_MAX][2][2] = {0}; |
| 148 | U32 gDramcImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX] = {{0,0,0,0},{0,0,0,0},{0,0,0,0}}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 149 | |
| 150 | S16 gu2RX_DQS_Duty_Offset[DQS_BYTE_NUMBER][2]; |
| 151 | |
| 152 | #define RX_DELAY_PRE_CAL 1 |
| 153 | #if RX_DELAY_PRE_CAL |
| 154 | S16 s2RxDelayPreCal=PASS_RANGE_NA; |
| 155 | #endif |
| 156 | |
| 157 | #if MRW_CHECK_ONLY |
| 158 | U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM]; |
| 159 | #endif |
| 160 | #if MRW_CHECK_ONLY || MRW_BACKUP |
| 161 | U8 gFSPWR_Flag[RANK_MAX]={FSP_0}; |
| 162 | #endif |
| 163 | |
| 164 | #define IN_CBT (0) |
| 165 | #define OUT_CBT (1) |
| 166 | |
| 167 | #if PRINT_CALIBRATION_SUMMARY |
| 168 | static void vSetCalibrationResult(DRAMC_CTX_T *p, U8 ucCalType, U8 ucResult) |
| 169 | { |
| 170 | U32 *Pointer_CalExecute,*Pointer_CalResult; |
| 171 | if (ucCalType == DRAM_CALIBRATION_SW_IMPEDANCE) |
| 172 | { |
| 173 | Pointer_CalExecute = &p->SWImpCalExecute; |
| 174 | Pointer_CalResult = &p->SWImpCalResult; |
| 175 | } |
| 176 | else |
| 177 | { |
| 178 | Pointer_CalExecute = &p->aru4CalExecuteFlag[p->channel][p->rank]; |
| 179 | Pointer_CalResult = &p->aru4CalResultFlag[p->channel][p->rank]; |
| 180 | } |
| 181 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 182 | if (ucResult == DRAM_FAIL) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 183 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 184 | *Pointer_CalExecute |= (1<<ucCalType); |
| 185 | *Pointer_CalResult |= (1<<ucCalType); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 186 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 187 | else if(ucResult == DRAM_OK) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 188 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 189 | *Pointer_CalExecute |= (1<<ucCalType); |
| 190 | *Pointer_CalResult &= (~(1<<ucCalType)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 191 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 192 | else if(ucResult == DRAM_FAST_K) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 193 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 194 | *Pointer_CalExecute &= (~(1<<ucCalType)); |
| 195 | *Pointer_CalResult &= (~(1<<ucCalType)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 196 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 197 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 198 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 199 | *Pointer_CalExecute &= (~(1<<ucCalType)); |
| 200 | *Pointer_CalResult |= (1<<ucCalType); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 201 | } |
| 202 | } |
| 203 | |
| 204 | #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK |
| 205 | void Fast_K_CheckResult(DRAMC_CTX_T *p, U8 ucCalType) |
| 206 | { |
| 207 | U32 CheckResult=0xFFFFFFFF; |
| 208 | U32 debug_cnt[2], u4all_result_R, u4all_result_F; |
| 209 | BOOL FastK_Check_flag=0; |
| 210 | U32 *Pointer_FastKExecute,*Pointer_FastKResult; |
| 211 | |
| 212 | Pointer_FastKExecute = &p->FastKExecuteFlag[p->channel][p->rank]; |
| 213 | Pointer_FastKResult = &p->FastKResultFlag[p->channel][p->rank]; |
| 214 | |
| 215 | if ((ucCalType==DRAM_CALIBRATION_TX_PERBIT)||(ucCalType==DRAM_CALIBRATION_DATLAT)||(ucCalType==DRAM_CALIBRATION_RX_PERBIT)) |
| 216 | { |
| 217 | DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); |
| 218 | CheckResult = DramcEngine2Run(p,TE_OP_WRITE_READ_CHECK , TEST_XTALK_PATTERN); |
| 219 | DramcEngine2End(p); |
| 220 | FastK_Check_flag=1; |
| 221 | } |
| 222 | else if (ucCalType==DRAM_CALIBRATION_RX_RDDQC) |
| 223 | { |
| 224 | DramcRxWinRDDQCInit(p); |
| 225 | CheckResult = DramcRxWinRDDQCRun(p); |
| 226 | DramcRxWinRDDQCEnd(p); |
| 227 | FastK_Check_flag=1; |
| 228 | } |
| 229 | else if (ucCalType==DRAM_CALIBRATION_GATING) |
| 230 | { |
| 231 | DramcEngine2Init(p, 0x55000000, 0xaa000000 |0x23, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT); |
| 232 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 233 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 234 | DramPhyReset(p); |
| 235 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, |
| 236 | MISC_STBCAL2_DQSG_CNT_RST); |
| 237 | mcDELAY_US(1); |
| 238 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, |
| 239 | MISC_STBCAL2_DQSG_CNT_RST); |
| 240 | |
| 241 | DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN); |
| 242 | |
| 243 | debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0)); |
| 244 | debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1)); |
| 245 | |
| 246 | //mcSHOW_DBG_MSG((" 0x%X ",u4DebugCnt)) |
| 247 | if (debug_cnt[0]==0x4646 && debug_cnt[1]==0x4646) |
| 248 | CheckResult=0; |
| 249 | |
| 250 | DramcEngine2End(p); |
| 251 | FastK_Check_flag=1; |
| 252 | } |
| 253 | |
| 254 | |
| 255 | if ((FastK_Check_flag==1)&&(CheckResult==0)) |
| 256 | { |
| 257 | //mcSHOW_DBG_MSG((" [FAST K CHECK]->PASS\n")) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 258 | *Pointer_FastKResult &= (~(1<<ucCalType)); |
| 259 | *Pointer_FastKExecute |= (1<<ucCalType);; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 260 | } |
| 261 | else if ((FastK_Check_flag==1)&&(CheckResult !=0)) |
| 262 | { |
| 263 | //mcSHOW_DBG_MSG((" [FAST K CHECK]->FAIL\n")) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 264 | *Pointer_FastKResult |= (1<<ucCalType); |
| 265 | *Pointer_FastKExecute |= (1<<ucCalType);; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 266 | } |
| 267 | } |
| 268 | #endif |
| 269 | |
| 270 | const char *szCalibStatusName[DRAM_CALIBRATION_MAX]= |
| 271 | { |
| 272 | "SW Impedance ", |
| 273 | "DUTY Scan ", |
| 274 | "ZQ Calibration ", |
| 275 | "Jitter Meter ", |
| 276 | "CBT Training ", |
| 277 | "Write leveling ", |
| 278 | "RX DQS gating ", |
| 279 | "RX IN BUFF OFFC ", |
| 280 | "RX DQ/DQS(RDDQC) ", |
| 281 | "TX DQ/DQS ", |
| 282 | "RX DATLAT ", |
| 283 | "RX DQ/DQS(Engine)", |
| 284 | "TX OE ", |
| 285 | }; |
| 286 | |
| 287 | void vPrintCalibrationResult(DRAMC_CTX_T *p) |
| 288 | { |
| 289 | U8 ucCHIdx, ucRankIdx, ucCalIdx; |
| 290 | U32 ucCalResult_All, ucCalExecute_All; |
| 291 | U8 ucCalResult, ucCalExecute; |
| 292 | U8 u1CalibrationFail; |
| 293 | |
| 294 | mcSHOW_DBG_MSG(("\n\n[Calibration Summary] Freqency %d\n", p->frequency)); |
| 295 | |
| 296 | //for(ucFreqIdx=0; ucFreqIdx<DRAM_DFS_SRAM_MAX; ucFreqIdx++) |
| 297 | { |
| 298 | //mcSHOW_DBG_MSG(("==Freqency = %d==\n", get_FreqTbl_by_SRAMIndex(p,ucFreqIdx)->frequency)); |
| 299 | for(ucCHIdx=0; ucCHIdx<p->support_channel_num; ucCHIdx++) |
| 300 | { |
| 301 | for(ucRankIdx=0; ucRankIdx<p->support_rank_num; ucRankIdx++) |
| 302 | { |
| 303 | u1CalibrationFail =0; |
| 304 | ucCalExecute_All = p->aru4CalExecuteFlag[ucCHIdx][ucRankIdx]; |
| 305 | ucCalResult_All = p->aru4CalResultFlag[ucCHIdx][ucRankIdx]; |
| 306 | mcSHOW_DBG_MSG(("CH %d, Rank %d\n", ucCHIdx, ucRankIdx)); |
| 307 | //mcSHOW_DBG_MSG(("[vPrintCalibrationResult] Channel = %d, Rank= %d, Freq.= %d, (ucCalExecute_All 0x%x, ucCalResult_All 0x%x)\n", ucCHIdx, ucRankIdx, ucFreqIdx, ucCalExecute_All, ucCalResult_All)); |
| 308 | |
| 309 | for(ucCalIdx =0; ucCalIdx<DRAM_CALIBRATION_MAX; ucCalIdx++) |
| 310 | { |
| 311 | if(ucCalIdx==0) |
| 312 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 313 | ucCalExecute = (U8)p->SWImpCalExecute; |
| 314 | ucCalResult = (U8)p->SWImpCalResult; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 315 | } |
| 316 | else |
| 317 | { |
| 318 | ucCalExecute = (U8)((ucCalExecute_All >>ucCalIdx) & 0x1); |
| 319 | ucCalResult = (U8)((ucCalResult_All >>ucCalIdx) & 0x1); |
| 320 | } |
| 321 | |
| 322 | #if PRINT_CALIBRATION_SUMMARY_DETAIL |
| 323 | mcSHOW_DBG_MSG(("%s: ", szCalibStatusName[ucCalIdx])) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 324 | if(ucCalExecute==1 && ucCalResult ==1) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 325 | { |
| 326 | u1CalibrationFail =1; |
| 327 | mcSHOW_DBG_MSG(("%s\n", "@_@FAIL@_@")) |
| 328 | #if defined(SLT) |
| 329 | mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__)); |
| 330 | while (1); |
| 331 | #endif |
| 332 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 333 | else if (ucCalExecute==1 && ucCalResult ==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 334 | { |
| 335 | mcSHOW_DBG_MSG(("%s\n", "PASS")) |
| 336 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 337 | else if (ucCalExecute==0 && ucCalResult ==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 338 | { |
| 339 | mcSHOW_DBG_MSG(("%s\n", "FAST K")) |
| 340 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 341 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 342 | { |
| 343 | mcSHOW_DBG_MSG(("%s\n", "NO K")) |
| 344 | } |
| 345 | |
| 346 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 347 | if(ucCalExecute==1 && ucCalResult ==1) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 348 | { |
| 349 | u1CalibrationFail =1; |
| 350 | mcSHOW_DBG_MSG(("%s: %s\n", szCalibStatusName[ucCalIdx],"@_@FAIL@_@")) |
| 351 | #if defined(SLT) |
| 352 | mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x00000001, line: %d\n",__LINE__)); |
| 353 | while (1); |
| 354 | #endif |
| 355 | } |
| 356 | #endif |
| 357 | } |
| 358 | |
| 359 | if(u1CalibrationFail ==0) |
| 360 | { |
| 361 | mcSHOW_DBG_MSG(("All Pass.\n")); |
| 362 | } |
| 363 | mcSHOW_DBG_MSG(("\n")); |
| 364 | } |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | } |
| 369 | #endif |
| 370 | |
| 371 | #ifdef DEVIATION |
| 372 | static void DeviationAddVrefOffset(U8 k_type, U16 *u2FinalRange, U16 *u2FinalVref, S8 Vref_Offset) |
| 373 | { |
| 374 | S16 temp_vref_value; |
| 375 | |
| 376 | if (k_type==Deviation_RX) |
| 377 | { |
| 378 | temp_vref_value = *u2FinalVref + Vref_Offset; |
| 379 | if (temp_vref_value < 0) |
| 380 | { |
| 381 | *u2FinalVref = 0; |
| 382 | } |
| 383 | else if (temp_vref_value < RX_VREF_RANGE_END) |
| 384 | { |
| 385 | *u2FinalVref = temp_vref_value; |
| 386 | } |
| 387 | else |
| 388 | { |
| 389 | *u2FinalVref = RX_VREF_RANGE_END; |
| 390 | } |
| 391 | } |
| 392 | else |
| 393 | { |
| 394 | temp_vref_value = (*u2FinalRange*30) + *u2FinalVref + Vref_Offset; |
| 395 | if (temp_vref_value < 0) |
| 396 | { |
| 397 | *u2FinalRange = 0; |
| 398 | *u2FinalVref = 0; |
| 399 | } |
| 400 | else if (temp_vref_value <=50) |
| 401 | { |
| 402 | *u2FinalRange = 0; |
| 403 | *u2FinalVref = temp_vref_value; |
| 404 | } |
| 405 | else if (temp_vref_value < 81) |
| 406 | { |
| 407 | *u2FinalRange = 1; |
| 408 | *u2FinalVref = temp_vref_value - 30; |
| 409 | } |
| 410 | else |
| 411 | { |
| 412 | *u2FinalRange = 1; |
| 413 | *u2FinalVref = 50; |
| 414 | } |
| 415 | } |
| 416 | } |
| 417 | void SetDeviationVref(DRAMC_CTX_T *p) |
| 418 | { |
| 419 | U8 u1ChannelIdx, u1RankIdx; |
| 420 | U16 deviation_Vref, deviation_Vref_Range; |
| 421 | U16 temp_Vref; |
| 422 | U8 backup_channel, backup_rank; |
| 423 | |
| 424 | backup_channel = vGetPHY2ChannelMapping(p); |
| 425 | backup_rank = u1GetRank(p); |
| 426 | |
| 427 | mcSHOW_DBG_MSG2(("[SetDeviationVref]\n")); |
| 428 | for(u1ChannelIdx=0; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++) |
| 429 | { |
| 430 | vSetPHY2ChannelMapping(p, u1ChannelIdx); |
| 431 | for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++) |
| 432 | { |
| 433 | vSetRank(p, u1RankIdx); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 434 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 435 | if (gSetSpecificedVref_Enable[Deviation_CA]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_CA] && p->rank==gSetSpecificedVref_Rank[Deviation_CA]) || gSetSpecificedVref_All_ChRk[Deviation_CA]==ENABLE)) |
| 436 | { |
| 437 | deviation_Vref = u1MR12Value[p->channel][p->rank][p->dram_fsp]& 0x3f; |
| 438 | deviation_Vref_Range = (u1MR12Value[p->channel][p->rank][p->dram_fsp]>>6)&0x1; |
| 439 | DeviationAddVrefOffset(Deviation_CA, &deviation_Vref_Range, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_CA]); |
| 440 | temp_Vref= ((deviation_Vref & 0x3f)|((deviation_Vref_Range & 0x1) <<6)); |
| 441 | DramcModeRegWriteByRank(p, p->rank, 12, temp_Vref); |
| 442 | u1MR12Value[p->channel][p->rank][p->dram_fsp]=temp_Vref; |
| 443 | mcSHOW_DBG_MSG2(("CBT Channel%d, Rank%d, u1MR12Value = 0x%x\n", p->channel, p->rank, u1MR12Value[p->channel][p->rank][p->dram_fsp])); |
| 444 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 445 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 446 | if (gSetSpecificedVref_Enable[Deviation_TX]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_TX] && p->rank==gSetSpecificedVref_Rank[Deviation_TX]) || gSetSpecificedVref_All_ChRk[Deviation_TX]==ENABLE)) |
| 447 | { |
| 448 | deviation_Vref = u1MR14Value[p->channel][p->rank][p->dram_fsp]& 0x3f; |
| 449 | deviation_Vref_Range = (u1MR14Value[p->channel][p->rank][p->dram_fsp]>>6)&0x1; |
| 450 | DeviationAddVrefOffset(Deviation_TX, &deviation_Vref_Range, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_TX]); |
| 451 | temp_Vref= ((deviation_Vref & 0x3f)|((deviation_Vref_Range & 0x1) <<6)); |
| 452 | DramcModeRegWriteByRank(p, p->rank, 14, temp_Vref); |
| 453 | u1MR14Value[p->channel][p->rank][p->dram_fsp]=temp_Vref; |
| 454 | mcSHOW_DBG_MSG2(("TX Channel%d, Rank%d, u1MR14Value = 0x%x\n", p->channel, p->rank, u1MR14Value[p->channel][p->rank][p->dram_fsp])); |
| 455 | } |
| 456 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 457 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 458 | if (gSetSpecificedVref_Enable[Deviation_RX]==ENABLE && ((p->channel==gSetSpecificedVref_Channel[Deviation_RX] && p->rank==gSetSpecificedVref_Rank[Deviation_RX]) || gSetSpecificedVref_All_ChRk[Deviation_RX]==ENABLE)) |
| 459 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 460 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 461 | deviation_Vref = gFinalRXVrefDQ[p->channel][p->rank][BYTE_0]; |
| 462 | DeviationAddVrefOffset(Deviation_RX, NULL, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_RX]); |
| 463 | gFinalRXVrefDQ[p->channel][p->rank][BYTE_0] = deviation_Vref; |
| 464 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), |
| 465 | P_Fld(deviation_Vref, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | |
| 466 | P_Fld(deviation_Vref, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0)); |
| 467 | mcSHOW_DBG_MSG2(("RX Channel%d, Rank%d, RX Vref B0 = 0x%x\n", p->channel, p->rank, gFinalRXVrefDQ[p->channel][p->rank][BYTE_0])); |
| 468 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 469 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 470 | deviation_Vref = gFinalRXVrefDQ[p->channel][p->rank][BYTE_1]; |
| 471 | DeviationAddVrefOffset(Deviation_RX, NULL, &deviation_Vref, gSetSpecificedVref_Vref_Offset[Deviation_RX]); |
| 472 | gFinalRXVrefDQ[p->channel][p->rank][BYTE_1] = deviation_Vref; |
| 473 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL), |
| 474 | P_Fld(deviation_Vref, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) | |
| 475 | P_Fld(deviation_Vref, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1)); |
| 476 | mcSHOW_DBG_MSG2(("RX Channel%d, Rank%d, RX Vref B1 = 0x%x\n", p->channel, p->rank, gFinalRXVrefDQ[p->channel][p->rank][BYTE_1])); |
| 477 | } |
| 478 | } |
| 479 | } |
| 480 | vSetRank(p, backup_rank); |
| 481 | vSetPHY2ChannelMapping(p, backup_channel); |
| 482 | } |
| 483 | #endif |
| 484 | |
| 485 | void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p) |
| 486 | { |
| 487 | U8 u1CHIdx, u1RankIdx, u1FSPIdx; |
| 488 | |
| 489 | u1MR01Value[FSP_0] = 0x26; |
| 490 | u1MR01Value[FSP_1] = 0x56; |
| 491 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 492 | u1MR03Value[FSP_0] = 0x31; |
| 493 | u1MR03Value[FSP_1] = 0x31; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 494 | #ifndef ENABLE_POST_PACKAGE_REPAIR |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 495 | u1MR03Value[FSP_0] |= 0x4; |
| 496 | u1MR03Value[FSP_1] |= 0x4; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 497 | #endif |
| 498 | #if ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 499 | u1MR03Value[FSP_1] |= 0x2; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 500 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 501 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 502 | u1MR04Value[RANK_0] = 0x3; |
| 503 | u1MR04Value[RANK_1] = 0x3; |
| 504 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 505 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 506 | u1MR21Value[FSP_0] = 0x0; |
| 507 | u1MR21Value[FSP_1] = 0x0; |
| 508 | u1MR51Value[FSP_0] = 0x0; |
| 509 | u1MR51Value[FSP_1] = 0x0; |
| 510 | |
| 511 | for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++) |
| 512 | { |
| 513 | u1MR02Value[u1FSPIdx] = 0x1a; |
| 514 | } |
| 515 | |
| 516 | for (u1CHIdx = 0; u1CHIdx < CHANNEL_NUM; u1CHIdx++) |
| 517 | for (u1RankIdx = 0; u1RankIdx < RANK_MAX; u1RankIdx++) |
| 518 | for (u1FSPIdx = 0; u1FSPIdx < p->support_fsp_num; u1FSPIdx++) |
| 519 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 520 | |
| 521 | u1MR14Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x18; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 522 | #if FSP1_CLKCA_TERM |
| 523 | u1MR12Value[u1CHIdx][u1RankIdx][u1FSPIdx] = (u1FSPIdx == FSP_0)? 0x5d: 0x1b; |
| 524 | #else |
| 525 | u1MR12Value[u1CHIdx][u1RankIdx][u1FSPIdx] = 0x5d; |
| 526 | #endif |
| 527 | #if MRW_CHECK_ONLY |
| 528 | for (u1MRIdx = 0; u1MRIdx < MR_NUM; u1MRIdx++) |
| 529 | u2MRRecord[u1CHIdx][u1RankIdx][u1FSPIdx][u1MRIdx] = 0xffff; |
| 530 | #endif |
| 531 | } |
| 532 | |
| 533 | memset(gu2RX_DQS_Duty_Offset, 0, sizeof(gu2RX_DQS_Duty_Offset)); |
| 534 | } |
| 535 | |
| 536 | const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6] = |
| 537 | { |
| 538 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 539 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 540 | { |
| 541 | 3, 1, 0, 5, 7, 4 |
| 542 | }, |
| 543 | |
| 544 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 545 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 546 | { |
| 547 | 3, 2, 4, 0, 5, 1 |
| 548 | }, |
| 549 | #endif |
| 550 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 551 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 552 | { |
| 553 | 3, 1, 0, 5, 7, 4 |
| 554 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 555 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 556 | { |
| 557 | 3, 2, 4, 0, 5, 1 |
| 558 | }, |
| 559 | #endif |
| 560 | }, |
| 561 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 562 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 563 | { |
| 564 | 5, 2, 1, 3, 4, 0 |
| 565 | }, |
| 566 | |
| 567 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 568 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 569 | { |
| 570 | 0, 2, 1, 3, 4, 5 |
| 571 | }, |
| 572 | #endif |
| 573 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 574 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 575 | { |
| 576 | 0, 1, 2, 3, 4, 5 |
| 577 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 578 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 579 | { |
| 580 | 0, 1, 2, 3, 4, 5 |
| 581 | }, |
| 582 | #endif |
| 583 | }, |
| 584 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 585 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 586 | { |
| 587 | 5, 4, 3, 2, 1, 0 |
| 588 | }, |
| 589 | |
| 590 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 591 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 592 | { |
| 593 | 4, 5, 2, 0, 3, 1 |
| 594 | }, |
| 595 | #endif |
| 596 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 597 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 598 | { |
| 599 | 5, 4, 0, 2, 1, 3 |
| 600 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 601 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 602 | { |
| 603 | 3, 5, 2, 4, 0, 1 |
| 604 | }, |
| 605 | #endif |
| 606 | }, |
| 607 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 608 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 609 | { |
| 610 | 3, 0, 2, 4, 1, 5 |
| 611 | }, |
| 612 | |
| 613 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 614 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 615 | { |
| 616 | 4, 1, 0, 2, 3, 5 |
| 617 | }, |
| 618 | #endif |
| 619 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 620 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 621 | { |
| 622 | 5, 0, 4, 3, 1, 2 |
| 623 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 624 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 625 | { |
| 626 | 2, 5, 3, 0, 4, 1 |
| 627 | }, |
| 628 | #endif |
| 629 | }, |
| 630 | }; |
| 631 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 632 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 633 | const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] = |
| 634 | { |
| 635 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 636 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 637 | { |
| 638 | 0, 1, 2, 3, 5, 7, 6, 4, |
| 639 | 9, 8, 13, 15, 10, 14, 11, 12 |
| 640 | }, |
| 641 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 642 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 643 | { |
| 644 | 0, 1, 5, 4, 3, 7, 6, 2, |
| 645 | 9, 8, 13, 14, 10, 15, 11, 12 |
| 646 | }, |
| 647 | #endif |
| 648 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 649 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 650 | { |
| 651 | 0, 1, 2, 3, 5, 7, 6, 4, |
| 652 | 9, 8, 13, 15, 10, 14, 11, 12 |
| 653 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 654 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 655 | { |
| 656 | 0, 1, 5, 4, 3, 7, 6, 2, |
| 657 | 9, 8, 13, 14, 10, 15, 11, 12 |
| 658 | }, |
| 659 | #endif |
| 660 | }, |
| 661 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 662 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 663 | { |
| 664 | 0, 1, 4, 3, 2, 5, 7, 6, |
| 665 | 9, 8, 10, 11, 14, 13, 15, 12 |
| 666 | }, |
| 667 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 668 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 669 | { |
| 670 | 0, 1, 2, 4, 5, 3, 7, 6, |
| 671 | 8, 9, 10, 11, 15, 14, 13, 12 |
| 672 | }, |
| 673 | #endif |
| 674 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 675 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 676 | { |
| 677 | 0, 1, 2, 3, 4, 5, 6, 7, |
| 678 | 8, 9, 10, 11, 12, 13, 14, 15 |
| 679 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 680 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 681 | { |
| 682 | 0, 1, 2, 3, 4, 5, 6, 7, |
| 683 | 8, 9, 10, 11, 12, 13, 14, 15 |
| 684 | }, |
| 685 | #endif |
| 686 | }, |
| 687 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 688 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 689 | { |
| 690 | 0, 1, 3, 6, 4, 7, 2, 5, |
| 691 | 8, 9, 10, 13, 11, 12, 15, 14 |
| 692 | }, |
| 693 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 694 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 695 | { |
| 696 | 0, 1, 4, 7, 3, 5, 6, 2, |
| 697 | 9, 8, 10, 12, 11, 14, 13, 15 |
| 698 | }, |
| 699 | #endif |
| 700 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 701 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 702 | { |
| 703 | 1, 0, 3, 2, 4, 7, 6, 5, |
| 704 | 8, 9, 10, 14, 11, 15, 13, 12 |
| 705 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 706 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 707 | { |
| 708 | 0, 1, 4, 7, 3, 5, 6, 2, |
| 709 | 9, 8, 10, 12, 11, 14, 13, 15 |
| 710 | }, |
| 711 | #endif |
| 712 | }, |
| 713 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 714 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 715 | { |
| 716 | 9, 8, 11, 10, 14, 15, 13, 12, |
| 717 | 0, 1, 7, 6, 4, 5, 2, 3 |
| 718 | }, |
| 719 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 720 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 721 | { |
| 722 | 8, 9, 11, 10, 12, 14, 13, 15, |
| 723 | 1, 0, 5, 6, 3, 2, 7, 4 |
| 724 | }, |
| 725 | #endif |
| 726 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 727 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 728 | { |
| 729 | 0, 1, 7, 6, 4, 5, 2, 3, |
| 730 | 9, 8, 11, 10, 14, 15, 13, 12 |
| 731 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 732 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 733 | { |
| 734 | 1, 0, 5, 6, 3, 2, 7, 4, |
| 735 | 8, 9, 11, 10, 12, 14, 13, 15 |
| 736 | }, |
| 737 | #endif |
| 738 | }, |
| 739 | }; |
| 740 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 741 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 742 | #if (CA_PER_BIT_DELAY_CELL || PINMUX_AUTO_TEST_PER_BIT_CA) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 743 | |
| 744 | U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6] = |
| 745 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 746 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 747 | { |
| 748 | 2, 1, 0, 5, 3, 4 |
| 749 | }, |
| 750 | |
| 751 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 752 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 753 | { |
| 754 | 3, 5, 1, 0, 2, 4 |
| 755 | }, |
| 756 | #endif |
| 757 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 758 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 759 | { |
| 760 | 2, 1, 0, 5, 3, 4 |
| 761 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 762 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 763 | { |
| 764 | 3, 5, 1, 0, 2, 4 |
| 765 | }, |
| 766 | #endif |
| 767 | }; |
| 768 | #endif |
| 769 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 770 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 771 | U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16] = |
| 772 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 773 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 774 | { |
| 775 | 0, 1, 2, 3, 5, 7, 6, 4, |
| 776 | 9, 8, 13, 15, 10, 14, 11, 12 |
| 777 | }, |
| 778 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 779 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 780 | { |
| 781 | 0, 1, 5, 4, 3, 7, 6, 2, |
| 782 | 9, 8, 13, 14, 10, 15, 11, 12 |
| 783 | }, |
| 784 | #endif |
| 785 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 786 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 787 | { |
| 788 | 0, 1, 2, 3, 5, 7, 6, 4, |
| 789 | 9, 8, 13, 15, 10, 14, 11, 12 |
| 790 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 791 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 792 | { |
| 793 | 0, 1, 5, 4, 3, 7, 6, 2, |
| 794 | 9, 8, 13, 14, 10, 15, 11, 12 |
| 795 | }, |
| 796 | #endif |
| 797 | }; |
| 798 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 799 | #ifdef IMPEDANCE_TRACKING_ENABLE |
| 800 | static void ImpedanceTracking_DisImpHw_Setting(DRAMC_CTX_T *p, U8 u1DisImpHw) |
| 801 | { |
| 802 | vIO32WriteFldMulti(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS) |
| 803 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS) |
| 804 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS) |
| 805 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS) |
| 806 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS) |
| 807 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS) |
| 808 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS) |
| 809 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS) |
| 810 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS) |
| 811 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS) |
| 812 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS) |
| 813 | | P_Fld(u1DisImpHw, MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS) |
| 814 | | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS) |
| 815 | | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS) |
| 816 | | P_Fld(1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS)); |
| 817 | |
| 818 | #if (fcFOR_CHIP_ID == fc8195) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 819 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 820 | if (p->DRAMPinmux == PINMUX_DSC){ |
| 821 | vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, 1, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS); |
| 822 | }else{ |
| 823 | vIO32WriteFldAlign(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1, 0, MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS); |
| 824 | } |
| 825 | #endif |
| 826 | |
| 827 | vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_IMPCAL1, (u1DisImpHw? 0x0:0x40), SHU_MISC_IMPCAL1_IMPCALCNT); |
| 828 | vIO32WriteFldMulti(DDRPHY_REG_SHU_MISC_DRVING1, P_Fld(u1DisImpHw, SHU_MISC_DRVING1_DIS_IMPCAL_HW) |
| 829 | | P_Fld(u1DisImpHw, SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK)); |
| 830 | |
| 831 | vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_DRVING2, u1DisImpHw, SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN); |
| 832 | vIO32WriteFldAlign(DDRPHY_REG_SHU_CA_CMD12, u1DisImpHw, SHU_CA_CMD12_RG_RIMP_UNTERM_EN); |
| 833 | |
| 834 | } |
| 835 | #endif |
| 836 | |
| 837 | void vBeforeCalibration(DRAMC_CTX_T *p) |
| 838 | { |
| 839 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 840 | |
| 841 | #if SIMULATION_RX_DVS || ENABLE_RX_TRACKING |
| 842 | DramcRxInputDelayTrackingInit_byFreq(p); |
| 843 | #endif |
| 844 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 845 | DramcHWGatingOnOff(p, 0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 846 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 847 | CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 848 | |
| 849 | #if ENABLE_TMRRI_NEW_MODE |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 850 | SetCKE2RankIndependent(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 851 | #endif |
| 852 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 853 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 854 | vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, 0x0, SHU_TX_SET0_DBIWR); |
| 855 | |
| 856 | #ifdef IMPEDANCE_TRACKING_ENABLE |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 857 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 858 | U8 u1DisImpHw; |
| 859 | U32 u4TermFreq, u4WbrBackup; |
| 860 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 861 | u4TermFreq = LP4_MRFSP_TERM_FREQ; |
| 862 | |
| 863 | u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1; |
| 864 | |
| 865 | u4WbrBackup = GetDramcBroadcast(); |
| 866 | DramcBroadcastOnOff(DRAMC_BROADCAST_ON); |
| 867 | ImpedanceTracking_DisImpHw_Setting(p, u1DisImpHw); |
| 868 | DramcBroadcastOnOff(u4WbrBackup); |
| 869 | |
| 870 | #endif |
| 871 | |
| 872 | vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL, P_Fld(0, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) |
| 873 | | P_Fld(0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN)); |
| 874 | |
| 875 | |
| 876 | vIO32WriteFldMulti_All(DRAMC_REG_SHU_ZQ_SET0, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 877 | P_Fld(0x1ff, SHU_ZQ_SET0_ZQCSCNT) | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 878 | P_Fld(0x1b, SHU_ZQ_SET0_TZQLAT)); |
| 879 | |
| 880 | if (p->support_channel_num == CHANNEL_SINGLE) |
| 881 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 882 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 883 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0), P_Fld(0, ZQ_SET0_ZQCSDUAL) | P_Fld(0x0, ZQ_SET0_ZQCSMASK)); |
| 884 | } |
| 885 | else if (p->support_channel_num == CHANNEL_DUAL) |
| 886 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 887 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 888 | #ifdef ZQCS_ENABLE_LP4 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 889 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 890 | |
| 891 | vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) | |
| 892 | P_Fld(0, ZQ_SET0_ZQCSMASK_OPT) | |
| 893 | P_Fld(0, ZQ_SET0_ZQMASK_CGAR) | |
| 894 | P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR)); |
| 895 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 896 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 897 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); |
| 898 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + SHIFT_TO_CHB_ADDR, 0, ZQ_SET0_ZQCSMASK); |
| 899 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 900 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 901 | vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL); |
| 902 | #endif |
| 903 | } |
| 904 | #if (CHANNEL_NUM > 2) |
| 905 | else if (p->support_channel_num == CHANNEL_FOURTH) |
| 906 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 907 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 908 | #ifdef ZQCS_ENABLE_LP4 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 909 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 910 | |
| 911 | vIO32WriteFldMulti_All(DRAMC_REG_ZQ_SET0, P_Fld(1, ZQ_SET0_ZQCSDUAL) | |
| 912 | P_Fld(0, ZQ_SET0_ZQCALL) | |
| 913 | P_Fld(0, ZQ_SET0_ZQ_SRF_OPT) | |
| 914 | P_Fld(0, ZQ_SET0_ZQCSMASK_OPT) | |
| 915 | P_Fld(0, ZQ_SET0_ZQMASK_CGAR) | |
| 916 | P_Fld(0, ZQ_SET0_ZQCS_MASK_SEL_CGAR)); |
| 917 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 918 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 919 | #if fcFOR_CHIP_ID == fcPetrus |
| 920 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); |
| 921 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_B << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); |
| 922 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_C << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); |
| 923 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_D << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); |
| 924 | #elif (fcFOR_CHIP_ID == fc8195) |
| 925 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_A << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); |
| 926 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_B << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); |
| 927 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_C << POS_BANK_NUM), 1, ZQ_SET0_ZQCSMASK); |
| 928 | vIO32WriteFldAlign(DRAMC_REG_ZQ_SET0 + (CHANNEL_D << POS_BANK_NUM), 0, ZQ_SET0_ZQCSMASK); |
| 929 | #endif |
| 930 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 931 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 932 | vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET0, 0, ZQ_SET0_ZQCS_MASK_SEL); |
| 933 | #endif |
| 934 | } |
| 935 | #endif |
| 936 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 937 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 938 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 0, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0); |
| 939 | if (!isLP4_DSC) |
| 940 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 0, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1); |
| 941 | else |
| 942 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD2, 0, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA); |
| 943 | |
| 944 | #if ENABLE_PA_IMPRO_FOR_TX_AUTOK |
| 945 | vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0x0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK); |
| 946 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 947 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 948 | #if ENABLE_PA_IMPRO_FOR_TX_TRACKING |
| 949 | vIO32WriteFldAlign_All(DRAMC_REG_DCM_SUB_CTRL, 0, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING); |
| 950 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 951 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 952 | vIO32WriteFldAlign_All(DRAMC_REG_DQSOSCR, 0x1, DQSOSCR_DQSOSCRDIS); |
| 953 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 954 | vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x1, REFCTRL0_REFDIS); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 955 | |
| 956 | vIO32WriteFldAlign_All(DRAMC_REG_SHU_MATYPE, u1MaType, SHU_MATYPE_MATYPE); |
| 957 | |
| 958 | TX_Path_Algorithm(p); |
| 959 | } |
| 960 | |
| 961 | void vAfterCalibration(DRAMC_CTX_T *p) |
| 962 | { |
| 963 | |
| 964 | #if ENABLE_READ_DBI |
| 965 | EnableDRAMModeRegReadDBIAfterCalibration(p); |
| 966 | #endif |
| 967 | |
| 968 | #if ENABLE_WRITE_DBI |
| 969 | EnableDRAMModeRegWriteDBIAfterCalibration(p); |
| 970 | #endif |
| 971 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 972 | SetMr13VrcgToNormalOperation(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 973 | |
| 974 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 975 | CKEFixOnOff(p, TO_ALL_RANK, CKE_DYNAMIC, TO_ALL_CHANNEL); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 976 | |
| 977 | vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, p->support_rank_num, DUMMY_RD_RANK_NUM); |
| 978 | |
| 979 | #if ENABLE_PER_BANK_REFRESH |
| 980 | DramcSetPerBankRefreshMode(p); |
| 981 | #endif |
| 982 | |
| 983 | #if FOR_DV_SIMULATION_USED == 1 |
| 984 | cal_sv_rand_args_t *psra = get_psra(); |
| 985 | |
| 986 | if (psra) { |
| 987 | u1MR03Value[p->dram_fsp] = psra->mr3_value; |
| 988 | } |
| 989 | #endif |
| 990 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 991 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 992 | vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL7, 0, MISC_CG_CTRL7_CK_BFE_DCM_EN); |
| 993 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 994 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 995 | vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL); |
| 996 | vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A2, 0x20, TEST2_A2_TEST2_OFF); |
| 997 | |
| 998 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 999 | vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DUTYSCAN1, 0, MISC_DUTYSCAN1_DQSERRCNT_DIS); |
| 1000 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1001 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1002 | vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL1, 0, MISC_CTRL1_R_DMSTBENCMP_RK_OPT); |
| 1003 | } |
| 1004 | |
| 1005 | static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) |
| 1006 | { |
| 1007 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1008 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1009 | const U32 u4O1RegBackupAddress[] = |
| 1010 | { |
| 1011 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), |
| 1012 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), |
| 1013 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), |
| 1014 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), |
| 1015 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)), |
| 1016 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)) |
| 1017 | }; |
| 1018 | #endif |
| 1019 | |
| 1020 | U8 u1VrefSel; |
| 1021 | |
| 1022 | if (u1OnOff == ON) |
| 1023 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1024 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1025 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF), 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0); |
| 1026 | if (!isLP4_DSC) |
Rex-BC Chen | 1259da1 | 2021-10-06 20:26:58 +0800 | [diff] [blame] | 1027 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1028 | else |
| 1029 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF), 1, SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA); |
| 1030 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1031 | u1VrefSel = 0x37; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1032 | |
| 1033 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), |
| 1034 | P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | |
| 1035 | P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0)); |
| 1036 | if (!isLP4_DSC) |
| 1037 | { |
| 1038 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL), |
| 1039 | P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) | |
| 1040 | P_Fld(u1VrefSel, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1)); |
| 1041 | } |
| 1042 | else |
| 1043 | { |
| 1044 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL), |
| 1045 | P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB) | |
| 1046 | P_Fld(u1VrefSel, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB)); |
| 1047 | } |
| 1048 | } |
| 1049 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1050 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1051 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), u1OnOff, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0); |
| 1052 | if (!isLP4_DSC) |
| 1053 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), u1OnOff, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1); |
| 1054 | else |
| 1055 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), u1OnOff, CA_CMD6_RG_RX_ARCMD_O1_SEL); |
| 1056 | |
| 1057 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1058 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1059 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), |
| 1060 | P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0) | |
| 1061 | P_Fld(u1OnOff, B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0)); |
| 1062 | if (!isLP4_DSC) |
| 1063 | { |
| 1064 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), |
| 1065 | P_Fld(u1OnOff, B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1) | |
| 1066 | P_Fld(u1OnOff, B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1)); |
| 1067 | } |
| 1068 | else |
| 1069 | { |
| 1070 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), |
| 1071 | P_Fld(u1OnOff, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN) | |
| 1072 | P_Fld(u1OnOff, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN)); |
| 1073 | } |
| 1074 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1075 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1076 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), u1OnOff, B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0); |
| 1077 | if (!isLP4_DSC) |
| 1078 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), u1OnOff, B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1); |
| 1079 | else |
| 1080 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), u1OnOff, CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA); |
| 1081 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1082 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1083 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL),(u1OnOff << 1) | u1OnOff, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); |
| 1084 | |
| 1085 | mcDELAY_US(1); |
| 1086 | } |
| 1087 | |
| 1088 | static inline u8 get_ca_pi_per_ui(DRAMC_CTX_T *p) |
| 1089 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1090 | return 32; |
| 1091 | } |
| 1092 | |
| 1093 | static int get_capi_max(DRAMC_CTX_T *p) |
| 1094 | { |
| 1095 | if (u1IsPhaseMode(p) == TRUE) |
| 1096 | { |
| 1097 | return 32; |
| 1098 | } |
| 1099 | |
| 1100 | return 64; |
| 1101 | } |
| 1102 | #if 0 |
| 1103 | static u8 get_autok_sweep_max_cnt(u8 lenpi, u8 respi) |
| 1104 | { |
| 1105 | u8 max; |
| 1106 | |
| 1107 | lenpi += 1; |
| 1108 | max = 64 / (1 << (respi & 0x3)); |
| 1109 | return lenpi > max? max: lenpi; |
| 1110 | } |
| 1111 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1112 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1113 | |
| 1114 | static int cbt_wlev_train_autok(DRAMC_CTX_T *p, ATUOK_MODE_T autok_mode, |
| 1115 | u8 initpi, u8 lenpi, u8 respi, |
| 1116 | u32 *cmp0_array, |
| 1117 | u32 *cmp1_array, |
| 1118 | u8 pin_num) |
| 1119 | { |
| 1120 | u8 sweep_max_cnt, i; |
| 1121 | u32 cnt, ready; |
| 1122 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1123 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1124 | cnt = TIME_OUT_CNT * 3; |
| 1125 | |
| 1126 | switch (autok_mode){ |
| 1127 | case AUTOK_CS: |
| 1128 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1129 | P_Fld(0, CBT_WLEV_ATK_CTRL0_ARPICS_SW)); |
| 1130 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1), |
| 1131 | P_Fld(0, CBT_WLEV_ATK_CTRL1_UICS_SW)); |
| 1132 | break; |
| 1133 | case AUTOK_CA: |
| 1134 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), |
| 1135 | P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) | |
| 1136 | P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS)); |
| 1137 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1138 | P_Fld(0, CBT_WLEV_ATK_CTRL0_ARPICA_SW)); |
| 1139 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1), |
| 1140 | P_Fld(0, CBT_WLEV_ATK_CTRL1_UICA_SW)); |
| 1141 | break; |
| 1142 | case AUTOK_DQS: |
| 1143 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1144 | P_Fld(0, CBT_WLEV_ATK_CTRL0_ARPIDQS_SW)); |
| 1145 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1), |
| 1146 | P_Fld(0, CBT_WLEV_ATK_CTRL1_UIDQS_SW)); |
| 1147 | break; |
| 1148 | } |
| 1149 | |
| 1150 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1), |
| 1151 | (get_ca_pi_per_ui(p) == 64) ? 0x1 : 0x0, CBT_WLEV_ATK_CTRL1_CBT_ATK_CA1UI64PI); |
| 1152 | |
| 1153 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1154 | 0x3, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INTV); |
| 1155 | |
| 1156 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1157 | P_Fld(lenpi, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_LENPI) | |
| 1158 | P_Fld(respi, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_RESPI) | |
| 1159 | P_Fld(initpi, CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INITPI)); |
| 1160 | |
| 1161 | switch (autok_mode){ |
| 1162 | case AUTOK_CS: |
| 1163 | if (p->new_cbt_mode) |
| 1164 | { |
| 1165 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1166 | P_Fld(1, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN)); |
| 1167 | } |
| 1168 | else |
| 1169 | { |
| 1170 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1171 | P_Fld(1, CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN)); |
| 1172 | } |
| 1173 | break; |
| 1174 | case AUTOK_CA: |
| 1175 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1176 | P_Fld(1, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN)); |
| 1177 | break; |
| 1178 | case AUTOK_DQS: |
| 1179 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1180 | P_Fld(1, CBT_WLEV_ATK_CTRL0_WLEV_ATKEN)); |
| 1181 | break; |
| 1182 | } |
| 1183 | |
| 1184 | do { |
| 1185 | ready = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_STATUS), |
| 1186 | CBT_WLEV_STATUS_CBT_WLEV_ATK_RESPONSE); |
| 1187 | cnt--; |
| 1188 | mcDELAY_US(1); |
| 1189 | } |
| 1190 | #if FOR_DV_SIMULATION_USED |
| 1191 | while (ready == 0); |
| 1192 | #else |
| 1193 | while ((ready == 0) && (cnt > 0)); |
| 1194 | #endif |
| 1195 | |
| 1196 | if (cnt == 0){ |
| 1197 | mcSHOW_ERR_MSG(("[cbt_autok] Resp fail (time out) for ")) |
| 1198 | switch (autok_mode) { |
| 1199 | case AUTOK_CS: |
| 1200 | mcSHOW_ERR_MSG(("CSTrain\n")); |
| 1201 | break; |
| 1202 | case AUTOK_CA: |
| 1203 | mcSHOW_ERR_MSG(("CATrain\n")); |
| 1204 | break; |
| 1205 | case AUTOK_DQS: |
| 1206 | mcSHOW_ERR_MSG(("DQSTrain\n")); |
| 1207 | break; |
| 1208 | } |
| 1209 | } |
| 1210 | |
| 1211 | sweep_max_cnt = get_autok_sweep_max_cnt(lenpi, respi); |
| 1212 | for (i = 0; i < pin_num; i++) { |
| 1213 | cmp0_array[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_RESULT0 + i * 8)); |
| 1214 | |
| 1215 | if (sweep_max_cnt > 32) { |
| 1216 | cmp1_array[i] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_RESULT1 + i * 8)); |
| 1217 | } else { |
| 1218 | cmp1_array[i] = 0xFFFFFFFF; |
| 1219 | } |
| 1220 | } |
| 1221 | |
| 1222 | for (i = 0; i < pin_num; i++) { |
| 1223 | mcSHOW_DBG_MSG4(("cmp0[%d]=0x%x, cmp1[%d]=0x%x\n", |
| 1224 | i, cmp0_array[i], |
| 1225 | i, cmp1_array[i])); |
| 1226 | } |
| 1227 | |
| 1228 | switch (autok_mode){ |
| 1229 | case AUTOK_CS: |
| 1230 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1231 | P_Fld(1, CBT_WLEV_ATK_CTRL0_ARPICS_SW)); |
| 1232 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1), |
| 1233 | P_Fld(0x3, CBT_WLEV_ATK_CTRL1_UICS_SW)); |
| 1234 | if (p->new_cbt_mode) |
| 1235 | { |
| 1236 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1237 | P_Fld(0, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN)); |
| 1238 | } |
| 1239 | else |
| 1240 | { |
| 1241 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1242 | P_Fld(0, CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN)); |
| 1243 | } |
| 1244 | break; |
| 1245 | case AUTOK_CA: |
| 1246 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1247 | P_Fld(1, CBT_WLEV_ATK_CTRL0_ARPICA_SW)); |
| 1248 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1), |
| 1249 | P_Fld(0x7F, CBT_WLEV_ATK_CTRL1_UICA_SW)); |
| 1250 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1251 | P_Fld(0, CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN)); |
| 1252 | break; |
| 1253 | case AUTOK_DQS: |
| 1254 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1255 | P_Fld(1, CBT_WLEV_ATK_CTRL0_ARPIDQS_SW)); |
| 1256 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL1), |
| 1257 | P_Fld(0xF, CBT_WLEV_ATK_CTRL1_UIDQS_SW)); |
| 1258 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_ATK_CTRL0), |
| 1259 | P_Fld(0, CBT_WLEV_ATK_CTRL0_WLEV_ATKEN)); |
| 1260 | break; |
| 1261 | } |
| 1262 | |
| 1263 | return 0; |
| 1264 | } |
| 1265 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1266 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1267 | |
| 1268 | struct cbt_intv { |
| 1269 | DRAM_PLL_FREQ_SEL_T freq_sel; |
| 1270 | DIV_MODE_T divmode; |
| 1271 | u8 tcmdo1lat; |
| 1272 | u8 catrain_intv; |
| 1273 | u8 new_cbt_pat_intv; |
| 1274 | u8 wlev_dqspat_lat; |
| 1275 | }; |
| 1276 | |
| 1277 | static void set_cbt_intv_rg(DRAMC_CTX_T *p, struct cbt_intv *pintv) |
| 1278 | { |
| 1279 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), |
| 1280 | P_Fld(pintv->tcmdo1lat, CBT_WLEV_CTRL1_TCMDO1LAT) | |
| 1281 | P_Fld(pintv->catrain_intv, CBT_WLEV_CTRL1_CATRAIN_INTV)); |
| 1282 | |
| 1283 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5), |
| 1284 | P_Fld(pintv->new_cbt_pat_intv, CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV)); |
| 1285 | |
| 1286 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), |
| 1287 | P_Fld(pintv->wlev_dqspat_lat, CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT)); |
| 1288 | } |
| 1289 | |
| 1290 | static struct cbt_intv *lookup_cbt_intv(struct cbt_intv *intv, int cnt, |
| 1291 | DRAM_PLL_FREQ_SEL_T fsel, DIV_MODE_T dmode) |
| 1292 | { |
| 1293 | struct cbt_intv *pintv = NULL; |
| 1294 | int i; |
| 1295 | |
| 1296 | for (i = 0; i < cnt; i++) { |
| 1297 | if (intv[i].freq_sel == fsel && intv[i].divmode == dmode) { |
| 1298 | pintv = &intv[i]; |
| 1299 | break; |
| 1300 | } |
| 1301 | } |
| 1302 | |
| 1303 | return pintv; |
| 1304 | } |
| 1305 | |
| 1306 | static void set_cbt_wlev_intv_lp4(DRAMC_CTX_T *p) |
| 1307 | { |
| 1308 | struct cbt_intv intv[] = { |
| 1309 | { |
| 1310 | LP4_DDR4266, |
| 1311 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1312 | 17, |
| 1313 | 14, |
| 1314 | 19, |
| 1315 | 19, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1316 | }, { |
| 1317 | LP4_DDR3733, |
| 1318 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1319 | 16, |
| 1320 | 13, |
| 1321 | 18, |
| 1322 | 18, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1323 | }, { |
| 1324 | LP4_DDR3200, |
| 1325 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1326 | 14, |
| 1327 | 11, |
| 1328 | 16, |
| 1329 | 16, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1330 | }, { |
| 1331 | LP4_DDR2667, |
| 1332 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1333 | 13, |
| 1334 | 10, |
| 1335 | 15, |
| 1336 | 15, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1337 | }, { |
| 1338 | LP4_DDR2400, |
| 1339 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1340 | 12, |
| 1341 | 9, |
| 1342 | 14, |
| 1343 | 14, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1344 | }, { |
| 1345 | LP4_DDR1866, |
| 1346 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1347 | 11, |
| 1348 | 9, |
| 1349 | 13, |
| 1350 | 13, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1351 | }, { |
| 1352 | LP4_DDR1600, |
| 1353 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1354 | 10, |
| 1355 | 8, |
| 1356 | 12, |
| 1357 | 12, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1358 | }, { |
| 1359 | LP4_DDR1200, |
| 1360 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1361 | 9, |
| 1362 | 8, |
| 1363 | 11, |
| 1364 | 11, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1365 | }, { |
| 1366 | LP4_DDR800, |
| 1367 | DIV8_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1368 | 8, |
| 1369 | 8, |
| 1370 | 10, |
| 1371 | 10, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1372 | }, { |
| 1373 | LP4_DDR1600, |
| 1374 | DIV4_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1375 | 16, |
| 1376 | 13, |
| 1377 | 16, |
| 1378 | 16, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1379 | }, { |
| 1380 | LP4_DDR1200, |
| 1381 | DIV4_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1382 | 14, |
| 1383 | 13, |
| 1384 | 14, |
| 1385 | 14, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1386 | }, { |
| 1387 | LP4_DDR800, |
| 1388 | DIV4_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1389 | 12, |
| 1390 | 13, |
| 1391 | 12, |
| 1392 | 12, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1393 | }, { |
| 1394 | LP4_DDR400, |
| 1395 | DIV4_MODE, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1396 | 12, |
| 1397 | 13, |
| 1398 | 12, |
| 1399 | 12, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1400 | }, |
| 1401 | }; |
| 1402 | |
| 1403 | struct cbt_intv *pintv; |
| 1404 | |
| 1405 | pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv), |
| 1406 | p->freq_sel, vGet_Div_Mode(p)); |
| 1407 | if (!pintv) { |
| 1408 | mcSHOW_ERR_MSG(("not found entry!\n")); |
| 1409 | return; |
| 1410 | } |
| 1411 | |
| 1412 | set_cbt_intv_rg(p, pintv); |
| 1413 | } |
| 1414 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1415 | static void set_cbt_wlev_intv(DRAMC_CTX_T *p) |
| 1416 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1417 | set_cbt_wlev_intv_lp4(p); |
| 1418 | } |
| 1419 | |
| 1420 | #if SIMUILATION_CBT == 1 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1421 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1422 | struct cbt_pinmux { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1423 | u8 dram_dq_b0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1424 | u8 dram_dq_b1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1425 | u8 dram_dmi_b0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1426 | u8 dram_dmi_b1; |
| 1427 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1428 | u8 dram_dq7_b0; |
| 1429 | u8 dram_dq7_b1; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1430 | }; |
| 1431 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1432 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1433 | static struct cbt_pinmux lp4_cp[CHANNEL_NUM] = { |
| 1434 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1435 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1436 | .dram_dq_b0 = 0, |
| 1437 | .dram_dq_b1 = 1, |
| 1438 | |
| 1439 | .dram_dmi_b0 = 0, |
| 1440 | .dram_dmi_b1 = 1, |
| 1441 | }, |
| 1442 | #if (CHANNEL_NUM>1) |
| 1443 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1444 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1445 | .dram_dq_b0 = 0, |
| 1446 | .dram_dq_b1 = 1, |
| 1447 | |
| 1448 | .dram_dmi_b0 = 0, |
| 1449 | .dram_dmi_b1 = 1, |
| 1450 | }, |
| 1451 | #endif |
| 1452 | #if (CHANNEL_NUM>2) |
| 1453 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1454 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1455 | .dram_dq_b0 = 0, |
| 1456 | .dram_dq_b1 = 1, |
| 1457 | |
| 1458 | .dram_dmi_b0 = 0, |
| 1459 | .dram_dmi_b1 = 1, |
| 1460 | }, |
| 1461 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1462 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1463 | .dram_dq_b0 = 0, |
| 1464 | .dram_dq_b1 = 1, |
| 1465 | |
| 1466 | .dram_dmi_b0 = 0, |
| 1467 | .dram_dmi_b1 = 1, |
| 1468 | }, |
| 1469 | #endif |
| 1470 | }; |
| 1471 | #if 0 |
| 1472 | static struct cbt_pinmux lp5_cp[CHANNEL_NUM] = { |
| 1473 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1474 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1475 | .dram_dq_b0 = 1, |
| 1476 | .dram_dq_b1 = 0, |
| 1477 | |
| 1478 | .dram_dmi_b0 = 1, |
| 1479 | .dram_dmi_b1 = 0, |
| 1480 | |
| 1481 | .dram_dq7_b0 = 13, |
| 1482 | .dram_dq7_b1 = 5, |
| 1483 | }, |
| 1484 | #if (CHANNEL_NUM > 1) |
| 1485 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1486 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1487 | .dram_dq_b0 = 1, |
| 1488 | .dram_dq_b1 = 0, |
| 1489 | |
| 1490 | .dram_dmi_b0 = 1, |
| 1491 | .dram_dmi_b1 = 0, |
| 1492 | |
| 1493 | .dram_dq7_b0 = 13, |
| 1494 | .dram_dq7_b1 = 5, |
| 1495 | }, |
| 1496 | #endif |
| 1497 | }; |
| 1498 | #endif |
| 1499 | static inline u8 is_byte_mode(DRAMC_CTX_T *p) |
| 1500 | { |
| 1501 | return p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1? 1: 0; |
| 1502 | } |
| 1503 | |
| 1504 | static void vSetDramMRCBTOnOff(DRAMC_CTX_T *p, U8 u1OnOff, U8 operating_fsp) |
| 1505 | { |
| 1506 | if (u1OnOff) |
| 1507 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1508 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1509 | if (operating_fsp) |
| 1510 | { |
| 1511 | MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) | |
| 1512 | P_Fld(1, MR13_FSP_WR) | |
| 1513 | P_Fld(1, MR13_CBT), |
| 1514 | TO_MR); |
| 1515 | } |
| 1516 | else |
| 1517 | { |
| 1518 | MRWriteFldMulti(p, 13, P_Fld(1, MR13_FSP_OP) | |
| 1519 | P_Fld(0, MR13_FSP_WR) | |
| 1520 | P_Fld(1, MR13_CBT), |
| 1521 | TO_MR); |
| 1522 | } |
| 1523 | |
| 1524 | if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) |
| 1525 | { |
| 1526 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(1, CBT_WLEV_CTRL0_BYTEMODECBTEN) | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1527 | P_Fld(1, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1528 | } |
| 1529 | } |
| 1530 | else |
| 1531 | { |
| 1532 | if (operating_fsp) |
| 1533 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1534 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1535 | MRWriteFldMulti(p, 13, P_Fld(0, MR13_FSP_OP) | |
| 1536 | P_Fld(1, MR13_FSP_WR) | |
| 1537 | P_Fld(0, MR13_CBT), |
| 1538 | TO_MR); |
| 1539 | } |
| 1540 | else |
| 1541 | { |
| 1542 | MRWriteFldMulti(p, 13, P_Fld(1, MR13_FSP_OP) | |
| 1543 | P_Fld(0, MR13_FSP_WR) | |
| 1544 | P_Fld(0, MR13_CBT), |
| 1545 | TO_MR); |
| 1546 | } |
| 1547 | } |
| 1548 | |
| 1549 | } |
| 1550 | |
| 1551 | static void CBTEntryLP4(DRAMC_CTX_T *p, U8 operating_fsp, U16 operation_frequency) |
| 1552 | { |
| 1553 | struct cbt_pinmux *cp = &lp4_cp[p->channel]; |
| 1554 | |
| 1555 | #if MR_CBT_SWITCH_FREQ |
| 1556 | if (p->dram_fsp == FSP_1) |
| 1557 | DramcModeRegInit_CATerm(p, 1); |
| 1558 | #endif |
| 1559 | |
| 1560 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), |
| 1561 | 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); |
| 1562 | |
| 1563 | CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 1564 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1565 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1566 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK); |
| 1567 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1568 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1569 | vSetDramMRCBTOnOff(p, ENABLE, operating_fsp); |
| 1570 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1571 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1572 | if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) |
| 1573 | { |
| 1574 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), |
| 1575 | 1, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); |
| 1576 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1577 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1578 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), |
| 1579 | 0x1, CBT_WLEV_CTRL0_DQSOEAOEN); |
| 1580 | |
| 1581 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), |
| 1582 | (1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN); |
| 1583 | } |
| 1584 | |
| 1585 | mcDELAY_US(1); |
| 1586 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1587 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1588 | CKEFixOnOff(p, p->rank, CKE_FIXOFF, TO_ONE_CHANNEL); |
| 1589 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1590 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1591 | (operating_fsp == FSP_1)? |
| 1592 | DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE): |
| 1593 | DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, JUST_TO_GLOBAL_VALUE); |
| 1594 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1595 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1596 | if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) |
| 1597 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1598 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1599 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0x3, PADCTRL_FIXDQIEN); |
| 1600 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1601 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1602 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); |
| 1603 | O1PathOnOff(p, ON); |
| 1604 | } |
| 1605 | |
| 1606 | if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) |
| 1607 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1608 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1609 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); |
| 1610 | O1PathOnOff(p, ON); |
| 1611 | } |
| 1612 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1613 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1614 | mcDELAY_US(1); |
| 1615 | } |
| 1616 | |
| 1617 | static void CBTExitLP4(DRAMC_CTX_T *p, U8 operating_fsp, U8 operation_frequency) |
| 1618 | { |
| 1619 | //U8 u1MROP; |
| 1620 | |
| 1621 | if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) |
| 1622 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1623 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1624 | CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 1625 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1626 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1627 | mcDELAY_US(1); |
| 1628 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1629 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1630 | vSetDramMRCBTOnOff(p, DISABLE, operating_fsp); |
| 1631 | |
| 1632 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), |
| 1633 | 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); |
| 1634 | } |
| 1635 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1636 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1637 | if (p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) |
| 1638 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1639 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1640 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B1_DQ3), 0, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); |
| 1641 | O1PathOnOff(p, OFF); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1642 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1643 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_PADCTRL), 0, PADCTRL_FIXDQIEN); |
| 1644 | } |
| 1645 | |
| 1646 | if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) |
| 1647 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1648 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1649 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_B0_DQ3), 0, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); |
| 1650 | O1PathOnOff(p, OFF); |
| 1651 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1652 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1653 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), P_Fld(0, CBT_WLEV_CTRL0_BYTEMODECBTEN) | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1654 | P_Fld(0, CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1655 | } |
| 1656 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1657 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1658 | mcDELAY_US(1); |
| 1659 | } |
| 1660 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1661 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1662 | static u8 get_mck_ck_ratio(DRAMC_CTX_T *p) |
| 1663 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1664 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1665 | u32 ratio; |
| 1666 | //u32 ui_max; |
| 1667 | |
| 1668 | ratio = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD), |
| 1669 | SHU_LP5_CMD_LP5_CMD1TO2EN); |
| 1670 | |
| 1671 | mcSHOW_DBG_MSG5(("LP5 MCK:CK=%s\n", ratio == 1 ? "1:1" : "1:2")); |
| 1672 | |
| 1673 | return ratio; |
| 1674 | } |
| 1675 | |
| 1676 | static u8 get_cbtui_adjustable_maxvalue(DRAMC_CTX_T *p) |
| 1677 | { |
| 1678 | u8 ratio; |
| 1679 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1680 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1681 | ratio = (vGet_Div_Mode(p) == DIV4_MODE) ? 3 : 7; |
| 1682 | |
| 1683 | return ratio; |
| 1684 | } |
| 1685 | |
| 1686 | static inline u32 get_ca_mck(DRAMC_CTX_T *p) |
| 1687 | { |
| 1688 | u32 dly; |
| 1689 | |
| 1690 | dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3)); |
| 1691 | return dly & 0x0FFFFFFFU; |
| 1692 | } |
| 1693 | |
| 1694 | static inline void put_ca_mck(DRAMC_CTX_T *p, u32 ca_mck) |
| 1695 | { |
| 1696 | u32 dly; |
| 1697 | |
| 1698 | dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3)); |
| 1699 | dly &= 0xF0000000U; |
| 1700 | ca_mck &= 0x0FFFFFFFU; |
| 1701 | dly |= ca_mck; |
| 1702 | |
| 1703 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), dly); |
| 1704 | } |
| 1705 | |
| 1706 | static inline u32 get_ca_ui(DRAMC_CTX_T *p) |
| 1707 | { |
| 1708 | u32 dly; |
| 1709 | |
| 1710 | dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7)); |
| 1711 | return dly & 0x0FFFFFFFU; |
| 1712 | } |
| 1713 | |
| 1714 | static inline void put_ca_ui(DRAMC_CTX_T *p, u32 ca_ui) |
| 1715 | { |
| 1716 | u32 dly; |
| 1717 | |
| 1718 | dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7)); |
| 1719 | dly &= 0xF0000000U; |
| 1720 | ca_ui &= 0x0FFFFFFFU; |
| 1721 | dly |= ca_ui; |
| 1722 | |
| 1723 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), dly); |
| 1724 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1725 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1726 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), ca_ui & 0xF, SHU_SELPH_CA5_DLY_CKE); |
| 1727 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), ca_ui & 0xF, SHU_SELPH_CA6_DLY_CKE1); |
| 1728 | } |
| 1729 | |
| 1730 | static void xlate_ca_mck_ui(DRAMC_CTX_T *p, u32 ui_delta, |
| 1731 | u32 mck_old, u32 ui_old, u32 *mck_new, u32 *ui_new) |
| 1732 | { |
| 1733 | u8 i; |
| 1734 | u32 mask, max; |
| 1735 | u32 bit_ui, bit_mck; |
| 1736 | u32 ui_tmp = 0, mck_tmp = 0; |
| 1737 | |
| 1738 | max = get_cbtui_adjustable_maxvalue(p); |
| 1739 | mask = max; |
| 1740 | |
| 1741 | for (i = 0; i < CATRAINING_NUM_LP5; i++) { |
| 1742 | bit_mck = 0; |
| 1743 | bit_ui = ((ui_old >> (i * 4)) & mask) + ui_delta; |
| 1744 | if (bit_ui > max) { |
| 1745 | bit_mck = bit_ui / (max + 1); |
| 1746 | bit_ui = bit_ui % (max + 1); |
| 1747 | } |
| 1748 | |
| 1749 | mck_tmp += (bit_mck << (i * 4)); |
| 1750 | ui_tmp += (bit_ui << (i * 4)); |
| 1751 | } |
| 1752 | |
| 1753 | if (ui_new) |
| 1754 | *ui_new = ui_tmp; |
| 1755 | |
| 1756 | if (mck_new) |
| 1757 | *mck_new = mck_old + mck_tmp; |
| 1758 | } |
| 1759 | |
| 1760 | static S16 adjust_ca_ui(DRAMC_CTX_T *p, U32 ca_mck, |
| 1761 | U32 ca_ui, S16 pi_dly) |
| 1762 | { |
| 1763 | S16 p2u; |
| 1764 | S16 ui, pi; |
| 1765 | U32 ui_new = 0, mck_new = 0; |
| 1766 | |
| 1767 | if (pi_dly < get_capi_max(p)) |
| 1768 | { |
| 1769 | return pi_dly; |
| 1770 | } |
| 1771 | |
| 1772 | p2u = get_ca_pi_per_ui(p); |
| 1773 | |
| 1774 | ui = pi_dly / p2u; |
| 1775 | pi = pi_dly % p2u; |
| 1776 | |
| 1777 | xlate_ca_mck_ui(p, ui, ca_mck, ca_ui, &mck_new, &ui_new); |
| 1778 | |
| 1779 | put_ca_ui(p, ui_new); |
| 1780 | put_ca_mck(p, mck_new); |
| 1781 | mcSHOW_DBG_MSG5(("mck_new: 0x%x, ui_new: 0x%x, pi:%d\n", |
| 1782 | mck_new, ui_new, pi)); |
| 1783 | |
| 1784 | return pi; |
| 1785 | } |
| 1786 | |
| 1787 | static inline u32 get_cs_mck(DRAMC_CTX_T *p) |
| 1788 | { |
| 1789 | if (p->rank == RANK_1) |
| 1790 | return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), |
| 1791 | SHU_SELPH_CA1_TXDLY_CS1); |
| 1792 | else |
| 1793 | return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), |
| 1794 | SHU_SELPH_CA1_TXDLY_CS); |
| 1795 | } |
| 1796 | |
| 1797 | static inline void put_cs_mck(DRAMC_CTX_T *p, u32 cs_ui) |
| 1798 | { |
| 1799 | if (p->rank == RANK_1) |
| 1800 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), |
| 1801 | cs_ui, SHU_SELPH_CA1_TXDLY_CS1); |
| 1802 | else |
| 1803 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), |
| 1804 | cs_ui, SHU_SELPH_CA1_TXDLY_CS); |
| 1805 | } |
| 1806 | |
| 1807 | static inline u32 get_cs_ui(DRAMC_CTX_T *p) |
| 1808 | { |
| 1809 | if (p->rank == RANK_1) |
| 1810 | return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), |
| 1811 | SHU_SELPH_CA5_DLY_CS1); |
| 1812 | else |
| 1813 | return u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), |
| 1814 | SHU_SELPH_CA5_DLY_CS); |
| 1815 | } |
| 1816 | |
| 1817 | static inline void put_cs_ui(DRAMC_CTX_T *p, u32 cs_ui) |
| 1818 | { |
| 1819 | if (p->rank == RANK_1) |
| 1820 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), |
| 1821 | cs_ui, SHU_SELPH_CA5_DLY_CS1); |
| 1822 | else |
| 1823 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), |
| 1824 | cs_ui, SHU_SELPH_CA5_DLY_CS); |
| 1825 | } |
| 1826 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1827 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1828 | |
| 1829 | static S16 adjust_cs_ui(DRAMC_CTX_T *p, u32 cs_mck, u32 cs_ui, S16 pi_dly) |
| 1830 | { |
| 1831 | S16 p2u; |
| 1832 | S16 ui = 0, pi = 0; |
| 1833 | u8 ratio; |
| 1834 | u32 ui_max; |
| 1835 | u32 cs_bit_mask, cs_ui_tmp, cs_mck_tmp; |
| 1836 | |
| 1837 | if (pi_dly < get_capi_max(p)) |
| 1838 | { |
| 1839 | return pi_dly; |
| 1840 | } |
| 1841 | |
| 1842 | p2u = get_ca_pi_per_ui(p); |
| 1843 | |
| 1844 | ui = pi_dly / p2u; |
| 1845 | pi = pi_dly % p2u; |
| 1846 | |
| 1847 | ratio = get_mck_ck_ratio(p); |
| 1848 | if (ratio) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1849 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1850 | cs_bit_mask = 1; |
| 1851 | } else { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1852 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1853 | cs_bit_mask = 3; |
| 1854 | } |
| 1855 | |
| 1856 | ui_max = get_cbtui_adjustable_maxvalue(p); |
| 1857 | cs_ui_tmp = (cs_ui & cs_bit_mask) + ui; |
| 1858 | cs_mck_tmp = 0; |
| 1859 | if (cs_ui_tmp > ui_max) { |
| 1860 | cs_mck_tmp = cs_ui_tmp / (ui_max + 1); |
| 1861 | cs_ui_tmp = cs_ui_tmp % (ui_max + 1); |
| 1862 | } |
| 1863 | |
| 1864 | cs_mck_tmp += cs_mck; |
| 1865 | put_cs_ui(p, cs_ui_tmp); |
| 1866 | put_cs_mck(p, cs_mck_tmp); |
| 1867 | |
| 1868 | mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d before\n", |
| 1869 | cs_mck, cs_ui, 0)); |
| 1870 | mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d after\n", |
| 1871 | cs_mck_tmp, cs_ui_tmp, pi)); |
| 1872 | |
| 1873 | return pi; |
| 1874 | } |
| 1875 | |
| 1876 | static u32 get_capi_step(DRAMC_CTX_T *p, int autok) |
| 1877 | { |
| 1878 | u32 step; |
| 1879 | |
| 1880 | #if FOR_DV_SIMULATION_USED |
| 1881 | step = 8; |
| 1882 | #else |
| 1883 | switch (p->freq_sel) { |
| 1884 | case LP5_DDR800: |
| 1885 | case LP5_DDR1200: |
| 1886 | case LP5_DDR1600: |
| 1887 | case LP5_DDR3733: |
| 1888 | step = 8; |
| 1889 | break; |
| 1890 | default: |
| 1891 | if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) |
| 1892 | step = 8; |
| 1893 | else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) |
| 1894 | step = 16; |
| 1895 | else |
| 1896 | step = 1; |
| 1897 | |
| 1898 | break; |
| 1899 | } |
| 1900 | #endif |
| 1901 | |
| 1902 | if (step > 8 && autok) |
| 1903 | step = 8; |
| 1904 | |
| 1905 | return step; |
| 1906 | } |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1907 | |
| 1908 | void CmdOEOnOff(DRAMC_CTX_T *p, U8 u1OnOff, CMDOE_DIS_CHANNEL CmdOeDisChannelNUM) |
| 1909 | { |
| 1910 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
| 1911 | |
| 1912 | if (CmdOeDisChannelNUM ==CMDOE_DIS_TO_ALL_CHANNEL) |
| 1913 | { |
| 1914 | if (!isLP4_DSC) |
| 1915 | { |
| 1916 | vIO32WriteFldMulti_All(DDRPHY_REG_CA_CMD2, P_Fld(!u1OnOff, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) |
| 1917 | | P_Fld(u1OnOff, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) |
| 1918 | | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); |
| 1919 | } |
| 1920 | else |
| 1921 | { |
| 1922 | vIO32WriteFldMulti_All(DDRPHY_REG_B1_DQ2, P_Fld(!u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1) |
| 1923 | | P_Fld(u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) |
| 1924 | | P_Fld(0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1)); |
| 1925 | } |
| 1926 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1927 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1928 | { |
| 1929 | if (!isLP4_DSC) |
| 1930 | { |
| 1931 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(!u1OnOff, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA) |
| 1932 | | P_Fld(u1OnOff, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) |
| 1933 | | P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); |
| 1934 | } |
| 1935 | else |
| 1936 | { |
| 1937 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld(!u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_DIS_B1) |
| 1938 | | P_Fld(u1OnOff, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) |
| 1939 | | P_Fld(0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1)); |
| 1940 | } |
| 1941 | } |
| 1942 | |
| 1943 | |
| 1944 | } |
| 1945 | |
| 1946 | void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay) |
| 1947 | { |
| 1948 | if (iDelay < 0) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1949 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1950 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), |
| 1951 | P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CMD) | |
| 1952 | P_Fld(-iDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) | |
| 1953 | P_Fld(-iDelay, SHU_R0_CA_CMD0_RG_ARPI_CS)); |
| 1954 | } |
| 1955 | /* |
| 1956 | else if (iDelay >= 64) |
| 1957 | { |
| 1958 | DramcCmdUIDelaySetting(p, 2); |
| 1959 | |
| 1960 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), |
| 1961 | P_Fld(iDelay - 64, SHU_R0_CA_CMD0_RG_ARPI_CMD) | |
| 1962 | P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) | |
| 1963 | P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS)); |
| 1964 | } |
| 1965 | */ |
| 1966 | else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1967 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1968 | // DramcCmdUIDelaySetting(p, 0); |
| 1969 | |
| 1970 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), |
| 1971 | P_Fld(iDelay, SHU_R0_CA_CMD0_RG_ARPI_CMD) | |
| 1972 | P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CLK) | |
| 1973 | P_Fld(0, SHU_R0_CA_CMD0_RG_ARPI_CS)); |
| 1974 | } |
| 1975 | } |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1976 | |
| 1977 | #if CBT_AUTO_K_SUPPORT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 1978 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 1979 | #if 0 |
| 1980 | static int cbt_catrain_autok(DRAMC_CTX_T *p, |
| 1981 | u8 initpi, u8 steps, u8 respi, |
| 1982 | u32 *cmp0_array, u32 *cmp1_array, |
| 1983 | u8 n) |
| 1984 | { |
| 1985 | u8 lenpi; |
| 1986 | int res; |
| 1987 | |
| 1988 | if (steps == 0) |
| 1989 | steps = 1; |
| 1990 | |
| 1991 | lenpi = steps - 1; |
| 1992 | |
| 1993 | return cbt_wlev_train_autok(p, AUTOK_CA, initpi, lenpi, respi, |
| 1994 | cmp0_array, cmp1_array, n); |
| 1995 | } |
| 1996 | |
| 1997 | static int cbt_cstrain_autok(DRAMC_CTX_T *p, |
| 1998 | u8 initpi, u8 steps, u8 respi, |
| 1999 | u32 *cmp0, u32 *cmp1) |
| 2000 | { |
| 2001 | u8 lenpi; |
| 2002 | |
| 2003 | if (steps == 0) |
| 2004 | steps = 1; |
| 2005 | |
| 2006 | lenpi = steps - 1; |
| 2007 | |
| 2008 | return cbt_wlev_train_autok(p, AUTOK_CS, |
| 2009 | initpi, lenpi, respi, cmp0, cmp1, 1); |
| 2010 | } |
| 2011 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2012 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2013 | static int cbt_catrain_autok_next_window(DRAMC_CTX_T *p, |
| 2014 | u32 *bitmap, u8 start_pos, |
| 2015 | u8 initpi, u8 steps, u8 respi, |
| 2016 | PASS_WIN_DATA_T *pwin) |
| 2017 | { |
| 2018 | u8 lenpi; |
| 2019 | u8 sweep_max_cnt, win_left, win_right; |
| 2020 | int res; |
| 2021 | |
| 2022 | if (steps == 0) |
| 2023 | steps = 1; |
| 2024 | |
| 2025 | lenpi = steps - 1; |
| 2026 | |
| 2027 | sweep_max_cnt = get_autok_sweep_max_cnt(lenpi, respi); |
| 2028 | res = find_zero_window(bitmap, start_pos, sweep_max_cnt - 1, |
| 2029 | &win_left, &win_right); |
| 2030 | |
| 2031 | if (!res) { |
| 2032 | mcSHOW_DBG_MSG4(("can't find zero window.\n")); |
| 2033 | return 0; |
| 2034 | } else { |
| 2035 | mcSHOW_DBG_MSG4(("find max zero window [%d, %d]\n", |
| 2036 | win_left, win_right)); |
| 2037 | pwin->first_pass = initpi + win_left * (1 << respi); |
| 2038 | pwin->last_pass = initpi + win_right * (1 << respi); |
| 2039 | return 1; |
| 2040 | } |
| 2041 | } |
| 2042 | static void cbt_autok_maxwindow(DRAMC_CTX_T *p, |
| 2043 | u32 *bitmap, u8 uiDelay, u8 pi_step, u8 steps, u8 respi, |
| 2044 | S32 *iFirstPass, S32 *iLastPass) |
| 2045 | { |
| 2046 | int res; |
| 2047 | u8 start_pos; |
| 2048 | PASS_WIN_DATA_T win; |
| 2049 | |
| 2050 | start_pos = 0; |
| 2051 | |
| 2052 | while (1) |
| 2053 | { |
| 2054 | res = cbt_catrain_autok_next_window(p, |
| 2055 | bitmap, start_pos, |
| 2056 | uiDelay, steps, respi, &win); |
| 2057 | |
| 2058 | if (!res) |
| 2059 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2060 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2061 | mcSHOW_DBG_MSG2(("no window @pi [%d, %d]\n", |
| 2062 | uiDelay + start_pos, |
| 2063 | uiDelay + pi_step - 1)); |
| 2064 | |
| 2065 | if ((*iFirstPass != PASS_RANGE_NA) && |
| 2066 | (*iLastPass == PASS_RANGE_NA)) |
| 2067 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2068 | |
| 2069 | if ((uiDelay - *iFirstPass) < 5) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2070 | { |
| 2071 | *iFirstPass = PASS_RANGE_NA; |
| 2072 | } |
| 2073 | else |
| 2074 | { |
| 2075 | *iLastPass = uiDelay - pi_step; |
| 2076 | } |
| 2077 | } |
| 2078 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2079 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2080 | break; |
| 2081 | } |
| 2082 | else |
| 2083 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2084 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2085 | mcSHOW_DBG_MSG2(("find pi pass window [%d, %d] in [%d, %d]\n", |
| 2086 | win.first_pass, win.last_pass, |
| 2087 | uiDelay, uiDelay + pi_step - 1)); |
| 2088 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2089 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2090 | start_pos = win.last_pass - uiDelay + 1; |
| 2091 | |
| 2092 | if (*iFirstPass == PASS_RANGE_NA) |
| 2093 | { |
| 2094 | *iFirstPass = win.first_pass; |
| 2095 | } |
| 2096 | else if (*iLastPass != PASS_RANGE_NA) |
| 2097 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2098 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2099 | if (*iLastPass + (1 << respi) >= win.first_pass) |
| 2100 | { |
| 2101 | *iLastPass = win.last_pass; |
| 2102 | } |
| 2103 | else |
| 2104 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2105 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2106 | if (win.last_pass - win.first_pass >= *iLastPass - *iFirstPass) |
| 2107 | { |
| 2108 | *iFirstPass = win.first_pass; |
| 2109 | *iLastPass = win.last_pass; |
| 2110 | } |
| 2111 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2112 | continue; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2113 | } |
| 2114 | |
| 2115 | if (*iLastPass == PASS_RANGE_NA) |
| 2116 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2117 | if ((win.last_pass - *iFirstPass) < 5) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2118 | { |
| 2119 | *iFirstPass = PASS_RANGE_NA; |
| 2120 | continue; |
| 2121 | } |
| 2122 | |
| 2123 | *iLastPass = win.last_pass; |
| 2124 | } |
| 2125 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2126 | } |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2127 | } |
| 2128 | #endif |
| 2129 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2130 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2131 | static void CBTAdjustCS(DRAMC_CTX_T *p, int autok) |
| 2132 | { |
| 2133 | S32 iCSFinalDelay = 0;//iFirstCSPass = 0, iLastCSPass = 0, iCSCenter |
| 2134 | //U32 uiDelay, u4ValueReadBack, u4CSWinSize; |
| 2135 | U8 backup_rank, ii; |
| 2136 | //u32 pi_start, pi_end, pi_step; |
| 2137 | u32 pi_dly; |
| 2138 | u32 cs_ui, cs_mck; |
| 2139 | //u16 u2HalfCSWin; |
| 2140 | //u8 idx = 0; |
| 2141 | //u8 step_respi = AUTOK_RESPI_1; |
| 2142 | //u32 capi_max; |
| 2143 | |
| 2144 | backup_rank = u1GetRank(p); |
| 2145 | |
| 2146 | cs_ui = get_cs_ui(p); |
| 2147 | cs_mck = get_cs_mck(p); |
| 2148 | |
| 2149 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) |
| 2150 | if (p->femmc_Ready == 1) |
| 2151 | { |
| 2152 | CATrain_CsDelay[p->channel][p->rank] = p->pSavetimeData->u1CBTCsDelay_Save[p->channel][p->rank]; |
| 2153 | } |
| 2154 | #endif |
| 2155 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2156 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2157 | if(backup_rank == RANK_1) |
| 2158 | { |
| 2159 | iCSFinalDelay = (CATrain_CsDelay[p->channel][RANK_0] + CATrain_CsDelay[p->channel][RANK_1]) >> 1; |
| 2160 | } |
| 2161 | else |
| 2162 | { |
| 2163 | iCSFinalDelay = CATrain_CsDelay[p->channel][p->rank]; |
| 2164 | } |
| 2165 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2166 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2167 | for (ii = RANK_0; ii <= backup_rank; ii++) |
| 2168 | { |
| 2169 | vSetRank(p, ii); |
| 2170 | |
| 2171 | pi_dly = adjust_cs_ui(p, cs_mck, cs_ui, iCSFinalDelay); |
| 2172 | |
| 2173 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), pi_dly, SHU_R0_CA_CMD0_RG_ARPI_CS); |
| 2174 | |
| 2175 | #ifdef FOR_HQA_REPORT_USED |
| 2176 | if (gHQALog_flag == 1) |
| 2177 | { |
| 2178 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, "CS_Center", " ", 0, pi_dly, NULL); |
| 2179 | } |
| 2180 | #endif |
| 2181 | } |
| 2182 | |
| 2183 | vSetRank(p, backup_rank); |
| 2184 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2185 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2186 | //mcSHOW_DBG_MSG(("CS delay=%d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass)); |
| 2187 | //mcDUMP_REG_MSG(("CS delay=%d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass)); |
| 2188 | } |
| 2189 | |
| 2190 | #if CA_PER_BIT_DELAY_CELL |
| 2191 | static void CATrainingSetPerBitDelayCell(DRAMC_CTX_T *p, S16 *iCAFinalCenter, U8 ca_pin_num) |
| 2192 | { |
| 2193 | U8 *uiLPDDR_CA_Mapping = NULL; |
| 2194 | U8 u1CA; |
| 2195 | S8 iCA_PerBit_DelayLine[8] = {0}; |
| 2196 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2197 | { |
| 2198 | uiLPDDR_CA_Mapping = (U8 *)uiLPDDR4_CA_Mapping_POP[p->channel]; |
| 2199 | } |
| 2200 | |
| 2201 | for (u1CA = 0;u1CA < ca_pin_num;u1CA++) |
| 2202 | { |
| 2203 | iCA_PerBit_DelayLine[uiLPDDR_CA_Mapping[u1CA]] = iCAFinalCenter[u1CA]; |
| 2204 | } |
| 2205 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2206 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2207 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_TXDLY0), |
| 2208 | P_Fld(iCA_PerBit_DelayLine[0], SHU_R0_CA_TXDLY0_TX_ARCA0_DLY) | |
| 2209 | P_Fld(iCA_PerBit_DelayLine[1], SHU_R0_CA_TXDLY0_TX_ARCA1_DLY) | |
| 2210 | P_Fld(iCA_PerBit_DelayLine[2], SHU_R0_CA_TXDLY0_TX_ARCA2_DLY) | |
| 2211 | P_Fld(iCA_PerBit_DelayLine[3], SHU_R0_CA_TXDLY0_TX_ARCA3_DLY)); |
| 2212 | |
| 2213 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_TXDLY1), |
| 2214 | P_Fld(iCA_PerBit_DelayLine[4], SHU_R0_CA_TXDLY1_TX_ARCA4_DLY) | |
| 2215 | P_Fld(iCA_PerBit_DelayLine[5], SHU_R0_CA_TXDLY1_TX_ARCA5_DLY) | |
| 2216 | P_Fld(iCA_PerBit_DelayLine[6], SHU_R0_CA_TXDLY1_TX_ARCA6_DLY) | |
| 2217 | P_Fld(iCA_PerBit_DelayLine[7], SHU_R0_CA_TXDLY1_TX_ARCA7_DLY)); |
| 2218 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2219 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2220 | |
| 2221 | static void CBTSetCACLKResult(DRAMC_CTX_T *p, U32 u4MCK, U32 u4UI, U8 ca_pin_num) |
| 2222 | { |
| 2223 | S8 iFinalCACLK; |
| 2224 | U8 backup_rank, rank_i, uiCA; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2225 | S16 iCAFinalCenter[CATRAINING_NUM]={0}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2226 | |
| 2227 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) |
| 2228 | if (p->femmc_Ready == 1) |
| 2229 | { |
| 2230 | CATrain_CmdDelay[p->channel][p->rank] = p->pSavetimeData->s1CBTCmdDelay_Save[p->channel][p->rank]; |
| 2231 | vSetCalibrationResult(p, DRAM_CALIBRATION_CA_TRAIN, DRAM_FAST_K); |
| 2232 | #if CA_PER_BIT_DELAY_CELL |
| 2233 | for (uiCA = 0; uiCA < ca_pin_num; uiCA++) |
| 2234 | iCAFinalCenter[uiCA] = p->pSavetimeData->u1CBTCA_PerBit_DelayLine_Save[p->channel][p->rank][uiCA]; |
| 2235 | #endif |
| 2236 | } |
| 2237 | #endif |
| 2238 | |
| 2239 | iFinalCACLK = CATrain_CmdDelay[p->channel][p->rank]; |
| 2240 | |
| 2241 | mcSHOW_DBG_MSG(("\n[CBTSetCACLKResult] CA Dly = %d\n", iFinalCACLK)); |
| 2242 | |
| 2243 | iFinalCACLK = adjust_ca_ui(p, u4MCK, u4UI, iFinalCACLK); |
| 2244 | |
| 2245 | backup_rank = u1GetRank(p); |
| 2246 | |
| 2247 | for (rank_i = RANK_0; rank_i <= p->support_rank_num;rank_i++) |
| 2248 | { |
| 2249 | vSetRank(p, rank_i); |
| 2250 | |
| 2251 | CBTDelayCACLK(p, iFinalCACLK); |
| 2252 | |
| 2253 | #if CA_PER_BIT_DELAY_CELL |
| 2254 | CATrainingSetPerBitDelayCell(p, iCAFinalCenter, ca_pin_num); |
| 2255 | #endif |
| 2256 | } |
| 2257 | |
| 2258 | vSetRank(p, backup_rank); |
| 2259 | } |
| 2260 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2261 | static U8 GetCBTVrefPinMuxValue(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel) |
| 2262 | { |
| 2263 | U8 u2VrefBit, u2Vref_org; |
| 2264 | U16 u2Vref_new; |
| 2265 | |
| 2266 | if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) |
| 2267 | return ((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f); |
| 2268 | |
| 2269 | u2Vref_org = ((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f); |
| 2270 | |
| 2271 | u2Vref_new = 0; |
| 2272 | for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++) |
| 2273 | { |
| 2274 | //mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit])); |
| 2275 | if (u2Vref_org & (1 << u2VrefBit)) |
| 2276 | { |
| 2277 | u2Vref_new |= (1 << uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]); |
| 2278 | } |
| 2279 | } |
| 2280 | |
| 2281 | mcSHOW_DBG_MSG4(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new)); |
| 2282 | |
| 2283 | if (lp4_cp[p->channel].dram_dq_b0) |
| 2284 | u2Vref_new >>= 8; |
| 2285 | |
| 2286 | return u2Vref_new; |
| 2287 | } |
| 2288 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2289 | static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 operating_fsp, U8 stateFlag) |
| 2290 | { |
| 2291 | U32 fld; |
| 2292 | U8 u4DbgValue; |
| 2293 | U8 u1VrefValue_pinmux; |
| 2294 | struct cbt_pinmux *cp = &lp4_cp[p->channel]; |
| 2295 | |
| 2296 | if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && |
| 2297 | (stateFlag == IN_CBT)) |
| 2298 | { |
| 2299 | u1VrefValue_pinmux = GetCBTVrefPinMuxValue(p, u1VrefRange, u1VrefLevel); |
| 2300 | |
| 2301 | #if !REDUCE_LOG_FOR_PRELOADER |
| 2302 | mcSHOW_DBG_MSG(("\nCH_%d, RK_%d, Range=%d, VrefValue_pinmux = 0x%x\n", p->channel, p->rank, u1VrefRange, u1VrefValue_pinmux)); |
| 2303 | #endif |
| 2304 | u1MR12Value[p->channel][p->rank][operating_fsp] = ((u1VrefRange & 0x1) << 6) | u1VrefLevel; |
| 2305 | |
| 2306 | fld = (cp->dram_dq_b0) ? CBT_WLEV_CTRL4_CBT_TXDQ_B1 : CBT_WLEV_CTRL4_CBT_TXDQ_B0; |
| 2307 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2308 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_WRITE_LEV), ((u1VrefRange&0x1) <<6) | (u1VrefLevel & 0x3f), WRITE_LEV_DMVREFCA); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2309 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2310 | u1VrefValue_pinmux, fld); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2311 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2312 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2313 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), (0x1 << cp->dram_dq_b0), CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL); |
| 2314 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3), 0xa, CBT_WLEV_CTRL3_DQSBX_G); |
| 2315 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 1, CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG); |
| 2316 | mcDELAY_US(1); |
| 2317 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG); |
| 2318 | |
| 2319 | } |
| 2320 | else |
| 2321 | { |
| 2322 | if (operating_fsp == FSP_1) |
| 2323 | { |
| 2324 | DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR); |
| 2325 | } |
| 2326 | |
| 2327 | u4DbgValue = (((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f)); |
| 2328 | u1MR12Value[p->channel][p->rank][operating_fsp] = u4DbgValue; |
| 2329 | mcSHOW_DBG_MSG5(("u4DbgValue = 0x%x\n", u4DbgValue)); |
| 2330 | |
| 2331 | DramcModeRegWriteByRank(p, p->rank, 12, u4DbgValue); |
| 2332 | } |
| 2333 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2334 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2335 | mcDELAY_US(1); |
| 2336 | } |
| 2337 | |
| 2338 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2339 | static void CBTEntryLP45(DRAMC_CTX_T *p, U8 u1FSP, U16 u2Freq) |
| 2340 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2341 | { |
| 2342 | if(p->dram_fsp == FSP_1) |
| 2343 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2344 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2345 | CmdOEOnOff(p, DISABLE, CMDOE_DIS_TO_ONE_CHANNEL); |
| 2346 | cbt_switch_freq(p, CBT_LOW_FREQ); |
| 2347 | CmdOEOnOff(p, ENABLE, CMDOE_DIS_TO_ONE_CHANNEL); |
| 2348 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2349 | #if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2350 | CmdBusTrainingLP4YWA(p, DISABLE); |
| 2351 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2352 | CBTEntryLP4(p, u1FSP, u2Freq); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2353 | if(p->dram_fsp == FSP_1) |
| 2354 | { |
| 2355 | cbt_switch_freq(p, CBT_HIGH_FREQ); |
| 2356 | } |
| 2357 | } |
| 2358 | } |
| 2359 | |
| 2360 | static void CBTExitLP45(DRAMC_CTX_T *p, U8 u1FSP, U8 u2Freq, U8 stateFlag) |
| 2361 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2362 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2363 | { |
| 2364 | if (stateFlag == OUT_CBT || p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) |
| 2365 | { |
| 2366 | (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL; |
| 2367 | CBTExitLP4(p, u1FSP, u2Freq); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2368 | #if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2369 | CmdBusTrainingLP4YWA(p, ENABLE); |
| 2370 | #endif |
| 2371 | } |
| 2372 | } |
| 2373 | } |
| 2374 | |
| 2375 | static void CBTSetVrefLP45(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 u1FSP, U16 u2Freq, U8 stateFlag) |
| 2376 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2377 | { |
| 2378 | if (stateFlag == IN_CBT && p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1) |
| 2379 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2380 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2381 | (p->dram_fsp == FSP_1)? cbt_switch_freq(p, CBT_LOW_FREQ): NULL; |
| 2382 | CBTExitLP4(p, u1FSP, u2Freq); |
| 2383 | |
| 2384 | CBTSetVrefLP4(p, u1VrefRange, u1VrefLevel, u1FSP, stateFlag); |
| 2385 | |
| 2386 | CBTEntryLP4(p, u1FSP, u2Freq); |
| 2387 | if(p->dram_fsp == FSP_1) |
| 2388 | { |
| 2389 | cbt_switch_freq(p, CBT_HIGH_FREQ); |
| 2390 | } |
| 2391 | } |
| 2392 | else |
| 2393 | { |
| 2394 | CBTSetVrefLP4(p, u1VrefRange, u1VrefLevel, u1FSP, stateFlag); |
| 2395 | } |
| 2396 | } |
| 2397 | } |
| 2398 | |
| 2399 | static void CBTScanPI(DRAMC_CTX_T *p, S16 *s2PIStart, S16 *s2PIEnd, S16 *s2PIStep, int autok) |
| 2400 | { |
| 2401 | u16 p2u; |
| 2402 | |
| 2403 | p2u = get_ca_pi_per_ui(p); |
| 2404 | |
| 2405 | if (is_discrete_lpddr4()) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2406 | *s2PIStart = -16; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2407 | else |
| 2408 | *s2PIStart = 0; |
| 2409 | *s2PIEnd = p2u * 3 - 1; |
| 2410 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2411 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2412 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2413 | #if !CBT_MOVE_CA_INSTEAD_OF_CLK |
| 2414 | if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) |
| 2415 | { |
| 2416 | *s2PIStart = -24; |
| 2417 | } |
| 2418 | else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) |
| 2419 | { |
| 2420 | *s2PIStart = -16; |
| 2421 | } |
| 2422 | else |
| 2423 | { |
| 2424 | *s2PIStart = -MAX_CLK_PI_DELAY; |
| 2425 | } |
| 2426 | *s2PIEnd = p2u * 2 - 1; |
| 2427 | #endif |
| 2428 | } |
| 2429 | |
| 2430 | *s2PIStep = get_capi_step(p, autok); |
| 2431 | } |
| 2432 | |
| 2433 | DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok, U8 K_Type) |
| 2434 | { |
| 2435 | U8 u1FinalVref, u1FinalRange=0; //u1VrefLevel, u1VrefRange, |
| 2436 | //U32 u1vrefidx, u1BitIdx, ii; |
| 2437 | //U8 u1VRangeStart, u1VRangeEnd; |
| 2438 | //U8 u1VrefStart, u1VrefEnd, u1VrefStep; |
| 2439 | //U8 u1VrefScanStart, u1VrefScanEnd; |
| 2440 | //U8 u1CBTError_flag=0; |
| 2441 | //U32 u4CompareResult; |
| 2442 | //PASS_WIN_DATA_T FinalWinPerCA[CATRAINING_NUM] = {{0,0,0,0,0}}; |
| 2443 | //U32 uiCA, uiFinishCount, uiTemp; |
| 2444 | //S16 iDelay, pi_dly; |
| 2445 | //S32 iFirstPass_tmp[CATRAINING_NUM], iLastPass_tmp[CATRAINING_NUM]; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 2446 | //uiCAWinSum, |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2447 | U8 operating_fsp; |
| 2448 | U16 operation_frequency; |
| 2449 | //S32 iCA_PerBit_DelayLine[CATRAINING_NUM] = {0}, iCK_MIN = 1000 |
| 2450 | #if CA_PER_BIT_DELAY_CELL |
| 2451 | S16 iCAFinalCenter[CATRAINING_NUM] = {0}; //for CA_PER_BIT |
| 2452 | #endif |
| 2453 | U8 u1CBTEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE); |
| 2454 | U8 backup_MR12Value=0; |
| 2455 | S32 backup_CATrain_CmdDelay=0; |
| 2456 | U32 backup_CATrain_CsDelay=0; |
| 2457 | S32 backup_CATrain_ClkDelay=0; |
| 2458 | U32 backup_CATrain_CmdUIDelay=0; |
| 2459 | U32 backup_CATrain_CmdCKEUIDelay=0; |
| 2460 | U32 backup_CATrain_CmdCKE1UIDelay=0; |
| 2461 | U32 backup_CATrain_CmdMCKDelay=0; |
| 2462 | |
| 2463 | #if ENABLE_EYESCAN_GRAPH |
| 2464 | U8 EyeScan_index[CATRAINING_NUM]; |
| 2465 | #endif |
| 2466 | |
| 2467 | S16 pi_step; //, pi_step_bk; |
| 2468 | S16 pi_start, pi_end; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 2469 | u32 ca_ui; //, ca_ui_tmp |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2470 | u32 ca_mck; //Vca_mck_tmp, a_mck_default |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2471 | u8 ca_pin_num; |
| 2472 | u8 step_respi = AUTOK_RESPI_1; |
| 2473 | //u32 capi_max; |
| 2474 | |
| 2475 | U32 u4RegBackupAddress[] = |
| 2476 | { |
| 2477 | (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)), |
| 2478 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)), |
| 2479 | (DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)), |
| 2480 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)), |
| 2481 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)), |
| 2482 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0)), |
| 2483 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)), |
| 2484 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL2)), |
| 2485 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3)), |
| 2486 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL4)), |
| 2487 | (DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)), |
| 2488 | (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)), |
| 2489 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2490 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), |
| 2491 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), |
| 2492 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)), |
| 2493 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), |
| 2494 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), |
| 2495 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)), |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2496 | }; |
| 2497 | |
| 2498 | CBTScanPI(p, &pi_start, &pi_end, &pi_step, autok); |
| 2499 | while (((1 << step_respi) < pi_step) && autok) |
| 2500 | step_respi++; |
| 2501 | |
| 2502 | #if MRW_CHECK_ONLY |
| 2503 | mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); |
| 2504 | #endif |
| 2505 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2506 | { |
| 2507 | u1FinalRange = u1MR12Value[p->channel][p->rank][p->dram_fsp] >> 6; |
| 2508 | u1FinalVref = u1MR12Value[p->channel][p->rank][p->dram_fsp] & 0x3f; |
| 2509 | ca_pin_num = CATRAINING_NUM_LP4; |
| 2510 | } |
| 2511 | |
| 2512 | #if ENABLE_EYESCAN_GRAPH |
| 2513 | if (u1CBTEyeScanEnable) |
| 2514 | { |
| 2515 | backup_MR12Value = u1MR12Value[p->channel][p->rank][p->dram_fsp]; |
| 2516 | |
| 2517 | backup_CATrain_CmdDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), SHU_R0_CA_CMD0_RG_ARPI_CMD); |
| 2518 | backup_CATrain_CsDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), SHU_R0_CA_CMD0_RG_ARPI_CS); |
| 2519 | backup_CATrain_ClkDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), SHU_R0_CA_CMD0_RG_ARPI_CLK); |
| 2520 | |
| 2521 | backup_CATrain_CmdUIDelay = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7)); |
| 2522 | backup_CATrain_CmdCKEUIDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), SHU_SELPH_CA5_DLY_CKE); |
| 2523 | backup_CATrain_CmdCKE1UIDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), SHU_SELPH_CA6_DLY_CKE1); |
| 2524 | |
| 2525 | backup_CATrain_CmdMCKDelay = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3)); |
| 2526 | |
| 2527 | for (u1vrefidx = 0; u1vrefidx < VREF_VOLTAGE_TABLE_NUM_LP5-1; u1vrefidx++) |
| 2528 | { |
| 2529 | for (uiCA = 0; uiCA < ca_pin_num; uiCA++) |
| 2530 | { |
| 2531 | for (ii = 0; ii < EYESCAN_BROKEN_NUM; ii++) |
| 2532 | { |
| 2533 | gEyeScan_Min[u1vrefidx][uiCA][ii] = EYESCAN_DATA_INVALID; |
| 2534 | gEyeScan_Max[u1vrefidx][uiCA][ii] = EYESCAN_DATA_INVALID; |
| 2535 | } |
| 2536 | } |
| 2537 | } |
| 2538 | } |
| 2539 | #endif |
| 2540 | |
| 2541 | //DUMP_REG_MSG(("\n[dumpRG] CmdBusTraining \n")); |
| 2542 | |
| 2543 | vPrintCalibrationBasicInfo(p); |
| 2544 | mcSHOW_DBG_MSG(("[CmdBusTrainingLP45] new_cbt_mode=%d, autok=%d\n", p->new_cbt_mode, autok)); |
| 2545 | mcSHOW_DBG_MSG2(("pi_start=%d, pi_end=%d, pi_step=%d\n", pi_start, pi_end, pi_step)); |
| 2546 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2547 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2548 | DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); |
| 2549 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2550 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2551 | if (u1CBTEyeScanEnable == DISABLE) |
| 2552 | { |
| 2553 | vSetCalibrationResult(p, DRAM_CALIBRATION_CA_TRAIN, DRAM_FAIL); |
| 2554 | #if CA_PER_BIT_DELAY_CELL |
| 2555 | CATrainingSetPerBitDelayCell(p, iCAFinalCenter, ca_pin_num); |
| 2556 | #endif |
| 2557 | |
| 2558 | } |
| 2559 | |
| 2560 | #if CBT_MOVE_CA_INSTEAD_OF_CLK |
| 2561 | if (u1IsLP4Family(p->dram_type)) |
| 2562 | { |
| 2563 | U8 u1CaPI = 0, u1CaUI = 0; |
| 2564 | |
| 2565 | u1CaUI = 1; |
| 2566 | u1CaPI = 0; |
| 2567 | |
| 2568 | DramcCmdUIDelaySetting(p, u1CaUI); |
| 2569 | |
| 2570 | CBTDelayCACLK(p, u1CaPI); |
| 2571 | } |
| 2572 | #endif |
| 2573 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2574 | |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 2575 | ca_ui = get_ca_ui(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2576 | ca_mck = get_ca_mck(p); |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 2577 | u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2578 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2579 | vAutoRefreshSwitch(p, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2580 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2581 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2582 | //vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1), |
| 2583 | // P_Fld(0x1F, CBT_WLEV_CTRL1_CATRAIN_INTV)); |
| 2584 | set_cbt_wlev_intv(p); |
| 2585 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2586 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2587 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), |
| 2588 | p->rank, TX_SET0_TXRANK); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2589 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2590 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), |
| 2591 | 1, TX_SET0_TXRANKFIX); |
| 2592 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2593 | operating_fsp = p->dram_fsp; |
| 2594 | operation_frequency = p->frequency; |
| 2595 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2596 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2597 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), |
| 2598 | P_Fld(0, DRAMC_PD_CTRL_DCMEN2) | |
| 2599 | P_Fld(1, DRAMC_PD_CTRL_MIOCKCTRLOFF) | |
| 2600 | P_Fld(0, DRAMC_PD_CTRL_PHYCLKDYNGEN) | |
| 2601 | P_Fld(0, DRAMC_PD_CTRL_COMBCLKCTRL) | |
| 2602 | P_Fld(1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF) | |
| 2603 | P_Fld(1, DRAMC_PD_CTRL_TCKFIXON)); |
| 2604 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2605 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2606 | CBTEntryLP45(p, operating_fsp, operation_frequency); |
| 2607 | |
| 2608 | #if PINMUX_AUTO_TEST_PER_BIT_CA |
| 2609 | CheckCADelayCell(p); |
| 2610 | #endif |
| 2611 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2612 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2613 | |
| 2614 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && (BYPASS_VREF_CAL || BYPASS_CBT)) |
| 2615 | if (p->femmc_Ready == 1) |
| 2616 | { |
| 2617 | u1FinalVref = p->pSavetimeData->u1CBTVref_Save[p->channel][p->rank]; |
| 2618 | } |
| 2619 | #endif |
| 2620 | |
| 2621 | if (u1CBTEyeScanEnable) |
| 2622 | { |
| 2623 | u1FinalVref = backup_MR12Value & 0x3f; |
| 2624 | u1FinalRange = (backup_MR12Value>>6) & 1; |
| 2625 | } |
| 2626 | |
| 2627 | mcSHOW_DBG_MSG(("\n[CmdBusTrainingLP45] Vref(ca) range %d: %d\n", u1FinalRange, u1FinalVref)); |
| 2628 | //DUMP_REG_MSG(("\n[CmdBusTrainingLP45] Vref(ca) range %d: %d\n", u1FinalRange, u1FinalVref)); |
| 2629 | |
| 2630 | #ifdef FOR_HQA_TEST_USED |
| 2631 | gFinalCBTVrefCA[p->channel][p->rank] = u1FinalVref; |
| 2632 | #endif |
| 2633 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2634 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2635 | CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, IN_CBT); |
| 2636 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_CBT) |
| 2637 | #if CBT_MOVE_CA_INSTEAD_OF_CLK |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2638 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2639 | DramcCmdUIDelaySetting(p, 0); |
| 2640 | ca_ui = get_ca_ui(p); |
| 2641 | #endif |
| 2642 | #endif |
| 2643 | put_ca_ui(p, ca_ui); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2644 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2645 | if (u1CBTEyeScanEnable == DISABLE) |
| 2646 | { |
| 2647 | CBTSetCACLKResult(p, ca_mck, ca_ui, ca_pin_num); |
| 2648 | } |
| 2649 | else |
| 2650 | { |
| 2651 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0), |
| 2652 | P_Fld(backup_CATrain_CmdDelay, SHU_R0_CA_CMD0_RG_ARPI_CMD) | |
| 2653 | P_Fld(backup_CATrain_ClkDelay, SHU_R0_CA_CMD0_RG_ARPI_CLK) | |
| 2654 | P_Fld(backup_CATrain_CsDelay, SHU_R0_CA_CMD0_RG_ARPI_CS)); |
| 2655 | |
| 2656 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), backup_CATrain_CmdUIDelay); |
| 2657 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), backup_CATrain_CmdCKEUIDelay, SHU_SELPH_CA5_DLY_CKE); |
| 2658 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), backup_CATrain_CmdCKE1UIDelay, SHU_SELPH_CA6_DLY_CKE1); |
| 2659 | |
| 2660 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), backup_CATrain_CmdMCKDelay); |
| 2661 | } |
| 2662 | |
| 2663 | #if ENABLE_EYESCAN_GRAPH |
| 2664 | gEyeScan_CaliDelay[0] = CATrain_CmdDelay[p->channel][p->rank] -pi_start; |
| 2665 | #endif |
| 2666 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2667 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2668 | |
| 2669 | if (u1CBTEyeScanEnable == DISABLE) |
| 2670 | { |
| 2671 | CBTAdjustCS(p, autok); |
| 2672 | } |
| 2673 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2674 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2675 | CBTExitLP45(p, operating_fsp, operation_frequency, OUT_CBT); |
| 2676 | CBTSetVrefLP45(p, u1FinalRange, u1FinalVref, operating_fsp, operation_frequency, OUT_CBT); |
| 2677 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2678 | { |
| 2679 | if (p->dram_fsp == FSP_1) |
| 2680 | { |
| 2681 | #if MR_CBT_SWITCH_FREQ |
| 2682 | DramcModeRegInit_CATerm(p, 0); |
| 2683 | #else |
| 2684 | DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_OP, TO_MR); |
| 2685 | #endif |
| 2686 | } |
| 2687 | } |
| 2688 | |
| 2689 | #if EYESCAN_LOG || defined(FOR_HQA_TEST_USED) |
| 2690 | gFinalCBTVrefDQ[p->channel][p->rank] = u1FinalVref; |
| 2691 | #endif |
| 2692 | |
| 2693 | mcSHOW_DBG_MSG4(("\n[CmdBusTrainingLP45] Done\n")); |
| 2694 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2695 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2696 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK); |
| 2697 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); |
| 2698 | |
| 2699 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2700 | DramcRestoreRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); |
| 2701 | |
| 2702 | return DRAM_OK; |
| 2703 | } |
| 2704 | #endif /* SIMUILATION_CBT */ |
| 2705 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2706 | |
| 2707 | #define WRITE_LEVELING_MOVD_DQS 1 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2708 | |
| 2709 | U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p) |
| 2710 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2711 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2712 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2713 | if (vGet_Div_Mode(p) == DIV4_MODE) |
| 2714 | { |
| 2715 | return MCK_TO_4UI_SHIFT; |
| 2716 | } |
| 2717 | else |
| 2718 | { |
| 2719 | return MCK_TO_8UI_SHIFT; |
| 2720 | } |
| 2721 | } |
| 2722 | } |
| 2723 | |
| 2724 | static DRAM_STATUS_T ExecuteMoveDramCDelay(DRAMC_CTX_T *p, |
| 2725 | REG_TRANSFER_T ui_reg, |
| 2726 | REG_TRANSFER_T mck_reg, |
| 2727 | S8 iShiftUI) |
| 2728 | { |
| 2729 | S32 s4HighLevelDelay, s4DelaySum; |
| 2730 | U32 u4TmpUI, u4TmpMCK; |
| 2731 | U8 ucDataRateDivShift = 0; |
| 2732 | DRAM_STATUS_T MoveResult; |
| 2733 | |
| 2734 | ucDataRateDivShift = u1MCK2UI_DivShift(p); |
| 2735 | |
| 2736 | u4TmpUI = u4IO32ReadFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), ui_reg.u4Fld) & (~(1 << ucDataRateDivShift)); |
| 2737 | u4TmpMCK = u4IO32ReadFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), mck_reg.u4Fld); |
| 2738 | //mcSHOW_DBG_MSG(("Base: u4TmpMCK:%d, u4TmpUI: %d,\n", u4TmpMCK, u4TmpUI)); |
| 2739 | |
| 2740 | s4HighLevelDelay = (u4TmpMCK << ucDataRateDivShift) + u4TmpUI; |
| 2741 | s4DelaySum = (s4HighLevelDelay + iShiftUI); |
| 2742 | |
| 2743 | if (s4DelaySum < 0) |
| 2744 | { |
| 2745 | u4TmpUI = 0; |
| 2746 | u4TmpMCK = 0; |
| 2747 | MoveResult = DRAM_FAIL; |
| 2748 | } |
| 2749 | else |
| 2750 | { |
| 2751 | u4TmpMCK = s4DelaySum >> ucDataRateDivShift; |
| 2752 | u4TmpUI = s4DelaySum - (u4TmpMCK << ucDataRateDivShift); |
| 2753 | MoveResult = DRAM_OK; |
| 2754 | } |
| 2755 | |
| 2756 | vIO32WriteFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), u4TmpUI, ui_reg.u4Fld); |
| 2757 | vIO32WriteFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), u4TmpMCK, mck_reg.u4Fld); |
| 2758 | //mcSHOW_DBG_MSG(("[%d] Final ==> u4TmpMCK:%d, u4TmpUI: %d,\n", iShiftUI, u4TmpMCK, u4TmpUI)); |
| 2759 | |
| 2760 | return MoveResult; |
| 2761 | } |
| 2762 | |
| 2763 | static void _LoopAryToDelay(DRAMC_CTX_T *p, |
| 2764 | REG_TRANSFER_T *ui_reg, |
| 2765 | REG_TRANSFER_T *mck_reg, |
| 2766 | U8 u8RG_num, |
| 2767 | S8 iShiftUI, |
| 2768 | BYTES_T eByteIdx) |
| 2769 | { |
| 2770 | U8 idx = 0, step = 1; |
| 2771 | if (eByteIdx == BYTE_0) |
| 2772 | { |
| 2773 | idx = 0; |
| 2774 | step = 2; |
| 2775 | } |
| 2776 | else if (eByteIdx == BYTE_1) |
| 2777 | { |
| 2778 | idx = 1; |
| 2779 | step = 2; |
| 2780 | } |
| 2781 | |
| 2782 | for (; idx < u8RG_num; idx += step) |
| 2783 | { |
| 2784 | ExecuteMoveDramCDelay(p, ui_reg[idx], mck_reg[idx], iShiftUI); |
| 2785 | } |
| 2786 | } |
| 2787 | |
| 2788 | static void LP4_ShiftDQSUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) |
| 2789 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2790 | |
| 2791 | REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS0}, |
| 2792 | {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_DQS1}}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2793 | REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS0}, |
| 2794 | {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_DQS1}}; |
| 2795 | |
| 2796 | _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, |
| 2797 | sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), |
| 2798 | iShiftUI, eByteIdx); |
| 2799 | } |
| 2800 | |
| 2801 | void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) |
| 2802 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2803 | |
| 2804 | REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS0}, |
| 2805 | {DRAMC_REG_SHU_SELPH_DQS1, SHU_SELPH_DQS1_DLY_OEN_DQS1}}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2806 | REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS0}, |
| 2807 | {DRAMC_REG_SHU_SELPH_DQS0, SHU_SELPH_DQS0_TXDLY_OEN_DQS1}}; |
| 2808 | |
| 2809 | _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, |
| 2810 | sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), |
| 2811 | iShiftUI, eByteIdx); |
| 2812 | } |
| 2813 | |
| 2814 | static void ShiftDQUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) |
| 2815 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2816 | |
| 2817 | REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM0}, |
| 2818 | {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_DQM1}, |
| 2819 | {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ0}, |
| 2820 | {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_DQ1}}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2821 | REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM0}, |
| 2822 | {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_DQM1}, |
| 2823 | {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_DQ0}, |
| 2824 | {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_DQ1}}; |
| 2825 | |
| 2826 | _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, |
| 2827 | sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), |
| 2828 | iShiftUI, eByteIdx); |
| 2829 | } |
| 2830 | |
| 2831 | static void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) |
| 2832 | { |
| 2833 | U8 backup_rank, rk_i; |
| 2834 | backup_rank = u1GetRank(p); |
| 2835 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2836 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2837 | for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++) |
| 2838 | { |
| 2839 | vSetRank(p, rk_i); |
| 2840 | ShiftDQUI(p, iShiftUI, eByteIdx); |
| 2841 | } |
| 2842 | vSetRank(p, backup_rank); |
| 2843 | } |
| 2844 | |
| 2845 | static void ShiftDQ_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) |
| 2846 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2847 | REG_TRANSFER_T TransferUIRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM0}, |
| 2848 | {DRAMC_REG_SHURK_SELPH_DQ3, SHURK_SELPH_DQ3_DLY_OEN_DQM1}, |
| 2849 | {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ0}, |
| 2850 | {DRAMC_REG_SHURK_SELPH_DQ2, SHURK_SELPH_DQ2_DLY_OEN_DQ1}}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2851 | REG_TRANSFER_T TransferMCKRegs[] = {{DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0}, |
| 2852 | {DRAMC_REG_SHURK_SELPH_DQ1, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1}, |
| 2853 | {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0}, |
| 2854 | {DRAMC_REG_SHURK_SELPH_DQ0, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1}}; |
| 2855 | |
| 2856 | _LoopAryToDelay(p, TransferUIRegs, TransferMCKRegs, |
| 2857 | sizeof(TransferUIRegs) / sizeof(REG_TRANSFER_T), |
| 2858 | iShiftUI, eByteIdx); |
| 2859 | } |
| 2860 | |
| 2861 | void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) |
| 2862 | { |
| 2863 | U8 backup_rank, rk_i; |
| 2864 | backup_rank = u1GetRank(p); |
| 2865 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2866 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2867 | for (rk_i = RANK_0; rk_i < p->support_rank_num; rk_i++) |
| 2868 | { |
| 2869 | vSetRank(p, rk_i); |
| 2870 | ShiftDQ_OENUI(p, iShiftUI, eByteIdx); |
| 2871 | } |
| 2872 | vSetRank(p, backup_rank); |
| 2873 | } |
| 2874 | |
| 2875 | //void WriteLevelingMoveDQSInsteadOfCLK(DRAMC_CTX_T *p, S8 iShiftUI) |
| 2876 | //{ |
| 2877 | // LP4_ShiftDQSUI(p, iShiftUI, ALL_BYTES); |
| 2878 | // LP4_ShiftDQUI(p, iShiftUI, ALL_BYTES); |
| 2879 | //} |
| 2880 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2881 | static void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx) |
| 2882 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2883 | { |
| 2884 | LP4_ShiftDQSUI(p, iShiftUI, eByteIdx); |
| 2885 | LP4_ShiftDQS_OENUI(p, iShiftUI, eByteIdx); |
| 2886 | } |
| 2887 | } |
| 2888 | |
| 2889 | U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p) |
| 2890 | { |
| 2891 | if ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400)) |
| 2892 | return TRUE; |
| 2893 | else |
| 2894 | return FALSE; |
| 2895 | } |
| 2896 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2897 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2898 | static void vSetDramMRWriteLevelingOnOff(DRAMC_CTX_T *p, U8 u1OnOff) |
| 2899 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2900 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2901 | if (u1OnOff) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2902 | u1MR02Value[p->dram_fsp] |= 0x80; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2903 | else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2904 | u1MR02Value[p->dram_fsp] &= 0x7f; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2905 | |
| 2906 | DramcModeRegWriteByRank(p, p->rank, 2, u1MR02Value[p->dram_fsp]); |
| 2907 | } |
| 2908 | |
| 2909 | U8 u1IsPhaseMode(DRAMC_CTX_T *p) |
| 2910 | { |
| 2911 | if ((vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) || (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)) |
| 2912 | return TRUE; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2913 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2914 | return FALSE; |
| 2915 | } |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2916 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2917 | #if 0 |
| 2918 | static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg) |
| 2919 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2920 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2921 | U32 u4TimeCnt = DDR_HW_AUTOK_POLLING_CNT; |
| 2922 | DRAM_STATUS_T u4RespFlag = 0; |
| 2923 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2924 | vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2925 | vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 1, TriggerReg.u4Fld); |
| 2926 | do |
| 2927 | { |
| 2928 | u4RespFlag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(RepondsReg.u4Addr), RepondsReg.u4Fld); |
| 2929 | u4TimeCnt --; |
| 2930 | mcDELAY_US(1); |
| 2931 | }while ((u4RespFlag == 0) && (u4TimeCnt > 0)); |
| 2932 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2933 | if (u4TimeCnt == 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2934 | { |
| 2935 | mcSHOW_ERR_MSG(("[DramcTriggerAndWait] Wait 0x%x respond fail (time out)\n", RepondsReg.u4Addr)); |
| 2936 | return DRAM_FAIL; |
| 2937 | } |
| 2938 | |
| 2939 | return DRAM_OK; |
| 2940 | } |
| 2941 | |
| 2942 | static DRAM_STATUS_T DramcTriggerAndWait_For_RX_AutoK_WorkAround(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerReg, REG_TRANSFER_T RepondsReg, U16 u16DelayStep) |
| 2943 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2944 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2945 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0), 0, MISC_RX_AUTOK_CFG0_RX_CAL_STEP); |
| 2946 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2947 | vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2948 | vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 1, TriggerReg.u4Fld); |
| 2949 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2950 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2951 | vIO32WriteFldAlign(DRAMC_REG_ADDR(TriggerReg.u4Addr), 0, TriggerReg.u4Fld); |
| 2952 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2953 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2954 | DramPhyReset(p); |
| 2955 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2956 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2957 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0), u16DelayStep, MISC_RX_AUTOK_CFG0_RX_CAL_STEP); |
| 2958 | |
| 2959 | return DramcTriggerAndWait(p, TriggerReg, RepondsReg); |
| 2960 | } |
| 2961 | #endif |
| 2962 | #if (SIMULATION_WRITE_LEVELING == 1) |
| 2963 | #define DQPI_PER_UI (32) |
| 2964 | #define STORAGED_DLY_UNIT (24) |
| 2965 | static void WriteLevelingScanRange_PI(DRAMC_CTX_T *p, S32 *ps4DlyBegin, S32 *ps4DlyEnd, U8 *pu1PIStep, S16 *pPI_bound, WLEV_DELAY_BASED_T stDelayBase) |
| 2966 | { |
| 2967 | S32 s4DlyBegin = 0, s4DlyEnd; |
| 2968 | U8 u1PIStep; |
| 2969 | S16 PI_bound; |
| 2970 | |
| 2971 | if (stDelayBase == PI_BASED) |
| 2972 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2973 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2974 | s4DlyBegin = WRITE_LEVELING_MOVD_DQS * 32 - MAX_CLK_PI_DELAY - 1; |
| 2975 | s4DlyEnd = s4DlyBegin + 64 - 1; |
| 2976 | |
| 2977 | if ((vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)) |
| 2978 | { |
| 2979 | u1PIStep = 16; |
| 2980 | PI_bound = 32; |
| 2981 | } |
| 2982 | else if ((vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE)) |
| 2983 | { |
| 2984 | u1PIStep = 8; |
| 2985 | PI_bound = 32; |
| 2986 | } |
| 2987 | else |
| 2988 | { |
| 2989 | u1PIStep = 1; |
| 2990 | PI_bound = 64; |
| 2991 | } |
| 2992 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2993 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2994 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2995 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 2996 | s4DlyBegin = 0; |
| 2997 | s4DlyEnd = 2 * STORAGED_DLY_UNIT; |
| 2998 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 2999 | u1PIStep = 1; |
| 3000 | PI_bound = 1024; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3001 | } |
| 3002 | mcSHOW_DBG_MSG2(("Delay: %d->%d, Step: %d, Bound: %d\n", s4DlyBegin, s4DlyEnd, u1PIStep, PI_bound)); |
| 3003 | |
| 3004 | *ps4DlyBegin = s4DlyBegin; |
| 3005 | *ps4DlyEnd = s4DlyEnd; |
| 3006 | *pu1PIStep = u1PIStep; |
| 3007 | *pPI_bound = PI_bound; |
| 3008 | |
| 3009 | } |
| 3010 | |
| 3011 | #if ENABLE_WDQS_MODE_2 |
| 3012 | void WriteLevelingPosCal(DRAMC_CTX_T *p, WLEV_DELAY_BASED_T stDelayBase) |
| 3013 | { |
| 3014 | DRAM_RANK_T backup_rank = u1GetRank(p); |
| 3015 | U8 wrlevel_dqs_delay[DQS_BYTE_NUMBER] = {0}; |
| 3016 | U8 rank_i = 0; |
| 3017 | |
| 3018 | if((wrlevel_dqs_final_delay[RANK_0][0] - wrlevel_dqs_final_delay[RANK_1][0])>=9 || |
| 3019 | (wrlevel_dqs_final_delay[RANK_0][0] - wrlevel_dqs_final_delay[RANK_1][0])<=-9 || |
| 3020 | (wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])>=9 || |
| 3021 | (wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])<=-9 ) |
| 3022 | { |
| 3023 | mcSHOW_ERR_MSG(("[WARNING] Larger WL R2R !!\n")); |
| 3024 | #if CHECK_HQA_CRITERIA |
| 3025 | while(1); |
| 3026 | #endif |
| 3027 | } |
| 3028 | |
| 3029 | wrlevel_dqs_delay[0] = (wrlevel_dqs_final_delay[RANK_0][0] + wrlevel_dqs_final_delay[RANK_1][0]) >> 1; |
| 3030 | wrlevel_dqs_delay[1] = (wrlevel_dqs_final_delay[RANK_0][1] + wrlevel_dqs_final_delay[RANK_1][1]) >> 1; |
| 3031 | |
| 3032 | wrlevel_dqs_final_delay[RANK_0][0] = wrlevel_dqs_final_delay[RANK_1][0] = wrlevel_dqs_delay[0]; |
| 3033 | wrlevel_dqs_final_delay[RANK_0][1] = wrlevel_dqs_final_delay[RANK_1][1] = wrlevel_dqs_delay[1]; |
| 3034 | |
| 3035 | for (rank_i = p->rank; rank_i < p->support_rank_num; rank_i++) |
| 3036 | { |
| 3037 | vSetRank(p, rank_i); |
| 3038 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3039 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3040 | if (stDelayBase == PI_BASED) |
| 3041 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3042 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3043 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0); |
| 3044 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1); |
| 3045 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3046 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3047 | { |
| 3048 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0); |
| 3049 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1); |
| 3050 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0); |
| 3051 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1); |
| 3052 | } |
| 3053 | } |
| 3054 | |
| 3055 | vSetRank(p, backup_rank); |
| 3056 | |
| 3057 | mcSHOW_DBG_MSG(("[WriteLevelingPosCal] DQS PI B0/B1 = %d/%d\n", wrlevel_dqs_delay[0], wrlevel_dqs_delay[1])); |
| 3058 | } |
| 3059 | #endif |
| 3060 | |
| 3061 | #define SET_PATTERN_MANUALLY_FOR_DEBUG 1 |
| 3062 | DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase) |
| 3063 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3064 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3065 | DRAM_STATUS_T KResult = DRAM_FAIL; |
| 3066 | |
| 3067 | //U8 *uiLPDDR_O1_Mapping = NULL; |
| 3068 | //U32 u4value = 0, u4dq_o1 = 0 u4value1 = 0, u4dq_o1_tmp[DQS_BYTE_NUMBER]; |
Arthur Heymans | 9781411 | 2023-04-19 10:13:44 +0200 | [diff] [blame^] | 3069 | U8 byte_i, rank_i, ucDoneFlg = 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3070 | //S32 iDelay, ClockDelayMax; |
| 3071 | //U8 ucStatus[DQS_BYTE_NUMBER], ucdq_o1[DQS_BYTE_NUMBER], ucdq_o1_shift[DQS_BYTE_NUMBER] |
| 3072 | //U8 ucHW_cmp_raw_data, uccmp_result[DQS_BYTE_NUMBER]; |
| 3073 | DRAM_RANK_T backup_rank; |
| 3074 | |
| 3075 | //S32 wrlevel_dq_delay[DQS_BYTE_NUMBER]; // 3 is channel number |
| 3076 | S32 wrlevel_dqs_delay[DQS_BYTE_NUMBER]; // 3 is channel number |
| 3077 | |
| 3078 | //u32 bitmap31_0[DQS_BYTE_NUMBER] = {0}; |
| 3079 | //u32 bitmap63_32[DQS_BYTE_NUMBER] = {0}; |
| 3080 | //u8 idx = 0; |
| 3081 | //U16 _bitmap_stored_num = 0; |
| 3082 | |
| 3083 | S32 s4DlyBegin, s4DlyEnd; |
| 3084 | U8 u1PIStep; |
| 3085 | U8 u1OverBoundCnt = 0; //jj = 0 |
| 3086 | S16 PI_bound = 64; |
| 3087 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3088 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3089 | vAutoRefreshSwitch(p, DISABLE); |
| 3090 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3091 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3092 | if (!p) |
| 3093 | { |
| 3094 | mcSHOW_ERR_MSG(("context NULL\n")); |
| 3095 | return DRAM_FAIL; |
| 3096 | } |
| 3097 | //DUMP_REG_MSG(("\n[dumpRG] DramcWriteLeveling \n")); |
| 3098 | #if VENDER_JV_LOG |
| 3099 | vPrintCalibrationBasicInfo_ForJV(p); |
| 3100 | #else |
| 3101 | vPrintCalibrationBasicInfo(p); |
| 3102 | #endif |
| 3103 | mcSHOW_DBG_MSG(("[Write Leveling] autok: %d\n", isAutoK)); |
| 3104 | |
| 3105 | fgwrlevel_done = 0; |
| 3106 | backup_rank = u1GetRank(p); |
| 3107 | |
| 3108 | //DramcRankSwap(p, p->rank); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3109 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3110 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), p->rank, TX_SET0_TXRANK); |
| 3111 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_TXRANKFIX); |
| 3112 | |
| 3113 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3114 | U32 u4RegBackupAddress[] = |
| 3115 | { |
| 3116 | (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)), |
| 3117 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0)), |
| 3118 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1)), |
| 3119 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL3)), |
| 3120 | (DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL5)), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3121 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF)), |
| 3122 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF)), |
| 3123 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF)), |
| 3124 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL)), |
| 3125 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL)), |
| 3126 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL)), |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3127 | (DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)) |
| 3128 | }; |
| 3129 | DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 3130 | |
| 3131 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3132 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3133 | vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAIL); |
| 3134 | |
| 3135 | #if MRW_CHECK_ONLY |
| 3136 | mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__)); |
| 3137 | #endif |
| 3138 | |
| 3139 | if (p->isWLevInitShift[p->channel] == FALSE) |
| 3140 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3141 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3142 | #if __ETT__ |
| 3143 | while (stDelayBase != PI_BASED); |
| 3144 | #else |
| 3145 | ASSERT(stDelayBase == PI_BASED); |
| 3146 | #endif |
| 3147 | |
| 3148 | p->isWLevInitShift[p->channel] = TRUE; |
| 3149 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3150 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3151 | ShiftDQUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); |
| 3152 | ShiftDQ_OENUI_AllRK(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); |
| 3153 | ShiftDQSWCK_UI(p, -WRITE_LEVELING_MOVD_DQS, ALL_BYTES); |
| 3154 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3155 | |
| 3156 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), 0, SHU_R0_B0_DQ0_ARPI_PBYTE_B0); |
| 3157 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), 0, SHU_R0_B1_DQ0_ARPI_PBYTE_B1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3158 | |
| 3159 | } |
| 3160 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3161 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3162 | WriteLevelingScanRange_PI(p, &s4DlyBegin, &s4DlyEnd, &u1PIStep, &PI_bound, stDelayBase); |
| 3163 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3164 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3165 | if (stDelayBase == DLY_BASED) |
| 3166 | isAutoK = FALSE; |
| 3167 | |
| 3168 | |
| 3169 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_WRITELEVELING) |
| 3170 | if (p->femmc_Ready == 1) |
| 3171 | { |
| 3172 | wrlevel_dqs_final_delay[p->rank][0] = p->pSavetimeData->u1WriteLeveling_bypass_Save[p->channel][p->rank][0]; |
| 3173 | wrlevel_dqs_final_delay[p->rank][1] = p->pSavetimeData->u1WriteLeveling_bypass_Save[p->channel][p->rank][1]; |
| 3174 | |
| 3175 | ucDoneFlg = 0xff; |
| 3176 | KResult = DRAM_OK; |
| 3177 | vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAST_K); |
| 3178 | } |
| 3179 | #endif |
| 3180 | |
| 3181 | if (u1OverBoundCnt > 0) |
| 3182 | ShiftDQSWCK_UI(p, -u1OverBoundCnt * (PI_bound / DQPI_PER_UI), ALL_BYTES); |
| 3183 | |
| 3184 | if (ucDoneFlg == 0xff) |
| 3185 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3186 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3187 | fgwrlevel_done = 1; |
| 3188 | KResult = DRAM_OK; |
| 3189 | } |
| 3190 | else |
| 3191 | { |
| 3192 | KResult = DRAM_FAIL; |
| 3193 | #if PIN_CHECK_TOOL |
| 3194 | PINInfo_flashtool.WL_ERR_FLAG|=(0x1<<(p->channel*2+p->rank)); |
| 3195 | #endif |
| 3196 | } |
| 3197 | vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, KResult); |
| 3198 | mcSHOW_DBG_MSG2(("pass bytecount = 0x%x (0xff: all bytes pass) \n\n", ucDoneFlg)); |
| 3199 | |
| 3200 | #if defined(FOR_HQA_TEST_USED) && defined(FOR_HQA_REPORT_USED) |
| 3201 | if (gHQALog_flag == 1) |
| 3202 | { |
| 3203 | for (byte_i = 0; byte_i < DQS_BYTE_NUMBER; byte_i++) |
| 3204 | { |
| 3205 | if (byte_i==0) |
| 3206 | { |
| 3207 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_MCK_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_DQS0), NULL); |
| 3208 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_UI_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_DQS0), NULL); |
| 3209 | } |
| 3210 | else |
| 3211 | { |
| 3212 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_MCK_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_DQS1), NULL); |
| 3213 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_UI_DQS", byte_i, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_DQS1), NULL); |
| 3214 | } |
| 3215 | |
| 3216 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "", "WriteLeveling_DQS", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i], NULL); |
| 3217 | } |
| 3218 | } |
| 3219 | #endif |
| 3220 | |
| 3221 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3222 | vSetDramMRWriteLevelingOnOff(p, DISABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3223 | |
| 3224 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3225 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3226 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL0), 0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN); |
| 3227 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3228 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3229 | O1PathOnOff(p, OFF); |
| 3230 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3231 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3232 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK); |
| 3233 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANKFIX); |
| 3234 | |
| 3235 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3236 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 3237 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3238 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3239 | for (byte_i = 0; byte_i < DQS_BYTE_NUMBER; byte_i++) |
| 3240 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3241 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3242 | mcSHOW_DBG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i])); |
| 3243 | //DUMP_REG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i])); |
| 3244 | if (wrlevel_dqs_final_delay[p->rank][byte_i] >= PI_bound) |
| 3245 | { |
| 3246 | ShiftDQSWCK_UI(p, (wrlevel_dqs_final_delay[p->rank][byte_i] / PI_bound) * (PI_bound / DQPI_PER_UI), byte_i); |
| 3247 | |
| 3248 | wrlevel_dqs_final_delay[p->rank][byte_i] %= PI_bound; |
| 3249 | } |
| 3250 | |
| 3251 | wrlevel_dqs_delay[byte_i] = wrlevel_dqs_final_delay[p->rank][byte_i]; |
| 3252 | mcSHOW_DBG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i])); |
| 3253 | //DUMP_REG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i])); |
| 3254 | } |
| 3255 | |
| 3256 | for (rank_i = p->rank; rank_i < RANK_MAX; rank_i++) |
| 3257 | { |
| 3258 | vSetRank(p, rank_i); |
| 3259 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3260 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3261 | if (stDelayBase == PI_BASED) |
| 3262 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3263 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3264 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), wrlevel_dqs_delay[0], SHU_R0_B0_DQ0_ARPI_PBYTE_B0); |
| 3265 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), wrlevel_dqs_delay[1], SHU_R0_B1_DQ0_ARPI_PBYTE_B1); |
| 3266 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3267 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3268 | { |
| 3269 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0); |
| 3270 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1); |
| 3271 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), wrlevel_dqs_delay[0], SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0); |
| 3272 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), wrlevel_dqs_delay[1], SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1); |
| 3273 | } |
| 3274 | } |
| 3275 | |
| 3276 | vSetRank(p, backup_rank); |
| 3277 | |
| 3278 | mcSHOW_DBG_MSG4(("[DramcWriteLeveling] Done\n\n")); |
| 3279 | |
| 3280 | return KResult; |
| 3281 | } |
| 3282 | #endif //SIMULATION_WRITE_LEVELING |
| 3283 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3284 | #if (fcFOR_CHIP_ID == fcA60868) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3285 | static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_sel) |
| 3286 | { |
| 3287 | U32 u4Response = 0; |
| 3288 | U32 u4TimeCnt = TIME_OUT_CNT; |
| 3289 | U32 u4BackupCKECTRL; |
| 3290 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3291 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3292 | u4BackupCKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); |
| 3293 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3294 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3295 | CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ALL_CHANNEL); |
| 3296 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3297 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3298 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), runtime_SW_cmd_sel, SWCMD_EN_RTSWCMD_SEL); |
| 3299 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3300 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3301 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x30, RTSWCMD_CNT_RTSWCMD_CNT); |
| 3302 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), |
| 3303 | P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) | |
| 3304 | P_Fld(p->rank, SWCMD_CTRL2_RTSWCMD_RK)); |
| 3305 | |
| 3306 | U8 _rank_idx_CAS_OFF = 0; |
| 3307 | U8 _is_differential_mode = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL), SHU_WCKCTRL_WCKDUAL); |
| 3308 | while (1) |
| 3309 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3310 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3311 | if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF) |
| 3312 | { |
| 3313 | if ( _is_differential_mode == 0) |
| 3314 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), _rank_idx_CAS_OFF, SWCMD_CTRL2_RTSWCMD_RK); |
| 3315 | } |
| 3316 | else if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_FS) |
| 3317 | { |
| 3318 | if (_is_differential_mode == 0) |
| 3319 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), 0x3, SWCMD_CTRL2_RTSWCMD_RK); |
| 3320 | } |
| 3321 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3322 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3323 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); |
| 3324 | |
| 3325 | do |
| 3326 | { |
| 3327 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); |
| 3328 | u4TimeCnt --; |
| 3329 | mcDELAY_US(1); |
| 3330 | }while ((u4Response == 0) && (u4TimeCnt > 0)); |
| 3331 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3332 | if (u4TimeCnt == 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3333 | { |
| 3334 | mcSHOW_ERR_MSG(("[LP5 RT SW Cmd ] Resp fail (time out)\n")); |
| 3335 | } |
| 3336 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3337 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3338 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); |
| 3339 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3340 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3341 | if (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF) |
| 3342 | { |
| 3343 | if (_is_differential_mode == 0) |
| 3344 | if (++_rank_idx_CAS_OFF <= 1) |
| 3345 | continue; |
| 3346 | } |
| 3347 | |
| 3348 | break; |
| 3349 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3350 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3351 | vIO32Write4B_All(DRAMC_REG_CKECTRL, u4BackupCKECTRL); |
| 3352 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3353 | #else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3354 | #if 0 |
| 3355 | static void RunTime_SW_Cmd(DRAMC_CTX_T *p, RUNTIME_SWCMD_SEL_T runtime_SW_cmd_sel) |
| 3356 | { |
| 3357 | U32 u4Response = 0; |
| 3358 | U32 u4TimeCnt = TIME_OUT_CNT; |
| 3359 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3360 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3361 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), runtime_SW_cmd_sel, SWCMD_EN_RTSWCMD_SEL); |
| 3362 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3363 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3364 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x30, RTSWCMD_CNT_RTSWCMD_CNT); |
| 3365 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), |
| 3366 | P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) | |
| 3367 | P_Fld(p->rank, SWCMD_CTRL2_RTSWCMD_RK)); |
| 3368 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3369 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3370 | if ((runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_FS) || (runtime_SW_cmd_sel == RUNTIME_SWCMD_CAS_OFF)) |
| 3371 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), 0x3, SWCMD_CTRL2_RTSWCMD_RK); |
| 3372 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3373 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3374 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); |
| 3375 | |
| 3376 | do |
| 3377 | { |
| 3378 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); |
| 3379 | u4TimeCnt --; |
| 3380 | mcDELAY_US(1); |
| 3381 | }while ((u4Response == 0) && (u4TimeCnt > 0)); |
| 3382 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3383 | if (u4TimeCnt == 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3384 | { |
| 3385 | mcSHOW_ERR_MSG(("[LP5 RT SW Cmd ] Resp fail (time out)\n")); |
| 3386 | } |
| 3387 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3388 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3389 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); |
| 3390 | |
| 3391 | } |
| 3392 | #endif |
| 3393 | #endif |
| 3394 | |
| 3395 | #if (SIMULATION_DUTY_CYC_MONITOR == 1) |
| 3396 | static U8 FetchRGSettingVal(int step_val) |
| 3397 | { |
| 3398 | if (step_val <= 0) |
| 3399 | return (U8)(-step_val); |
| 3400 | else |
| 3401 | return ((U8)step_val | 0x08); |
| 3402 | } |
| 3403 | |
| 3404 | DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p) |
| 3405 | { |
| 3406 | U8 backup_rank; |
| 3407 | // U8 u8ResultDutyCycMonitor[WHOLE_STEPS_NUM] = {0}; |
| 3408 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3409 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3410 | if (!p) |
| 3411 | { |
| 3412 | mcSHOW_ERR_MSG(("context NULL\n")); |
| 3413 | return DRAM_FAIL; |
| 3414 | } |
| 3415 | |
| 3416 | vAutoRefreshSwitch(p, DISABLE); |
| 3417 | //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 3418 | |
| 3419 | backup_rank = u1GetRank(p); |
| 3420 | |
| 3421 | RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_FS); |
| 3422 | |
| 3423 | int i = -7; |
| 3424 | for (i = -7; i <= 7; i++) |
| 3425 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3426 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3427 | U8 u8RGSettingVal = FetchRGSettingVal(i); |
| 3428 | mcSHOW_ERR_MSG(("Set value %d into MR30\n", u8RGSettingVal)); |
| 3429 | MRWriteFldMulti(p, 30, P_Fld(u8RGSettingVal, MR30_DCAU) | |
| 3430 | P_Fld(u8RGSettingVal, MR30_DCAL), |
| 3431 | TO_MR); |
| 3432 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3433 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3434 | DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_START_STOP, TO_MR); |
| 3435 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3436 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3437 | mcDELAY_US(2); |
| 3438 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3439 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3440 | DramcMRWriteFldAlign(p, 26, 1, MR26_DCM_FLIP, TO_MR); |
| 3441 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3442 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3443 | mcDELAY_US(2); |
| 3444 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3445 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3446 | DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_FLIP, TO_MR); |
| 3447 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3448 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3449 | mcDELAY_US(2); |
| 3450 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3451 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3452 | DramcMRWriteFldAlign(p, 26, 0, MR26_DCM_START_STOP, TO_MR); |
| 3453 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3454 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3455 | mcDELAY_US(2); |
| 3456 | |
| 3457 | mcSHOW_ERR_MSG(("Wait tMRD and MRR MR26\n")); |
| 3458 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3459 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3460 | |
| 3461 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3462 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3463 | |
| 3464 | RunTime_SW_Cmd(p, RUNTIME_SWCMD_CAS_OFF); |
| 3465 | |
| 3466 | vAutoRefreshSwitch(p, ENABLE); |
| 3467 | //CKEFixOnOff(p, p->rank, CKE_DYNAMIC, TO_ONE_CHANNEL); |
| 3468 | |
| 3469 | vSetRank(p, backup_rank); |
| 3470 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3471 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3472 | |
| 3473 | |
| 3474 | void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p) |
| 3475 | { |
| 3476 | U8 u1RankIdx, u1RankIdxBak; |
| 3477 | U32 u4WbrBackup = GetDramcBroadcast(); |
| 3478 | |
| 3479 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 3480 | u1RankIdxBak = u1GetRank(p); |
| 3481 | |
| 3482 | for(u1RankIdx=RANK_0; u1RankIdx<RANK_MAX; u1RankIdx++) |
| 3483 | { |
| 3484 | vSetRank(p, u1RankIdx); |
| 3485 | |
| 3486 | vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_CA_TXDLY0, |
| 3487 | P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA0_DLY) | |
| 3488 | P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA1_DLY) | |
| 3489 | P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA2_DLY) | |
| 3490 | P_Fld(0, SHU_R0_CA_TXDLY0_TX_ARCA3_DLY)); |
| 3491 | |
| 3492 | vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_CA_TXDLY1, |
| 3493 | P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA4_DLY) | |
| 3494 | P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA5_DLY) | |
| 3495 | P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA6_DLY) | |
| 3496 | P_Fld(0, SHU_R0_CA_TXDLY1_TX_ARCA7_DLY)); |
| 3497 | |
| 3498 | vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B0_TXDLY0, P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0) |
| 3499 | | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) |
| 3500 | | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
| 3501 | | P_Fld(0, SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0)); |
| 3502 | vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B0_TXDLY1, P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0) |
| 3503 | | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) |
| 3504 | | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
| 3505 | | P_Fld(0, SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0)); |
| 3506 | |
| 3507 | vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B1_TXDLY0, P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1) |
| 3508 | | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) |
| 3509 | | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
| 3510 | | P_Fld(0, SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1)); |
| 3511 | vIO32WriteFldMulti_All(DDRPHY_REG_SHU_R0_B1_TXDLY1, P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1) |
| 3512 | | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) |
| 3513 | | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
| 3514 | | P_Fld(0, SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1)); |
| 3515 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_R0_B0_TXDLY3, 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); |
| 3516 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_R0_B1_TXDLY3, 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); |
| 3517 | } |
| 3518 | |
| 3519 | vSetRank(p, u1RankIdxBak); |
| 3520 | DramcBroadcastOnOff(u4WbrBackup); |
| 3521 | } |
| 3522 | |
| 3523 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3524 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3525 | void DramPhyReset(DRAMC_CTX_T *p) |
| 3526 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3527 | |
| 3528 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 1, RX_SET0_RDATRST); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3529 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMPHYRST); |
| 3530 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3531 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3532 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), |
| 3533 | P_Fld(0, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | |
| 3534 | P_Fld(0, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0)); |
| 3535 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), |
| 3536 | P_Fld(0, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | |
| 3537 | P_Fld(0, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1)); |
| 3538 | mcDELAY_US(1);//delay 10ns |
| 3539 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), |
| 3540 | P_Fld(1, B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1) | |
| 3541 | P_Fld(1, B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1)); |
| 3542 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), |
| 3543 | P_Fld(1, B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0) | |
| 3544 | P_Fld(1, B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0)); |
| 3545 | |
| 3546 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMPHYRST); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3547 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, RX_SET0_RDATRST); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3548 | } |
| 3549 | |
| 3550 | #if SIMULATION_LP4_ZQ |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3551 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3552 | #if ZQ_SWCMD_MODE |
| 3553 | static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) |
| 3554 | { |
| 3555 | U32 u4Response; |
| 3556 | U32 u4TimeCnt = TIME_OUT_CNT; |
| 3557 | U32 u4SWCMDEN, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL; |
| 3558 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3559 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3560 | u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); |
| 3561 | u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)); |
| 3562 | u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); |
| 3563 | u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); |
| 3564 | |
| 3565 | mcSHOW_DBG_MSG4(("[ZQCalibration]\n")); |
| 3566 | //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); |
| 3567 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3568 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3569 | DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL); |
| 3570 | mcDELAY_US(1); |
| 3571 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3572 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3573 | CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 3574 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3575 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3576 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_SWTRIG_ZQ_RK); |
| 3577 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3578 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3579 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN_SWTRIG); |
| 3580 | |
| 3581 | do |
| 3582 | { |
| 3583 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQC_SWTRIG_RESPONSE); |
| 3584 | u4TimeCnt --; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3585 | mcDELAY_US(1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3586 | |
| 3587 | mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt)); |
| 3588 | //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); |
| 3589 | }while((u4Response==0) &&(u4TimeCnt>0)); |
| 3590 | |
| 3591 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN_SWTRIG); |
| 3592 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3593 | if(u4TimeCnt==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3594 | { |
| 3595 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); |
| 3596 | mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n")); |
| 3597 | //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n")); |
| 3598 | return DRAM_FAIL; |
| 3599 | } |
| 3600 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3601 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3602 | mcDELAY_US(1); |
| 3603 | u4TimeCnt = TIME_OUT_CNT; |
| 3604 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3605 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3606 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN_SWTRIG); |
| 3607 | do |
| 3608 | { |
| 3609 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE); |
| 3610 | u4TimeCnt --; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3611 | mcDELAY_US(1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3612 | |
| 3613 | mcSHOW_DBG_MSG4(("%d=\n\n", u4TimeCnt)); |
| 3614 | //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); |
| 3615 | }while((u4Response==0) &&(u4TimeCnt>0)); |
| 3616 | |
| 3617 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN_SWTRIG); |
| 3618 | |
| 3619 | if(u4TimeCnt==0)//time out |
| 3620 | { |
| 3621 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); |
| 3622 | mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n")); |
| 3623 | //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n")); |
| 3624 | return DRAM_FAIL; |
| 3625 | } |
| 3626 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3627 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3628 | mcDELAY_US(1); |
| 3629 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3630 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3631 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); |
| 3632 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4SWCMDCTRL); |
| 3633 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL); |
| 3634 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL); |
| 3635 | |
| 3636 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK); |
| 3637 | mcSHOW_DBG_MSG4(("[DramcZQCalibration] Done\n\n")); |
| 3638 | //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n")); |
| 3639 | |
| 3640 | return DRAM_OK; |
| 3641 | } |
| 3642 | #endif |
| 3643 | #if ZQ_RTSWCMD_MODE |
| 3644 | static DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank) |
| 3645 | { |
| 3646 | U32 u4Response; |
| 3647 | U32 u4TimeCnt = TIME_OUT_CNT; |
| 3648 | U32 u4SWCMDEN, u4SWCMDCTRL, u4MPCCTRL, u4RTSWCMD, u4SPDCTRL, u4CKECTRL; |
| 3649 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3650 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3651 | u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); |
| 3652 | u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2)); |
| 3653 | u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL)); |
| 3654 | u4RTSWCMD = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT)); |
| 3655 | u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); |
| 3656 | u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); |
| 3657 | |
| 3658 | mcSHOW_DBG_MSG4(("[ZQCalibration]\n")); |
| 3659 | //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); |
| 3660 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3661 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3662 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF); |
| 3663 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_TCKFIXON); |
| 3664 | mcDELAY_US(1); |
| 3665 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3666 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3667 | //CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 3668 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3669 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3670 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), |
| 3671 | P_Fld(rank, SWCMD_CTRL2_RTSWCMD_RK) | |
| 3672 | P_Fld(0x20, SWCMD_CTRL2_RTSWCMD_AGE)); |
| 3673 | |
| 3674 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0x1, MPC_CTRL_RTSWCMD_HPRI_EN); |
| 3675 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), 0x2a, RTSWCMD_CNT_RTSWCMD_CNT); |
| 3676 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3677 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3678 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x5, SWCMD_EN_RTSWCMD_SEL); |
| 3679 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); |
| 3680 | |
| 3681 | do |
| 3682 | { |
| 3683 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); |
| 3684 | u4TimeCnt --; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3685 | mcDELAY_US(1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3686 | |
| 3687 | mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt)); |
| 3688 | //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); |
| 3689 | }while((u4Response==0) &&(u4TimeCnt>0)); |
| 3690 | |
| 3691 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); |
| 3692 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3693 | if(u4TimeCnt==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3694 | { |
| 3695 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); |
| 3696 | mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n")); |
| 3697 | //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n")); |
| 3698 | return DRAM_FAIL; |
| 3699 | } |
| 3700 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3701 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3702 | mcDELAY_US(1); |
| 3703 | u4TimeCnt = TIME_OUT_CNT; |
| 3704 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3705 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3706 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x6, SWCMD_EN_RTSWCMD_SEL); |
| 3707 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_RTSWCMDEN); |
| 3708 | |
| 3709 | do |
| 3710 | { |
| 3711 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_RTSWCMD_RESPONSE); |
| 3712 | u4TimeCnt --; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3713 | mcDELAY_US(1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3714 | |
| 3715 | mcSHOW_DBG_MSG4(("%d=", u4TimeCnt)); |
| 3716 | //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); |
| 3717 | }while((u4Response==0) &&(u4TimeCnt>0)); |
| 3718 | |
| 3719 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN); |
| 3720 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3721 | if(u4TimeCnt==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3722 | { |
| 3723 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); |
| 3724 | mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n")); |
| 3725 | //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n")); |
| 3726 | return DRAM_FAIL; |
| 3727 | } |
| 3728 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3729 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3730 | mcDELAY_US(1); |
| 3731 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3732 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3733 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); |
| 3734 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL); |
| 3735 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL); |
| 3736 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT), u4RTSWCMD); |
| 3737 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL); |
| 3738 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL); |
| 3739 | |
| 3740 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK); |
| 3741 | mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n")); |
| 3742 | //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n")); |
| 3743 | |
| 3744 | return DRAM_OK; |
| 3745 | } |
| 3746 | #endif |
| 3747 | #if ZQ_SCSM_MODE |
| 3748 | static DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank) |
| 3749 | { |
| 3750 | U32 u4Response; |
| 3751 | U32 u4TimeCnt = TIME_OUT_CNT; |
| 3752 | U32 u4SWCMDEN, u4MPCCTRL, u4SWCMDCTRL, u4SPDCTRL, u4CKECTRL; |
| 3753 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3754 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3755 | u4SWCMDEN = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN)); |
| 3756 | u4SWCMDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0)); |
| 3757 | u4MPCCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION)); |
| 3758 | u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL)); |
| 3759 | u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)); |
| 3760 | |
| 3761 | mcSHOW_DBG_MSG4(("[ZQCalibration]\n")); |
| 3762 | //mcFPRINTF((fp_A60501, "[ZQCalibration]\n")); |
| 3763 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3764 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3765 | DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL); |
| 3766 | mcDELAY_US(1); |
| 3767 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3768 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3769 | CKEFixOnOff(p, rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 3770 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3771 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3772 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_MRSRK); |
| 3773 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN); |
| 3774 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3775 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3776 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQCEN); |
| 3777 | do |
| 3778 | { |
| 3779 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQC_RESPONSE); |
| 3780 | u4TimeCnt --; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3781 | mcDELAY_US(1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3782 | |
| 3783 | mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt)); |
| 3784 | //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt)); |
| 3785 | }while((u4Response==0) &&(u4TimeCnt>0)); |
| 3786 | |
| 3787 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN); |
| 3788 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3789 | if(u4TimeCnt==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3790 | { |
| 3791 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); |
| 3792 | mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n")); |
| 3793 | //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n")); |
| 3794 | return DRAM_FAIL; |
| 3795 | } |
| 3796 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3797 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3798 | mcDELAY_US(1); |
| 3799 | u4TimeCnt = TIME_OUT_CNT; |
| 3800 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3801 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3802 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_ZQLATEN); |
| 3803 | do |
| 3804 | { |
| 3805 | u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_ZQLAT_RESPONSE); |
| 3806 | u4TimeCnt --; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3807 | mcDELAY_US(1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3808 | |
| 3809 | mcSHOW_DBG_MSG4(("%d=", u4TimeCnt)); |
| 3810 | //mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt)); |
| 3811 | }while((u4Response==0) &&(u4TimeCnt>0)); |
| 3812 | |
| 3813 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN); |
| 3814 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3815 | if(u4TimeCnt==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3816 | { |
| 3817 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL); |
| 3818 | mcSHOW_ERR_MSG(("ZQCAL Latch fail (time out)\n")); |
| 3819 | //mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n")); |
| 3820 | return DRAM_FAIL; |
| 3821 | } |
| 3822 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3823 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3824 | mcDELAY_US(1); |
| 3825 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3826 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3827 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), u4SWCMDEN); |
| 3828 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2), u4SWCMDCTRL); |
| 3829 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), u4MPCCTRL); |
| 3830 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4SPDCTRL); |
| 3831 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL); |
| 3832 | |
| 3833 | vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK); |
| 3834 | mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n")); |
| 3835 | //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n")); |
| 3836 | |
| 3837 | return DRAM_OK; |
| 3838 | } |
| 3839 | #endif |
| 3840 | |
| 3841 | DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank) |
| 3842 | { |
| 3843 | #if ZQ_SWCMD_MODE |
| 3844 | return ZQ_SWCMD_MODE_Cal(p, rank); |
| 3845 | #elif ZQ_RTSWCMD_MODE |
| 3846 | return ZQ_RTSWCMD_MODE_Cal(p, rank); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3847 | #else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3848 | return ZQ_SCSM_MODE_Cal(p, rank); |
| 3849 | #endif |
| 3850 | } |
| 3851 | #endif |
| 3852 | |
| 3853 | #if ENABLE_RX_INPUT_BUFF_OFF_K |
| 3854 | static U8 RXInputBuf_DelayExchange(S8 iOfst) |
| 3855 | { |
| 3856 | U8 u1Value; |
| 3857 | |
| 3858 | if(iOfst <0) |
| 3859 | { |
| 3860 | u1Value = 0x8 | (-iOfst); |
| 3861 | } |
| 3862 | else |
| 3863 | { |
| 3864 | u1Value = iOfst; |
| 3865 | } |
| 3866 | |
| 3867 | return u1Value; |
| 3868 | } |
| 3869 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3870 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3871 | DRAM_STATUS_T DramcRXInputBufferOffsetCal(DRAMC_CTX_T *p) |
| 3872 | { |
| 3873 | S8 iOffset, s1begin, s1end; |
| 3874 | S8 s1DQFinalFlagChange[DQ_DATA_WIDTH], s1DQMFinalFlagChange[DQM_BYTE_NUM]; |
| 3875 | U8 u1BitIdx, u1ByteIdx, u1FinishCount, u1step, u1DQFinal_rg_offset[DQ_DATA_WIDTH], u1DQMFinal_rg_offset[DQM_BYTE_NUM]; |
| 3876 | //U8 *uiLPDDR_O1_Mapping = NULL; |
| 3877 | U8 ii, read_val_b0 = u1GetRank(p); //u1rank_backup |
| 3878 | U8 u1Offc_RgValue, u1O1_value; |
| 3879 | U32 u4RestltDQ, u4RestltDQ_B0, u4RestltDQ_B1, u4RestltDQM[DQM_BYTE_NUM]; |
| 3880 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
| 3881 | U32 u4RegBackupAddress[] = |
| 3882 | { |
| 3883 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)), |
| 3884 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)), |
| 3885 | (DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5)), |
| 3886 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)), |
| 3887 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)), |
| 3888 | (DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6)), |
| 3889 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)), |
| 3890 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)), |
| 3891 | (DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3)), |
| 3892 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3)), |
| 3893 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3)), |
| 3894 | (DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3)), |
| 3895 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL)), |
| 3896 | }; |
| 3897 | |
| 3898 | vSetCalibrationResult(p, DRAM_CALIBRATION_RX_INPUT_BUFF_OFFC, DRAM_FAIL); |
| 3899 | mcSHOW_DBG_MSG2(("\n[DramcRXInputBufferOffsetCal] \n")); |
| 3900 | #if VENDER_JV_LOG |
| 3901 | vPrintCalibrationBasicInfo_ForJV(p); |
| 3902 | #else |
| 3903 | vPrintCalibrationBasicInfo(p); |
| 3904 | #endif |
| 3905 | |
| 3906 | DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); |
| 3907 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3908 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3909 | DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN); |
| 3910 | |
| 3911 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), 0xf, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); |
| 3912 | |
| 3913 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), |
| 3914 | P_Fld(1, B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0) | |
| 3915 | P_Fld(1, B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0) | |
| 3916 | P_Fld(0, B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0) | |
| 3917 | P_Fld(1, B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0)); |
| 3918 | if (!isLP4_DSC) |
| 3919 | { |
| 3920 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), |
| 3921 | P_Fld(1, B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1) | |
| 3922 | P_Fld(1, B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1) | |
| 3923 | P_Fld(0, B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1) | |
| 3924 | P_Fld(1, B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1)); |
| 3925 | } |
| 3926 | else |
| 3927 | { |
| 3928 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), |
| 3929 | P_Fld(1, CA_CMD6_RG_RX_ARCMD_BIAS_PS) | |
| 3930 | P_Fld(1, CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN) | |
| 3931 | P_Fld(0, CA_CMD6_RG_TX_ARCMD_DDR3_SEL) | |
| 3932 | P_Fld(1, CA_CMD6_RG_TX_ARCMD_DDR4_SEL)); |
| 3933 | } |
| 3934 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3935 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3936 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); |
| 3937 | if (!isLP4_DSC) |
| 3938 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); |
| 3939 | else |
| 3940 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), 1, CA_CMD5_RG_RX_ARCMD_VREF_EN); |
| 3941 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3942 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3943 | mcDELAY_US(1); |
| 3944 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3945 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3946 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), P_Fld(1, B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0) | P_Fld(1, B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0)); |
| 3947 | if (!isLP4_DSC) |
| 3948 | { |
| 3949 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), P_Fld(1, B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1) | P_Fld(1, B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1)); |
| 3950 | } |
| 3951 | else |
| 3952 | { |
| 3953 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD3), P_Fld(1, CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN) | P_Fld(1, CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN)); |
| 3954 | } |
| 3955 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3956 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3957 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY3), 1, B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0); |
| 3958 | if (!isLP4_DSC) |
| 3959 | { |
| 3960 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY3), 1, B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1); |
| 3961 | } |
| 3962 | else |
| 3963 | { |
| 3964 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_PHY3), 1, CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA); |
| 3965 | } |
| 3966 | |
| 3967 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), |
| 3968 | P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | |
| 3969 | P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0)); |
| 3970 | if (!isLP4_DSC) |
| 3971 | { |
| 3972 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), |
| 3973 | P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | |
| 3974 | P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1)); |
| 3975 | } |
| 3976 | else |
| 3977 | { |
| 3978 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), |
| 3979 | P_Fld(0x1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) | |
| 3980 | P_Fld(0x1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA)); |
| 3981 | } |
| 3982 | |
| 3983 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_O1_SEL_B0); |
| 3984 | if (!isLP4_DSC) |
| 3985 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), 1, B1_DQ6_RG_RX_ARDQ_O1_SEL_B1); |
| 3986 | else |
| 3987 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD6), 1, CA_CMD6_RG_RX_ARCMD_O1_SEL); |
| 3988 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3989 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3990 | u1FinishCount =0; |
| 3991 | s1begin = -7; |
| 3992 | s1end = 8; |
| 3993 | u1step = 1; |
| 3994 | |
| 3995 | memset(s1DQFinalFlagChange, 0x7f, sizeof(s1DQFinalFlagChange)); |
| 3996 | memset(s1DQMFinalFlagChange, 0x7f, sizeof(s1DQMFinalFlagChange)); |
| 3997 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 3998 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 3999 | for(iOffset = s1begin; iOffset < s1end; iOffset+=u1step) |
| 4000 | { |
| 4001 | u1Offc_RgValue = RXInputBuf_DelayExchange(iOffset); |
| 4002 | |
| 4003 | mcSHOW_DBG_MSG2(("iOffset= %2d, set %2d,", iOffset, u1Offc_RgValue)); |
| 4004 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4005 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4006 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ0), |
| 4007 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0) | |
| 4008 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0) | |
| 4009 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ2_OFFC_B0) | |
| 4010 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ3_OFFC_B0) | |
| 4011 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ4_OFFC_B0) | |
| 4012 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ5_OFFC_B0) | |
| 4013 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ6_OFFC_B0) | |
| 4014 | P_Fld(u1Offc_RgValue, SHU_RK_B0_DQ0_RG_RX_ARDQ7_OFFC_B0)); |
| 4015 | if (!isLP4_DSC) |
| 4016 | { |
| 4017 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ0), |
| 4018 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ0_OFFC_B1) | |
| 4019 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ1_OFFC_B1) | |
| 4020 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ2_OFFC_B1) | |
| 4021 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ3_OFFC_B1) | |
| 4022 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ4_OFFC_B1) | |
| 4023 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ5_OFFC_B1) | |
| 4024 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ6_OFFC_B1) | |
| 4025 | P_Fld(u1Offc_RgValue, SHU_RK_B1_DQ0_RG_RX_ARDQ7_OFFC_B1)); |
| 4026 | } |
| 4027 | else |
| 4028 | { |
| 4029 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD0), |
| 4030 | P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA0_OFFC) | |
| 4031 | P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA1_OFFC) | |
| 4032 | P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA2_OFFC) | |
| 4033 | P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA3_OFFC) | |
| 4034 | P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA4_OFFC) | |
| 4035 | P_Fld(u1Offc_RgValue, SHU_RK_CA_CMD0_RG_RX_ARCA5_OFFC)); |
| 4036 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_DQ_OFFSET), |
| 4037 | P_Fld(u1Offc_RgValue, SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ6_OFFSETC_C0) | |
| 4038 | P_Fld(u1Offc_RgValue, SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ7_OFFSETC_C0)); |
| 4039 | } |
| 4040 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4041 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4042 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ1), u1Offc_RgValue, SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0); |
| 4043 | if (!isLP4_DSC) |
| 4044 | { |
| 4045 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ1), u1Offc_RgValue, SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1); |
| 4046 | } |
| 4047 | else |
| 4048 | { |
| 4049 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD1), u1Offc_RgValue, SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC); |
| 4050 | } |
| 4051 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4052 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4053 | mcDELAY_US(1); |
| 4054 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4055 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4056 | u4RestltDQ_B0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0); |
| 4057 | if (!isLP4_DSC) |
| 4058 | { |
| 4059 | u4RestltDQ_B1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1); |
| 4060 | } |
| 4061 | else |
| 4062 | { |
| 4063 | u4RestltDQ_B1 = ((u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_CMD_O1)))&0x3f)\ |
| 4064 | |(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ6_O1_C0)<<0x6)\ |
| 4065 | |(u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQ7_O1_C0)<<0x7); |
| 4066 | } |
| 4067 | u4RestltDQ = u4RestltDQ_B0|(u4RestltDQ_B1<<8); |
| 4068 | mcSHOW_DBG_MSG2((" DQ O1 = 0x%x, ", u4RestltDQ)); |
| 4069 | |
| 4070 | for(u1BitIdx= 0; u1BitIdx < DQ_DATA_WIDTH ; u1BitIdx++) |
| 4071 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4072 | if(s1DQFinalFlagChange[u1BitIdx] == 0x7f) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4073 | { |
| 4074 | u1O1_value = (u4RestltDQ >> u1BitIdx) & 0x1; |
| 4075 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4076 | if(u1O1_value ==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4077 | { |
| 4078 | s1DQFinalFlagChange[u1BitIdx] = iOffset; |
| 4079 | u1FinishCount ++; |
| 4080 | #if __ETT__ |
| 4081 | if(iOffset == s1begin) |
| 4082 | { |
| 4083 | mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n")); |
| 4084 | } |
| 4085 | #endif |
| 4086 | } |
| 4087 | else if(iOffset >= (s1end - u1step)) |
| 4088 | { |
| 4089 | s1DQFinalFlagChange[u1BitIdx] = iOffset; |
| 4090 | u1FinishCount ++; |
| 4091 | |
| 4092 | mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n")); |
| 4093 | } |
| 4094 | } |
| 4095 | } |
| 4096 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4097 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4098 | u4RestltDQM[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0); |
| 4099 | if (!isLP4_DSC) |
| 4100 | { |
| 4101 | u4RestltDQM[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_DQ_O1), MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1); |
| 4102 | } |
| 4103 | else |
| 4104 | { |
| 4105 | u4RestltDQM[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_AD_RX_CMD_O1), MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1); |
| 4106 | } |
| 4107 | |
| 4108 | mcSHOW_DBG_MSG2(("DQM O1 (B1)= 0x%2x, (B0)= 0x%2x\n", u4RestltDQM[1], u4RestltDQM[0])); |
| 4109 | |
| 4110 | for(u1ByteIdx= 0; u1ByteIdx < DQM_BYTE_NUM; u1ByteIdx++) |
| 4111 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4112 | if(s1DQMFinalFlagChange[u1ByteIdx]== 0x7f) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4113 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4114 | if(u4RestltDQM[u1ByteIdx]==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4115 | { |
| 4116 | s1DQMFinalFlagChange[u1ByteIdx]= iOffset; |
| 4117 | u1FinishCount++; |
| 4118 | #if __ETT__ |
| 4119 | if(iOffset == s1begin) |
| 4120 | { |
| 4121 | mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n")); |
| 4122 | } |
| 4123 | #endif |
| 4124 | } |
| 4125 | else if(iOffset == (s1end - u1step)) |
| 4126 | { |
| 4127 | s1DQMFinalFlagChange[u1ByteIdx] = iOffset; |
| 4128 | u1FinishCount ++; |
| 4129 | |
| 4130 | mcSHOW_ERR_MSG(("Error! didn't find trainsition point\n")); |
| 4131 | } |
| 4132 | } |
| 4133 | } |
| 4134 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4135 | if(u1FinishCount==(DQM_BYTE_NUM+DQ_DATA_WIDTH)) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4136 | { |
| 4137 | vSetCalibrationResult(p, DRAM_CALIBRATION_RX_INPUT_BUFF_OFFC, DRAM_OK); |
| 4138 | mcSHOW_DBG_MSG2(("All bits find pass window, early break!\n")); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4139 | break; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4140 | } |
| 4141 | } |
| 4142 | |
| 4143 | mcSHOW_DBG_MSG2(("O1 Result DQ : [00]%3d [01]%3d [02]%3d [03]%3d [04]%3d [05]%3d [06]%3d [07]%3d\n", |
| 4144 | s1DQFinalFlagChange[0], s1DQFinalFlagChange[1], s1DQFinalFlagChange[2], s1DQFinalFlagChange[3], |
| 4145 | s1DQFinalFlagChange[4], s1DQFinalFlagChange[5], s1DQFinalFlagChange[6], s1DQFinalFlagChange[7])); |
| 4146 | mcSHOW_DBG_MSG2(("O1 Result DQ : [08]%3d [09]%3d [10]%3d [11]%3d [12]%3d [13]%3d [14]%3d [15]%3d\n", |
| 4147 | s1DQFinalFlagChange[8], s1DQFinalFlagChange[9], s1DQFinalFlagChange[10], s1DQFinalFlagChange[11], |
| 4148 | s1DQFinalFlagChange[12], s1DQFinalFlagChange[13], s1DQFinalFlagChange[14],s1DQFinalFlagChange[15])); |
| 4149 | mcSHOW_DBG_MSG2(("O1 Result DQM0 %2d Result DQM1 %2d,\n", s1DQMFinalFlagChange[0], s1DQMFinalFlagChange[1])); |
| 4150 | |
| 4151 | for(u1BitIdx= 0; u1BitIdx <DQ_DATA_WIDTH; u1BitIdx++) |
| 4152 | { |
| 4153 | u1DQFinal_rg_offset[u1BitIdx] = RXInputBuf_DelayExchange(s1DQFinalFlagChange[u1BitIdx]); |
| 4154 | #ifdef FOR_HQA_REPORT_USED |
| 4155 | if (gHQALog_flag == 1) |
| 4156 | { |
| 4157 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0_1, "RX_Input_Offset", " ", u1BitIdx, s1DQFinalFlagChange[u1BitIdx], NULL); |
| 4158 | } |
| 4159 | #endif |
| 4160 | } |
| 4161 | u1DQMFinal_rg_offset[0]= RXInputBuf_DelayExchange(s1DQMFinalFlagChange[0]); |
| 4162 | u1DQMFinal_rg_offset[1]= RXInputBuf_DelayExchange(s1DQMFinalFlagChange[1]); |
| 4163 | #ifdef FOR_HQA_REPORT_USED |
| 4164 | if (gHQALog_flag == 1) |
| 4165 | { |
| 4166 | HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Input_Offset Channel%d Rank%d DQM0 %d\n", p->channel, p->rank, s1DQMFinalFlagChange[0])); |
| 4167 | HQA_LOG_Print_Prefix_String(p); mcSHOW_DBG_MSG(("RX_Input_Offset Channel%d Rank%d DQM1 %d\n", p->channel, p->rank, s1DQMFinalFlagChange[1])); |
| 4168 | } |
| 4169 | #endif |
| 4170 | |
| 4171 | for (ii = RANK_0; ii < p->support_rank_num; ii++) |
| 4172 | { |
| 4173 | vSetRank(p, ii); |
| 4174 | |
| 4175 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ0), |
| 4176 | P_Fld(u1DQFinal_rg_offset[0], SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0) | |
| 4177 | P_Fld(u1DQFinal_rg_offset[1], SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0) | |
| 4178 | P_Fld(u1DQFinal_rg_offset[2], SHU_RK_B0_DQ0_RG_RX_ARDQ2_OFFC_B0) | |
| 4179 | P_Fld(u1DQFinal_rg_offset[3], SHU_RK_B0_DQ0_RG_RX_ARDQ3_OFFC_B0) | |
| 4180 | P_Fld(u1DQFinal_rg_offset[4], SHU_RK_B0_DQ0_RG_RX_ARDQ4_OFFC_B0) | |
| 4181 | P_Fld(u1DQFinal_rg_offset[5], SHU_RK_B0_DQ0_RG_RX_ARDQ5_OFFC_B0) | |
| 4182 | P_Fld(u1DQFinal_rg_offset[6], SHU_RK_B0_DQ0_RG_RX_ARDQ6_OFFC_B0) | |
| 4183 | P_Fld(u1DQFinal_rg_offset[7], SHU_RK_B0_DQ0_RG_RX_ARDQ7_OFFC_B0)); |
| 4184 | if (!isLP4_DSC) |
| 4185 | { |
| 4186 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ0), |
| 4187 | P_Fld(u1DQFinal_rg_offset[8], SHU_RK_B1_DQ0_RG_RX_ARDQ0_OFFC_B1) | |
| 4188 | P_Fld(u1DQFinal_rg_offset[9], SHU_RK_B1_DQ0_RG_RX_ARDQ1_OFFC_B1) | |
| 4189 | P_Fld(u1DQFinal_rg_offset[10], SHU_RK_B1_DQ0_RG_RX_ARDQ2_OFFC_B1) | |
| 4190 | P_Fld(u1DQFinal_rg_offset[11], SHU_RK_B1_DQ0_RG_RX_ARDQ3_OFFC_B1) | |
| 4191 | P_Fld(u1DQFinal_rg_offset[12], SHU_RK_B1_DQ0_RG_RX_ARDQ4_OFFC_B1) | |
| 4192 | P_Fld(u1DQFinal_rg_offset[13], SHU_RK_B1_DQ0_RG_RX_ARDQ5_OFFC_B1) | |
| 4193 | P_Fld(u1DQFinal_rg_offset[14], SHU_RK_B1_DQ0_RG_RX_ARDQ6_OFFC_B1) | |
| 4194 | P_Fld(u1DQFinal_rg_offset[15], SHU_RK_B1_DQ0_RG_RX_ARDQ7_OFFC_B1)); |
| 4195 | } |
| 4196 | else |
| 4197 | { |
| 4198 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD0), |
| 4199 | P_Fld(u1DQFinal_rg_offset[8], SHU_RK_CA_CMD0_RG_RX_ARCA0_OFFC) | |
| 4200 | P_Fld(u1DQFinal_rg_offset[9], SHU_RK_CA_CMD0_RG_RX_ARCA1_OFFC) | |
| 4201 | P_Fld(u1DQFinal_rg_offset[10], SHU_RK_CA_CMD0_RG_RX_ARCA2_OFFC) | |
| 4202 | P_Fld(u1DQFinal_rg_offset[11], SHU_RK_CA_CMD0_RG_RX_ARCA3_OFFC) | |
| 4203 | P_Fld(u1DQFinal_rg_offset[12], SHU_RK_CA_CMD0_RG_RX_ARCA4_OFFC) | |
| 4204 | P_Fld(u1DQFinal_rg_offset[13], SHU_RK_CA_CMD0_RG_RX_ARCA5_OFFC)); |
| 4205 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_DQ_OFFSET), |
| 4206 | P_Fld(u1DQFinal_rg_offset[14], SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ6_OFFSETC_C0) | |
| 4207 | P_Fld(u1DQFinal_rg_offset[15], SHU_RK_CA_DQ_OFFSET_RG_RX_ARDQ7_OFFSETC_C0)); |
| 4208 | } |
| 4209 | |
| 4210 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQ1), u1DQMFinal_rg_offset[0], SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0); |
| 4211 | if (!isLP4_DSC) |
| 4212 | { |
| 4213 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQ1), u1DQMFinal_rg_offset[1], SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1); |
| 4214 | } |
| 4215 | else |
| 4216 | { |
| 4217 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_CA_CMD1), u1DQMFinal_rg_offset[1], SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC); |
| 4218 | } |
| 4219 | } |
| 4220 | vSetRank(p, read_val_b0); |
| 4221 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4222 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4223 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), 0x0, MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN); |
| 4224 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0); |
| 4225 | //vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1); |
| 4226 | |
| 4227 | DramcRestoreRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); |
| 4228 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4229 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4230 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), |
| 4231 | P_Fld(0x1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0) | |
| 4232 | P_Fld(0x0, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0)); |
| 4233 | if (!isLP4_DSC) |
| 4234 | { |
| 4235 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), |
| 4236 | P_Fld(0x1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1) | |
| 4237 | P_Fld(0x0, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1)); |
| 4238 | } |
| 4239 | else |
| 4240 | { |
| 4241 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), |
| 4242 | P_Fld(0x1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA) | |
| 4243 | P_Fld(0x0, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA)); |
| 4244 | } |
| 4245 | |
| 4246 | mcSHOW_DBG_MSG2(("[DramcRXInputBufferOffsetCal] ====Done====\n")); |
| 4247 | |
| 4248 | return DRAM_OK; |
| 4249 | } |
| 4250 | #endif |
| 4251 | |
| 4252 | #if (SIMULATION_GATING == 1) |
| 4253 | #define GATING_PATTERN_NUM_LP5 0x23 |
| 4254 | #define GATING_GOLDEND_DQSCNT_LP5 0x4646 |
| 4255 | #define RXDQS_GATING_AUTO_DBG_REG_NUM 6 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4256 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4257 | |
| 4258 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 4259 | U8 u1TXDLY_Cal_min =0xff, u1TXDLY_Cal_max=0; |
| 4260 | U8 ucbest_coarse_mck_backup[RANK_MAX][DQS_BYTE_NUMBER]; |
| 4261 | U8 ucbest_coarse_ui_backup[RANK_MAX][DQS_BYTE_NUMBER]; |
| 4262 | U8 ucbest_coarse_mck_P1_backup[RANK_MAX][DQS_BYTE_NUMBER]; |
| 4263 | U8 ucbest_coarse_ui_P1_backup[RANK_MAX][DQS_BYTE_NUMBER]; |
| 4264 | #endif |
| 4265 | |
| 4266 | |
| 4267 | struct rxdqs_gating_cal { |
| 4268 | U8 dqsien_dly_mck; |
| 4269 | U8 dqsien_dly_ui; |
| 4270 | U8 dqsien_dly_pi; |
| 4271 | |
| 4272 | U8 dqsien_dly_mck_p1; |
| 4273 | U8 dqsien_dly_ui_p1; |
| 4274 | |
| 4275 | U8 dqsien_pi_adj_step; |
| 4276 | |
| 4277 | U8 dqsien_pi_per_ui; |
| 4278 | U8 dqsien_ui_per_mck; |
| 4279 | U8 dqsien_freq_div; |
| 4280 | }; |
| 4281 | |
| 4282 | struct rxdqs_gating_trans { |
| 4283 | U8 dqs_lead[DQS_BYTE_NUMBER]; |
| 4284 | U8 dqs_lag[DQS_BYTE_NUMBER]; |
| 4285 | U8 dqs_high[DQS_BYTE_NUMBER]; |
| 4286 | #if GATING_LEADLAG_LOW_LEVEL_CHECK |
| 4287 | U8 dqs_low[DQS_BYTE_NUMBER]; |
| 4288 | #endif |
| 4289 | U8 dqs_transition[DQS_BYTE_NUMBER]; |
| 4290 | U8 dqs_transitioned[DQS_BYTE_NUMBER]; |
| 4291 | U8 dqsien_dly_mck_leadlag[DQS_BYTE_NUMBER]; |
| 4292 | U8 dqsien_dly_ui_leadlag[DQS_BYTE_NUMBER]; |
| 4293 | U8 dqsien_dly_pi_leadlag[DQS_BYTE_NUMBER]; |
| 4294 | }; |
| 4295 | |
| 4296 | struct rxdqs_gating_best_win { |
| 4297 | U8 best_dqsien_dly_mck[DQS_BYTE_NUMBER]; |
| 4298 | U8 best_dqsien_dly_ui[DQS_BYTE_NUMBER]; |
| 4299 | U8 best_dqsien_dly_pi[DQS_BYTE_NUMBER]; |
| 4300 | U8 best_dqsien_dly_mck_p1[DQS_BYTE_NUMBER]; |
| 4301 | U8 best_dqsien_dly_ui_p1[DQS_BYTE_NUMBER]; |
| 4302 | U8 best_dqsien_dly_pi_p1[DQS_BYTE_NUMBER]; |
| 4303 | }; |
| 4304 | |
| 4305 | struct rxdqs_gating_auto_param { |
| 4306 | U8 early_break; |
| 4307 | U8 dbg_mode; |
| 4308 | |
| 4309 | U8 init_mck; |
| 4310 | U8 init_ui; |
| 4311 | U8 end_mck; |
| 4312 | U8 end_ui; |
| 4313 | U8 pi_offset; |
| 4314 | |
| 4315 | U8 burst_len; |
| 4316 | }; |
| 4317 | |
| 4318 | #if ENABLE_GATING_AUTOK_WA |
| 4319 | U8 __wa__gating_swk_for_autok = 0; |
| 4320 | U8 __wa__gating_autok_init_ui[RANK_MAX] = { 0 }; |
| 4321 | #endif |
| 4322 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4323 | static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK) |
| 4324 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4325 | const U8 au1MR2MappingToRL[2][8] = {{6, 10, 14, 20, 24, 28, 32, 36}, |
| 4326 | {6, 10, 16, 22, 26, 32, 36, 40}}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4327 | //U8 u1CK2WCK, u1DVFSCEn; |
| 4328 | U8 u1MR0_LatencyMode; |
| 4329 | U8 u1MR2RLValue; |
| 4330 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4331 | u1MR2RLValue = u1MR02Value[p->dram_fsp] & 0x7; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4332 | U8 u1RX_Path_delay_UI, u1RealRL,u1StartUI, u1ExtraMCKfor1_4mode; |
| 4333 | U8 u1MCK2CK_UI, u1ReadDQSINCTL, u1DQSINCTL_UI; |
| 4334 | U8 u4TDQSCK_UI_min; |
| 4335 | U8 u1GatingAheadDQS_UI; |
| 4336 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4337 | |
| 4338 | if(gu2MR0_Value[p->rank] == 0xffff) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4339 | { |
| 4340 | u1MR0_LatencyMode = CBT_NORMAL_MODE; |
| 4341 | } |
| 4342 | else |
| 4343 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4344 | u1MR0_LatencyMode = (gu2MR0_Value[p->rank]>>1) & 0x1; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4345 | } |
| 4346 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4347 | { |
| 4348 | u4TDQSCK_UI_min = 1500 * DDRPhyGetRealFreq(p) *2/ 1000000; |
| 4349 | u1RealRL = au1MR2MappingToRL[u1MR0_LatencyMode][u1MR2RLValue]; |
| 4350 | } |
| 4351 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4352 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4353 | if(vGet_Div_Mode(p) == DIV4_MODE) |
| 4354 | { |
| 4355 | u1MCK2CK_UI = 4; |
| 4356 | u1ExtraMCKfor1_4mode = 1; |
| 4357 | u1GatingAheadDQS_UI = 3; |
| 4358 | } |
| 4359 | else if (vGet_Div_Mode(p) == DIV8_MODE) |
| 4360 | { |
| 4361 | u1MCK2CK_UI = 8; |
| 4362 | u1ExtraMCKfor1_4mode = 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4363 | u1GatingAheadDQS_UI = 5; |
| 4364 | } |
| 4365 | else |
| 4366 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4367 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4368 | u1MCK2CK_UI = 16; |
| 4369 | u1ExtraMCKfor1_4mode = 0; |
| 4370 | u1GatingAheadDQS_UI = 8; |
| 4371 | } |
| 4372 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4373 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4374 | u1RX_Path_delay_UI = (u1RealRL<<1) + u4TDQSCK_UI_min - u1GatingAheadDQS_UI + (u1MCK2CK_UI*u1ExtraMCKfor1_4mode); |
| 4375 | |
| 4376 | u1ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), MISC_SHU_RK_DQSCTL_DQSINCTL); |
| 4377 | u1DQSINCTL_UI = u1ReadDQSINCTL * u1MCK2CK_UI; |
| 4378 | |
| 4379 | if(u1AutoK) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4380 | u1RX_Path_delay_UI += 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4381 | else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4382 | u1RX_Path_delay_UI -= 3; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4383 | |
| 4384 | if(u1RX_Path_delay_UI >= u1DQSINCTL_UI) |
| 4385 | u1StartUI = u1RX_Path_delay_UI - u1DQSINCTL_UI; |
| 4386 | else |
| 4387 | { |
| 4388 | u1StartUI =0; |
| 4389 | mcSHOW_ERR_MSG(("GatingStartPos err! Need to fine-tune default DQSINCTL value.\n(RX_Path_delay_UI %d) < DQSINCTL_UI %d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI)); |
| 4390 | #if __ETT__ |
| 4391 | while(1); |
| 4392 | #endif |
| 4393 | } |
| 4394 | |
| 4395 | mcSHOW_DBG_MSG2(("[DUMPLOG] %d GatingStartPos_MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", p->frequency * 2, u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode)); |
| 4396 | |
| 4397 | if(u1AutoK) |
| 4398 | { |
| 4399 | mcSHOW_DBG_MSG2(("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI)); |
| 4400 | } |
| 4401 | else |
| 4402 | { |
| 4403 | mcSHOW_DBG_MSG2(("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI)); |
| 4404 | } |
| 4405 | |
| 4406 | return u1StartUI; |
| 4407 | } |
| 4408 | |
| 4409 | #if GATING_RODT_LATANCY_EN |
| 4410 | static U8 get_rodt_mck2ui(DRAMC_CTX_T *p) |
| 4411 | { |
| 4412 | if (vGet_Div_Mode(p) == DIV16_MODE) |
| 4413 | return 8; |
| 4414 | else if (vGet_Div_Mode(p) == DIV8_MODE) |
| 4415 | return 4; |
| 4416 | else |
| 4417 | return 2; |
| 4418 | } |
| 4419 | #endif |
| 4420 | |
| 4421 | static u8 rxdqs_gating_bypass(DRAMC_CTX_T *p) |
| 4422 | { |
| 4423 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_GatingCal |
| 4424 | if (p->femmc_Ready == 1) { |
| 4425 | mcSHOW_DBG_MSG(("[FAST_K] Bypass Gating Calibration\n")); |
| 4426 | return 1; |
| 4427 | } |
| 4428 | #endif |
| 4429 | |
| 4430 | return 0; |
| 4431 | } |
| 4432 | |
| 4433 | static void rxdqs_gating_fastk_save_restore(DRAMC_CTX_T *p, |
| 4434 | struct rxdqs_gating_best_win *best_win, |
| 4435 | struct rxdqs_gating_cal *gating_cal) |
| 4436 | { |
| 4437 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 4438 | u8 ui_per_mck = gating_cal->dqsien_ui_per_mck; |
| 4439 | u8 freq_div = gating_cal->dqsien_freq_div; |
| 4440 | u8 ch = p->channel; |
| 4441 | u8 rk = p->rank; |
| 4442 | u8 dqs_i; |
| 4443 | |
| 4444 | if (p->femmc_Ready == 1) { |
| 4445 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { |
| 4446 | best_win->best_dqsien_dly_mck[dqs_i] = |
| 4447 | p->pSavetimeData->u1Gating_MCK_Save[ch][rk][dqs_i]; |
| 4448 | best_win->best_dqsien_dly_ui[dqs_i] = |
| 4449 | p->pSavetimeData->u1Gating_UI_Save[ch][rk][dqs_i]; |
| 4450 | best_win->best_dqsien_dly_pi[dqs_i] = |
| 4451 | p->pSavetimeData->u1Gating_PI_Save[ch][rk][dqs_i]; |
| 4452 | |
| 4453 | /* Calculate P1 */ |
| 4454 | best_win->best_dqsien_dly_ui_p1[dqs_i] = |
| 4455 | best_win->best_dqsien_dly_mck[dqs_i] * ui_per_mck + |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4456 | best_win->best_dqsien_dly_ui[dqs_i] + freq_div; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4457 | best_win->best_dqsien_dly_mck_p1[dqs_i] = |
| 4458 | best_win->best_dqsien_dly_ui_p1[dqs_i] / ui_per_mck; |
| 4459 | best_win->best_dqsien_dly_ui_p1[dqs_i] = |
| 4460 | best_win->best_dqsien_dly_ui_p1[dqs_i] % ui_per_mck; |
| 4461 | |
| 4462 | vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAST_K); |
| 4463 | |
| 4464 | mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", |
| 4465 | ch, rk, dqs_i, best_win->best_dqsien_dly_mck[dqs_i], |
| 4466 | best_win->best_dqsien_dly_ui[dqs_i], |
| 4467 | best_win->best_dqsien_dly_pi[dqs_i])); |
| 4468 | mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", |
| 4469 | ch, rk, dqs_i, best_win->best_dqsien_dly_mck_p1[dqs_i], |
| 4470 | best_win->best_dqsien_dly_ui_p1[dqs_i], |
| 4471 | best_win->best_dqsien_dly_pi_p1[dqs_i])); |
| 4472 | |
| 4473 | } |
| 4474 | } |
| 4475 | #endif |
| 4476 | } |
| 4477 | |
| 4478 | static void rxdqs_gating_misc_process(DRAMC_CTX_T *p, |
| 4479 | struct rxdqs_gating_best_win *rxdqs_best_win) |
| 4480 | { |
| 4481 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 4482 | U8 u1TX_dly_DQSgated = 0; |
| 4483 | #endif |
| 4484 | U8 dqs_i; |
| 4485 | |
| 4486 | for (dqs_i=0; dqs_i<DQS_BYTE_NUMBER; dqs_i++) { |
| 4487 | #ifdef FOR_HQA_REPORT_USED |
| 4488 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT6, "DQSINCTL ", "", 0, |
| 4489 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), MISC_SHU_RK_DQSCTL_DQSINCTL), NULL); |
| 4490 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, |
| 4491 | "Gating_Center_", "2T", dqs_i, rxdqs_best_win->best_dqsien_dly_mck[dqs_i], NULL); |
| 4492 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, |
| 4493 | "Gating_Center_", "05T", dqs_i, rxdqs_best_win->best_dqsien_dly_ui[dqs_i], NULL); |
| 4494 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, |
| 4495 | "Gating_Center_", "PI", dqs_i, rxdqs_best_win->best_dqsien_dly_pi[dqs_i], NULL); |
| 4496 | #endif |
| 4497 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4498 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4499 | mcSHOW_DBG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, |
| 4500 | rxdqs_best_win->best_dqsien_dly_mck[dqs_i], |
| 4501 | rxdqs_best_win->best_dqsien_dly_ui[dqs_i], |
| 4502 | rxdqs_best_win->best_dqsien_dly_pi[dqs_i])); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4503 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4504 | |
| 4505 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 4506 | u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck[dqs_i] << 4) + |
| 4507 | rxdqs_best_win->best_dqsien_dly_ui[dqs_i]; |
| 4508 | |
| 4509 | if (vGet_Div_Mode(p) == DIV16_MODE) |
| 4510 | u1TX_dly_DQSgated >>= 4; |
| 4511 | else if (vGet_Div_Mode(p) == DIV8_MODE) |
| 4512 | u1TX_dly_DQSgated >>= 3; |
| 4513 | else |
| 4514 | u1TX_dly_DQSgated >>= 2; |
| 4515 | |
| 4516 | if (u1TX_dly_DQSgated < u1TXDLY_Cal_min) |
| 4517 | u1TXDLY_Cal_min = u1TX_dly_DQSgated; |
| 4518 | |
| 4519 | ucbest_coarse_ui_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_ui[dqs_i]; |
| 4520 | ucbest_coarse_mck_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_mck[dqs_i]; |
| 4521 | #endif |
| 4522 | } |
| 4523 | |
| 4524 | mcSHOW_DBG_MSG(("\n")); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4525 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4526 | |
| 4527 | for (dqs_i=0; dqs_i<DQS_BYTE_NUMBER; dqs_i++) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4528 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4529 | mcSHOW_DBG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i, |
| 4530 | rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i], |
| 4531 | rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i], |
| 4532 | rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i])); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4533 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4534 | |
| 4535 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4536 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4537 | u1TX_dly_DQSgated = (rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i] << 4) + |
| 4538 | rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i]; |
| 4539 | |
| 4540 | if (vGet_Div_Mode(p) == DIV16_MODE) |
| 4541 | u1TX_dly_DQSgated >>= 4; |
| 4542 | else if (vGet_Div_Mode(p) == DIV8_MODE) |
| 4543 | u1TX_dly_DQSgated >>= 3; |
| 4544 | else |
| 4545 | u1TX_dly_DQSgated >>= 2; |
| 4546 | |
| 4547 | if(u1TX_dly_DQSgated > u1TXDLY_Cal_max) |
| 4548 | u1TXDLY_Cal_max = u1TX_dly_DQSgated; |
| 4549 | |
| 4550 | ucbest_coarse_ui_P1_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i]; |
| 4551 | ucbest_coarse_mck_P1_backup[p->rank][dqs_i] = rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i]; |
| 4552 | #endif |
| 4553 | } |
| 4554 | |
| 4555 | #if RDSEL_TRACKING_EN |
| 4556 | if(p->frequency >= RDSEL_TRACKING_TH) |
| 4557 | { |
| 4558 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4559 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4560 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), |
| 4561 | (ucbest_coarse_mck_backup[p->rank][0] << 4) | (ucbest_coarse_ui_backup[p->rank][0]), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4562 | SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4563 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), rxdqs_best_win->best_dqsien_dly_pi[0], |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4564 | SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0); |
| 4565 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4566 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), |
| 4567 | (ucbest_coarse_mck_backup[p->rank][1] << 4) | (ucbest_coarse_ui_backup[p->rank][1]), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4568 | SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4569 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4570 | rxdqs_best_win->best_dqsien_dly_pi[1], SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4571 | } |
| 4572 | #endif |
| 4573 | |
| 4574 | } |
| 4575 | |
| 4576 | #if GATING_AUTO_K_SUPPORT |
| 4577 | static void rxdqs_gating_auto_cal_reset(DRAMC_CTX_T *p) |
| 4578 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4579 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4580 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), |
| 4581 | P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST) | |
| 4582 | P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST) | |
| 4583 | P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST)); |
| 4584 | |
| 4585 | mcDELAY_US(1); |
| 4586 | |
| 4587 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), |
| 4588 | P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST) | |
| 4589 | P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST) | |
| 4590 | P_Fld(0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST)); |
| 4591 | } |
| 4592 | static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p, |
| 4593 | struct rxdqs_gating_auto_param *auto_param) |
| 4594 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4595 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4596 | rxdqs_gating_auto_cal_reset(p); |
| 4597 | |
| 4598 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4599 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4600 | if (p->frequency == 800) { |
| 4601 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), |
| 4602 | 0x1, MISC_STBCAL1_STBCNT_SW_RST); |
| 4603 | } |
| 4604 | |
| 4605 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), |
| 4606 | 0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN); |
| 4607 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4608 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4609 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 4610 | 0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); |
| 4611 | |
| 4612 | if (p->dram_type == TYPE_LPDDR5) { |
| 4613 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 4614 | 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); |
| 4615 | } |
| 4616 | |
| 4617 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), |
| 4618 | 0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD); |
| 4619 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4620 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4621 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), |
| 4622 | 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); |
| 4623 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), |
| 4624 | 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); |
| 4625 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 4626 | 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); |
| 4627 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4628 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4629 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), |
| 4630 | 0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE); |
| 4631 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4632 | { |
| 4633 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), |
| 4634 | 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0); |
| 4635 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), |
| 4636 | 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1); |
| 4637 | } |
| 4638 | |
| 4639 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), |
| 4640 | 0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0); |
| 4641 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), |
| 4642 | 0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1); |
| 4643 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), |
| 4644 | 0x1, MISC_STBCAL_DQSIENMODE); |
| 4645 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4646 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4647 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 4648 | P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) | |
| 4649 | P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) | |
| 4650 | P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN)); |
| 4651 | |
| 4652 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), |
| 4653 | 0x1, B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0); |
| 4654 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), |
| 4655 | 0x1, B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1); |
| 4656 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4657 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4658 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD), |
| 4659 | 0x1, DUMMY_RD_DUMMY_RD_PA_OPT); |
| 4660 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0), |
| 4661 | 0x1, MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE); |
| 4662 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4663 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4664 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR), 3, RK_DUMMY_RD_ADR_DMY_RD_LEN); |
| 4665 | |
| 4666 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4667 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4), |
| 4668 | 0x4, TEST2_A4_TESTAGENTRKSEL); |
| 4669 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4670 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4671 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), |
| 4672 | P_Fld(auto_param->init_mck, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI_MCK) | |
| 4673 | P_Fld(auto_param->init_ui, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI__UI) | |
| 4674 | P_Fld(auto_param->end_mck, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END_MCK) | |
| 4675 | P_Fld(auto_param->end_ui, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END__UI) | |
| 4676 | P_Fld(auto_param->pi_offset, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_PI_OFFSET) | |
| 4677 | P_Fld(p->rank, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CUR_RANK) | |
| 4678 | P_Fld(auto_param->burst_len, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_BURST_LENGTH) | |
| 4679 | P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B0_EN) | |
| 4680 | P_Fld(0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B1_EN)); |
| 4681 | |
| 4682 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), |
| 4683 | auto_param->dbg_mode, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_DEBUG_MODE_EN); |
| 4684 | |
| 4685 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), |
| 4686 | auto_param->early_break, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_EARLY_BREAK_EN); |
| 4687 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4688 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4689 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), |
| 4690 | 0x0, MISC_STBCAL_PICGEN); |
| 4691 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), |
| 4692 | P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) | |
| 4693 | P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN)); |
| 4694 | |
| 4695 | mcSHOW_DBG_MSG(("[Gating] AUTO K with param:\n")); |
| 4696 | mcSHOW_DBG_MSG(("\tinit_mck: %d, init_ui: %d, end_mck: %d, end_ui: %d\n", |
| 4697 | auto_param->init_mck, auto_param->init_ui, |
| 4698 | auto_param->end_mck, auto_param->end_ui)); |
| 4699 | mcSHOW_DBG_MSG(("\tpi_offset: %d, early_break: %s\n", auto_param->pi_offset, |
| 4700 | (auto_param->early_break)? "ENABLE" : "DISABLE")); |
| 4701 | } |
| 4702 | |
| 4703 | static void rxdqs_gating_auto_cal_trigger(DRAMC_CTX_T *p) |
| 4704 | { |
| 4705 | mcSHOW_DBG_MSG(("[Gating] AUTO K start...\n")); |
| 4706 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), |
| 4707 | 0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO); |
| 4708 | } |
| 4709 | |
| 4710 | static void rxdqs_gating_auto_cal_stop(DRAMC_CTX_T *p) |
| 4711 | { |
| 4712 | mcSHOW_DBG_MSG(("[Gating] AUTO K stop...\n")); |
| 4713 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0), |
| 4714 | 0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO); |
| 4715 | |
| 4716 | rxdqs_gating_auto_cal_reset(p); |
| 4717 | } |
| 4718 | #endif |
| 4719 | |
| 4720 | static void rxdqs_gating_set_final_result(DRAMC_CTX_T *p, U8 mck2ui, |
| 4721 | struct rxdqs_gating_best_win *best_win) |
| 4722 | { |
| 4723 | //U8 reg_mck, reg_ui; |
| 4724 | //U8 value; |
| 4725 | //U8 reg_mck_rodt[DQS_BYTE_NUMBER], reg_ui_rodt[DQS_BYTE_NUMBER]; |
| 4726 | //U8 reg_mck_rodt_p1[DQS_BYTE_NUMBER], reg_ui_rodt_p1[DQS_BYTE_NUMBER]; |
| 4727 | //U8 dqs_i; |
| 4728 | |
| 4729 | #if GATING_RODT_LATANCY_EN |
| 4730 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { |
| 4731 | reg_mck = best_win->best_dqsien_dly_mck[dqs_i]; |
| 4732 | reg_ui = best_win->best_dqsien_dly_ui[dqs_i]; |
| 4733 | |
| 4734 | value = (reg_mck * mck2ui) + reg_ui; |
| 4735 | |
| 4736 | if (value >= 11) { |
| 4737 | U8 rodt_mck2ui = get_rodt_mck2ui(p); |
| 4738 | |
| 4739 | value -= 11; |
| 4740 | reg_mck_rodt[dqs_i] = value / rodt_mck2ui; |
| 4741 | reg_ui_rodt[dqs_i] = value % rodt_mck2ui; |
| 4742 | |
| 4743 | reg_mck_rodt_p1[dqs_i] = reg_mck_rodt[dqs_i]; |
| 4744 | reg_ui_rodt_p1[dqs_i] = reg_ui_rodt[dqs_i]; |
| 4745 | } else { |
| 4746 | |
| 4747 | reg_mck_rodt[dqs_i] = 0; |
| 4748 | reg_ui_rodt[dqs_i] = 0; |
| 4749 | reg_mck_rodt_p1[dqs_i] = 4; |
| 4750 | reg_ui_rodt_p1[dqs_i] = 4; |
| 4751 | mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI for B%d\n", |
| 4752 | dqs_i)); |
| 4753 | } |
| 4754 | |
| 4755 | mcSHOW_DBG_MSG(("DQS%d Final RODTEN: (%2d, %2d)\n", |
| 4756 | dqs_i, reg_mck_rodt[dqs_i], reg_ui_rodt[dqs_i])); |
| 4757 | mcSHOW_DBG_MSG(("DQS%d Final RODTEN_P1: (%2d, %2d)\n", |
| 4758 | dqs_i, reg_mck_rodt_p1[dqs_i], reg_ui_rodt_p1[dqs_i])); |
| 4759 | } |
| 4760 | #endif |
| 4761 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4762 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4763 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), |
| 4764 | P_Fld(best_win->best_dqsien_dly_mck[0], |
| 4765 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | |
| 4766 | P_Fld(best_win->best_dqsien_dly_ui[0], |
| 4767 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | |
| 4768 | P_Fld(best_win->best_dqsien_dly_mck_p1[0], |
| 4769 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | |
| 4770 | P_Fld(best_win->best_dqsien_dly_ui_p1[0], |
| 4771 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); |
| 4772 | |
| 4773 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), |
| 4774 | P_Fld(best_win->best_dqsien_dly_mck[1], |
| 4775 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | |
| 4776 | P_Fld(best_win->best_dqsien_dly_ui[1], |
| 4777 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | |
| 4778 | P_Fld(best_win->best_dqsien_dly_mck_p1[1], |
| 4779 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | |
| 4780 | P_Fld(best_win->best_dqsien_dly_ui_p1[1], |
| 4781 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); |
| 4782 | |
| 4783 | #if GATING_RODT_LATANCY_EN |
| 4784 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), |
| 4785 | P_Fld(reg_mck_rodt[0], |
| 4786 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | |
| 4787 | P_Fld(reg_ui_rodt[0], |
| 4788 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | |
| 4789 | P_Fld(reg_mck_rodt_p1[0], |
| 4790 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | |
| 4791 | P_Fld(reg_ui_rodt_p1[0], |
| 4792 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); |
| 4793 | |
| 4794 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), |
| 4795 | P_Fld(reg_mck_rodt[1], |
| 4796 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | |
| 4797 | P_Fld(reg_ui_rodt[1], |
| 4798 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | |
| 4799 | P_Fld(reg_mck_rodt_p1[1], |
| 4800 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | |
| 4801 | P_Fld(reg_ui_rodt_p1[1], |
| 4802 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); |
| 4803 | #endif |
| 4804 | |
| 4805 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), |
| 4806 | best_win->best_dqsien_dly_pi[0], |
| 4807 | SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); |
| 4808 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), |
| 4809 | best_win->best_dqsien_dly_pi[1], |
| 4810 | SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); |
| 4811 | |
| 4812 | } |
| 4813 | |
| 4814 | #if GATING_AUTO_K_SUPPORT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4815 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4816 | static void rxdqs_gating_auto_xlate(DRAMC_CTX_T *p, |
| 4817 | struct rxdqs_gating_best_win *best_win, |
| 4818 | struct rxdqs_gating_cal *rxdqs_cal) |
| 4819 | { |
| 4820 | u8 mck, ui, pi; |
| 4821 | U8 mck_p1, ui_p1; |
| 4822 | u8 mck2ui, freq_div; |
| 4823 | U8 total_ui; |
| 4824 | #if GATING_RODT_LATANCY_EN |
| 4825 | U8 mck_rodt, ui_rodt; |
| 4826 | U8 mck_rodt_p1, ui_rodt_p1; |
| 4827 | #endif |
| 4828 | U16 value; |
| 4829 | u8 dqs_i; |
| 4830 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4831 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4832 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { |
| 4833 | mck = best_win->best_dqsien_dly_mck[dqs_i]; |
| 4834 | ui = best_win->best_dqsien_dly_ui[dqs_i]; |
| 4835 | pi = best_win->best_dqsien_dly_pi[dqs_i]; |
| 4836 | mck2ui = rxdqs_cal->dqsien_ui_per_mck; |
| 4837 | freq_div = rxdqs_cal->dqsien_freq_div; |
| 4838 | |
| 4839 | if (vGet_Div_Mode(p) == DIV16_MODE) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4840 | total_ui = (mck << 4) + ui; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4841 | else if (vGet_Div_Mode(p) == DIV8_MODE) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4842 | total_ui = (mck << 3) + ui; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4843 | else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4844 | total_ui = (mck << 2) + ui; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4845 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4846 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4847 | mck = (total_ui >> 4); |
| 4848 | ui = (total_ui & 0xf); |
| 4849 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4850 | value = mck * mck2ui + ui; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4851 | mck_p1 = (value + freq_div) / mck2ui; |
| 4852 | ui_p1 = (value + freq_div) % mck2ui; |
| 4853 | |
| 4854 | mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result: (%d, %d, %d)\n", dqs_i, mck, ui, pi)); |
| 4855 | mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result P1: (%d, %d)\n", dqs_i, mck_p1, ui_p1)); |
| 4856 | |
| 4857 | best_win->best_dqsien_dly_mck[dqs_i] = mck; |
| 4858 | best_win->best_dqsien_dly_ui[dqs_i] = ui; |
| 4859 | best_win->best_dqsien_dly_pi[dqs_i] = pi; |
| 4860 | |
| 4861 | best_win->best_dqsien_dly_mck_p1[dqs_i] = mck_p1; |
| 4862 | best_win->best_dqsien_dly_ui_p1[dqs_i] = ui_p1; |
| 4863 | best_win->best_dqsien_dly_pi_p1[dqs_i] = pi; |
| 4864 | } |
| 4865 | } |
| 4866 | |
| 4867 | #define RXDQS_GATING_AUTO_CAL_STATUS_BYTE_OFFSET 0x40 |
| 4868 | |
| 4869 | static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p, |
| 4870 | struct rxdqs_gating_auto_param *auto_param, |
| 4871 | struct rxdqs_gating_best_win *best_win) |
| 4872 | { |
| 4873 | U8 mck_center[DQS_BYTE_NUMBER], ui_center[DQS_BYTE_NUMBER], pi_center[DQS_BYTE_NUMBER]; |
| 4874 | U8 mck_left[DQS_BYTE_NUMBER], ui_left[DQS_BYTE_NUMBER], pi_left[DQS_BYTE_NUMBER]; |
| 4875 | U8 mck_right[DQS_BYTE_NUMBER], ui_right[DQS_BYTE_NUMBER], pi_right[DQS_BYTE_NUMBER]; |
| 4876 | U8 done[DQS_BYTE_NUMBER] = { 0 }, error[DQS_BYTE_NUMBER] = { 0 }; |
| 4877 | DRAM_STATUS_T ret; |
| 4878 | U8 done_bytes, total_bytes; |
| 4879 | U8 byte_ofst; |
| 4880 | U8 dqs_i; |
| 4881 | //U8 div_mode; |
| 4882 | |
| 4883 | total_bytes = DQS_BYTE_NUMBER; |
| 4884 | done_bytes = 0; |
| 4885 | ret = DRAM_OK; |
| 4886 | |
| 4887 | while (done_bytes < total_bytes) { |
| 4888 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4889 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4890 | if (done[dqs_i]) |
| 4891 | continue; |
| 4892 | |
| 4893 | byte_ofst = dqs_i * RXDQS_GATING_AUTO_CAL_STATUS_BYTE_OFFSET; |
| 4894 | |
| 4895 | done[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4896 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), |
| 4897 | DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_DONE_B0_RK0); |
| 4898 | error[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4899 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), |
| 4900 | DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0); |
| 4901 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4902 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4903 | if (done[dqs_i] || error[dqs_i]) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4904 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4905 | if (error[dqs_i] == 0) { |
| 4906 | mck_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4907 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), |
| 4908 | DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK0); |
| 4909 | ui_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4910 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), |
| 4911 | DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK0); |
| 4912 | pi_center[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4913 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 + byte_ofst), |
| 4914 | DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK0); |
| 4915 | |
| 4916 | mck_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4917 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), |
| 4918 | DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK0); |
| 4919 | ui_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4920 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), |
| 4921 | DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK0); |
| 4922 | pi_left[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4923 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), |
| 4924 | DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0); |
| 4925 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4926 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4927 | if (auto_param->early_break == DISABLE) { |
| 4928 | mck_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4929 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), |
| 4930 | DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK0); |
| 4931 | ui_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4932 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), |
| 4933 | DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK0); |
| 4934 | pi_right[dqs_i] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 4935 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 + byte_ofst), |
| 4936 | DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK0); |
| 4937 | } |
| 4938 | } |
| 4939 | else |
| 4940 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4941 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4942 | done[dqs_i] = 1; |
| 4943 | } |
| 4944 | |
| 4945 | if (auto_param->dbg_mode == ENABLE) { |
| 4946 | U32 dbg_reg_addr; |
| 4947 | U32 dbg_reg_idx; |
| 4948 | U32 dbg_reg_val; |
| 4949 | |
| 4950 | dbg_reg_addr = DRAMC_REG_ADDR( |
| 4951 | DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS0 + byte_ofst); |
| 4952 | for (dbg_reg_idx = 0; |
| 4953 | dbg_reg_idx < RXDQS_GATING_AUTO_DBG_REG_NUM; |
| 4954 | dbg_reg_idx++, dbg_reg_addr += 4) { |
| 4955 | dbg_reg_val = u4IO32Read4B(dbg_reg_addr); |
| 4956 | |
| 4957 | mcSHOW_ERR_MSG(("B%d Gating AUTOK DBG Status-%d: [0x%08x]\n", |
| 4958 | dqs_i, dbg_reg_idx, dbg_reg_val)); |
| 4959 | } |
| 4960 | } |
| 4961 | } |
| 4962 | else |
| 4963 | { |
| 4964 | mcSHOW_ERR_MSG(("B%d Gating AUTOK didn't be done\n", dqs_i)); |
| 4965 | } |
| 4966 | done_bytes++; |
| 4967 | } |
| 4968 | |
| 4969 | mcDELAY_MS(1); |
| 4970 | } |
| 4971 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4972 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4973 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { |
| 4974 | mcSHOW_DBG_MSG(("[Gating][%s] AUTOK of CH-%d, Rk-%d, Byte-%d:\n", |
| 4975 | error[dqs_i]? "Fail" : "Pass", p->channel, p->rank, dqs_i)); |
| 4976 | |
| 4977 | if (done[dqs_i]) { |
| 4978 | if (error[dqs_i] == 0) { |
| 4979 | mcSHOW_DBG_MSG(("\tcenter(%2d, %2d, %2d)\n", |
| 4980 | mck_center[dqs_i], ui_center[dqs_i], pi_center[dqs_i])); |
| 4981 | mcSHOW_DBG_MSG(("\tleft(%2d, %2d, %2d)\n", |
| 4982 | mck_left[dqs_i], ui_left[dqs_i], pi_left[dqs_i])); |
| 4983 | |
| 4984 | if (auto_param->early_break == DISABLE) { |
| 4985 | mcSHOW_DBG_MSG(("\tright(%2d, %2d, %2d)\n", |
| 4986 | mck_right[dqs_i], ui_right[dqs_i], pi_right[dqs_i])); |
| 4987 | } |
| 4988 | } |
| 4989 | if (error[dqs_i]) { |
| 4990 | ret = DRAM_FAIL; |
| 4991 | } else { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 4992 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 4993 | best_win->best_dqsien_dly_mck[dqs_i] = mck_center[dqs_i]; |
| 4994 | best_win->best_dqsien_dly_ui[dqs_i] = ui_center[dqs_i]; |
| 4995 | best_win->best_dqsien_dly_pi[dqs_i] = pi_center[dqs_i]; |
| 4996 | } |
| 4997 | } |
| 4998 | } |
| 4999 | |
| 5000 | rxdqs_gating_auto_cal_stop(p); |
| 5001 | |
| 5002 | return ret; |
| 5003 | } |
| 5004 | |
| 5005 | static DRAM_STATUS_T dramc_rx_dqs_gating_auto_cal(DRAMC_CTX_T *p) |
| 5006 | { |
| 5007 | struct rxdqs_gating_auto_param auto_param; |
| 5008 | struct rxdqs_gating_best_win rxdqs_best_win; |
| 5009 | struct rxdqs_gating_cal rxdqs_cal; |
| 5010 | DRAM_STATUS_T ret; |
| 5011 | U8 start_ui, end_ui; |
| 5012 | U8 mck2ui_hw; //mck2ui_rg, freq_div |
| 5013 | |
| 5014 | U32 reg_backup_address[ ] = { |
| 5015 | (DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD)), |
| 5016 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0)), |
| 5017 | (DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4)), |
| 5018 | (DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR)) |
| 5019 | }; |
| 5020 | |
| 5021 | DramcBackupRegisters(p, reg_backup_address, |
| 5022 | sizeof (reg_backup_address) / sizeof (U32)); |
| 5023 | |
| 5024 | ret = DRAM_OK; |
| 5025 | |
| 5026 | memset((void *)&auto_param, 0, sizeof auto_param); |
| 5027 | memset((void *)&rxdqs_best_win, 0, sizeof rxdqs_best_win); |
| 5028 | memset((void *)&rxdqs_cal, 0, sizeof rxdqs_cal); |
| 5029 | |
| 5030 | if (vGet_Div_Mode(p) == DIV4_MODE) |
| 5031 | rxdqs_cal.dqsien_freq_div = 2; |
| 5032 | else |
| 5033 | rxdqs_cal.dqsien_freq_div = 4; |
| 5034 | rxdqs_cal.dqsien_ui_per_mck = DQS_GW_UI_PER_MCK; |
| 5035 | |
| 5036 | if (!rxdqs_gating_bypass(p)) { |
| 5037 | if (vGet_Div_Mode(p) == DIV16_MODE) |
| 5038 | mck2ui_hw = 16; |
| 5039 | else if (vGet_Div_Mode(p) == DIV8_MODE) |
| 5040 | mck2ui_hw = 8; |
| 5041 | else |
| 5042 | mck2ui_hw = 4; |
| 5043 | |
| 5044 | #if ENABLE_GATING_AUTOK_WA |
| 5045 | if (__wa__gating_autok_init_ui[p->rank] > 3) |
| 5046 | start_ui = __wa__gating_autok_init_ui[p->rank] - 3; |
| 5047 | else |
| 5048 | #endif |
| 5049 | start_ui = u1GetGatingStartPos(p, AUTOK_ON); |
| 5050 | end_ui = start_ui + 32; |
| 5051 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5052 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5053 | auto_param.early_break = ENABLE; |
| 5054 | auto_param.dbg_mode = ENABLE; |
| 5055 | auto_param.init_mck = start_ui / mck2ui_hw; |
| 5056 | auto_param.init_ui = start_ui % mck2ui_hw; |
| 5057 | auto_param.end_mck = end_ui / mck2ui_hw; |
| 5058 | auto_param.end_ui = end_ui % mck2ui_hw; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5059 | auto_param.pi_offset = 2; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5060 | auto_param.burst_len = RXDQS_BURST_LEN_8; |
| 5061 | |
| 5062 | |
| 5063 | #if FOR_DV_SIMULATION_USED == 1 |
| 5064 | cal_sv_rand_args_t *psra = get_psra(); |
| 5065 | |
| 5066 | if (psra) { |
| 5067 | auto_param.early_break = |
| 5068 | psra->dqsien_autok_early_break_en? ENABLE: DISABLE; |
| 5069 | auto_param.dbg_mode = |
| 5070 | psra->dqsien_autok_dbg_mode_en? ENABLE: DISABLE; |
| 5071 | auto_param.pi_offset = |
| 5072 | psra->dqsien_autok_pi_offset? ENABLE: DISABLE; |
| 5073 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5074 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5075 | |
| 5076 | rxdqs_gating_auto_cal_cfg(p, &auto_param); |
| 5077 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5078 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5079 | rxdqs_gating_auto_cal_trigger(p); |
| 5080 | |
| 5081 | ret = rxdqs_gating_auto_cal_status(p, &auto_param, &rxdqs_best_win); |
| 5082 | if (ret == DRAM_OK) |
| 5083 | vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK); |
| 5084 | |
| 5085 | rxdqs_gating_auto_xlate(p, &rxdqs_best_win, &rxdqs_cal); |
| 5086 | } |
| 5087 | |
| 5088 | rxdqs_gating_fastk_save_restore(p, &rxdqs_best_win, &rxdqs_cal); |
| 5089 | rxdqs_gating_set_final_result(p, rxdqs_cal.dqsien_ui_per_mck, &rxdqs_best_win); |
| 5090 | |
| 5091 | rxdqs_gating_misc_process(p, &rxdqs_best_win); |
| 5092 | DramcRestoreRegisters(p, reg_backup_address, |
| 5093 | sizeof (reg_backup_address) / sizeof (U32)); |
| 5094 | |
| 5095 | DramPhyReset(p); |
| 5096 | |
| 5097 | return ret; |
| 5098 | } |
| 5099 | #endif |
| 5100 | |
| 5101 | static void rxdqs_gating_sw_cal_init(DRAMC_CTX_T *p, U8 use_enhanced_rdqs) |
| 5102 | { |
| 5103 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5104 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5105 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0), 0, SHU_CONF0_PBREFEN); |
| 5106 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5107 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5108 | if (p->frequency == 800) { |
| 5109 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), |
| 5110 | 0x1, MISC_STBCAL1_STBCNT_SW_RST); |
| 5111 | } |
| 5112 | |
| 5113 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), |
| 5114 | 0x1, MISC_STBCAL1_STBCNT_SHU_RST_EN); |
| 5115 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5116 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5117 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 5118 | 0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN); |
| 5119 | |
| 5120 | if (p->dram_type == TYPE_LPDDR5) { |
| 5121 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 5122 | 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); |
| 5123 | } |
| 5124 | |
| 5125 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), |
| 5126 | 0x1, MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD); |
| 5127 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5128 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5129 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), |
| 5130 | 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); |
| 5131 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), |
| 5132 | 0x1, B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0); |
| 5133 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 5134 | 0x1, MISC_STBCAL2_STB_PICG_EARLY_1T_EN); |
| 5135 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5136 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5137 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), |
| 5138 | 0x1, MISC_SHU_STBCAL_DQSIEN_BURST_MODE); |
| 5139 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5140 | { |
| 5141 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9), |
| 5142 | 0x1, B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0); |
| 5143 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9), |
| 5144 | 0x1, B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1); |
| 5145 | } |
| 5146 | |
| 5147 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), |
| 5148 | 0x2, B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0); |
| 5149 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), |
| 5150 | 0x2, B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1); |
| 5151 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), |
| 5152 | 0x1, MISC_STBCAL_DQSIENMODE); |
| 5153 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5154 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5155 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), |
| 5156 | P_Fld(0x1, MISC_STBCAL2_STB_IG_XRANK_CG_RST) | |
| 5157 | P_Fld(0x1, MISC_STBCAL2_STB_RST_BY_RANK) | |
| 5158 | P_Fld(0x1, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN)); |
| 5159 | |
| 5160 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), |
| 5161 | 0x1, B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0); |
| 5162 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), |
| 5163 | 0x1, B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1); |
| 5164 | |
| 5165 | //DramcHWGatingOnOff(p, 0); |
| 5166 | |
| 5167 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, |
| 5168 | MISC_STBCAL2_STBENCMPEN); |
| 5169 | |
| 5170 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0), 0, |
| 5171 | RX_SET0_DM4TO1MODE); |
| 5172 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5173 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5174 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, |
| 5175 | MISC_STBCAL2_DQSG_CNT_EN); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5176 | mcDELAY_US(4); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5177 | |
| 5178 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, |
| 5179 | MISC_STBCAL2_DQSG_CNT_RST); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5180 | mcDELAY_US(1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5181 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, |
| 5182 | MISC_STBCAL2_DQSG_CNT_RST); |
| 5183 | |
| 5184 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), |
| 5185 | u1GetRank(p), MISC_CTRL1_R_DMSTBENCMP_RK_OPT); |
| 5186 | DramcEngine2Init(p, 0x55000000, |
| 5187 | 0xaa000000 | GATING_PATTERN_NUM_LP5, TEST_AUDIO_PATTERN, 0, TE_NO_UI_SHIFT); |
| 5188 | |
| 5189 | if (use_enhanced_rdqs) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5190 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5191 | } |
| 5192 | } |
| 5193 | |
| 5194 | static void rxdqs_gating_set_dqsien_dly(DRAMC_CTX_T *p, U8 dly_ui, |
| 5195 | struct rxdqs_gating_cal *rxdqs_cal) |
| 5196 | { |
| 5197 | //U32 value; |
| 5198 | U32 reg_mck, reg_ui; |
| 5199 | U32 reg_mck_p1, reg_ui_p1; |
| 5200 | #if GATING_RODT_LATANCY_EN |
| 5201 | U32 reg_mck_rodt, reg_ui_rodt; |
| 5202 | U32 reg_mck_rodt_p1, reg_ui_rodt_p1; |
| 5203 | #endif |
| 5204 | U8 mck2ui = rxdqs_cal->dqsien_ui_per_mck; |
| 5205 | |
| 5206 | rxdqs_cal->dqsien_dly_mck = dly_ui / rxdqs_cal->dqsien_ui_per_mck; |
| 5207 | rxdqs_cal->dqsien_dly_ui = dly_ui % rxdqs_cal->dqsien_ui_per_mck; |
| 5208 | rxdqs_cal->dqsien_dly_mck_p1 = (dly_ui + rxdqs_cal->dqsien_freq_div) / mck2ui; |
| 5209 | rxdqs_cal->dqsien_dly_ui_p1 = (dly_ui + rxdqs_cal->dqsien_freq_div) % mck2ui; |
| 5210 | |
| 5211 | reg_mck = rxdqs_cal->dqsien_dly_mck; |
| 5212 | reg_ui = rxdqs_cal->dqsien_dly_ui; |
| 5213 | reg_mck_p1 = rxdqs_cal->dqsien_dly_mck_p1; |
| 5214 | reg_ui_p1 = rxdqs_cal->dqsien_dly_ui_p1; |
| 5215 | |
| 5216 | #if GATING_RODT_LATANCY_EN |
| 5217 | value = (reg_mck * mck2ui) + reg_ui; |
| 5218 | |
| 5219 | if (value >= 11) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5220 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5221 | U8 rodt_mck2ui = get_rodt_mck2ui(p); |
| 5222 | |
| 5223 | value -= 11; |
| 5224 | reg_mck_rodt = value / rodt_mck2ui; |
| 5225 | reg_ui_rodt = value % rodt_mck2ui; |
| 5226 | |
| 5227 | reg_mck_rodt_p1 = reg_mck_rodt; |
| 5228 | reg_ui_rodt_p1 = reg_ui_rodt; |
| 5229 | } else { |
| 5230 | |
| 5231 | reg_mck_rodt = 0; |
| 5232 | reg_ui_rodt = 0; |
| 5233 | reg_mck_rodt_p1 = 4; |
| 5234 | reg_ui_rodt_p1 = 4; |
| 5235 | mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI\n")); |
| 5236 | } |
| 5237 | #endif |
| 5238 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5239 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5240 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), |
| 5241 | P_Fld(reg_mck, |
| 5242 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | |
| 5243 | P_Fld(reg_ui, |
| 5244 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | |
| 5245 | P_Fld(reg_mck_p1, |
| 5246 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | |
| 5247 | P_Fld(reg_ui_p1, |
| 5248 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); |
| 5249 | |
| 5250 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), |
| 5251 | P_Fld(reg_mck, |
| 5252 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | |
| 5253 | P_Fld(reg_ui, |
| 5254 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | |
| 5255 | P_Fld(reg_mck_p1, |
| 5256 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | |
| 5257 | P_Fld(reg_ui_p1, |
| 5258 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); |
| 5259 | |
| 5260 | #if GATING_RODT_LATANCY_EN |
| 5261 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY), |
| 5262 | P_Fld(reg_mck_rodt, |
| 5263 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0) | |
| 5264 | P_Fld(reg_ui_rodt, |
| 5265 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0) | |
| 5266 | P_Fld(reg_mck_rodt_p1, |
| 5267 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0) | |
| 5268 | P_Fld(reg_ui_rodt_p1, |
| 5269 | SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0)); |
| 5270 | |
| 5271 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY), |
| 5272 | P_Fld(reg_mck_rodt, |
| 5273 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1) | |
| 5274 | P_Fld(reg_ui_rodt, |
| 5275 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1) | |
| 5276 | P_Fld(reg_mck_rodt_p1, |
| 5277 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1) | |
| 5278 | P_Fld(reg_ui_rodt_p1, |
| 5279 | SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1)); |
| 5280 | #endif |
| 5281 | } |
| 5282 | |
| 5283 | static void rxdqs_gating_sw_cal_trigger(DRAMC_CTX_T *p, |
| 5284 | struct rxdqs_gating_cal *rxdqs_cal) |
| 5285 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5286 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5287 | if (u1IsPhaseMode(p) == TRUE) { |
| 5288 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), |
| 5289 | rxdqs_cal->dqsien_dly_pi >> 4, SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0); |
| 5290 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), |
| 5291 | rxdqs_cal->dqsien_dly_pi >> 4, SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1); |
| 5292 | } else |
| 5293 | #endif |
| 5294 | { |
| 5295 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), |
| 5296 | rxdqs_cal->dqsien_dly_pi, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); |
| 5297 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY), |
| 5298 | rxdqs_cal->dqsien_dly_pi, SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); |
| 5299 | } |
| 5300 | DramPhyReset(p); |
| 5301 | |
| 5302 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 1, |
| 5303 | MISC_STBCAL2_DQSG_CNT_RST); |
| 5304 | mcDELAY_US(1); |
| 5305 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0, |
| 5306 | MISC_STBCAL2_DQSG_CNT_RST); |
| 5307 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5308 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5309 | DramcEngine2Run(p, TE_OP_READ_CHECK, TEST_AUDIO_PATTERN); |
| 5310 | } |
| 5311 | |
| 5312 | static void rxdqs_gating_get_leadlag(DRAMC_CTX_T *p, |
| 5313 | struct rxdqs_gating_trans *rxdqs_trans, |
| 5314 | struct rxdqs_gating_cal *rxdqs_cal) |
| 5315 | { |
| 5316 | U8 dqs_i; |
| 5317 | U8 debounce_thrd_PI = 16; |
| 5318 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
| 5319 | |
| 5320 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { |
| 5321 | if (dqs_i == 0) { |
| 5322 | rxdqs_trans->dqs_lead[0] = u4IO32ReadFldAlign( |
| 5323 | DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B0), |
| 5324 | MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0); |
| 5325 | rxdqs_trans->dqs_lag[0] = u4IO32ReadFldAlign( |
| 5326 | DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B0), |
| 5327 | MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0); |
| 5328 | } else { |
| 5329 | if (isLP4_DSC){ |
| 5330 | rxdqs_trans->dqs_lead[1] = u4IO32ReadFldAlign( |
| 5331 | DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD), |
| 5332 | MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD); |
| 5333 | rxdqs_trans->dqs_lag[1] = u4IO32ReadFldAlign( |
| 5334 | DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD), |
| 5335 | MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG); |
| 5336 | } else { |
| 5337 | rxdqs_trans->dqs_lead[1] = u4IO32ReadFldAlign( |
| 5338 | DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B1), |
| 5339 | MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1); |
| 5340 | rxdqs_trans->dqs_lag[1] = u4IO32ReadFldAlign( |
| 5341 | DRAMC_REG_ADDR(DDRPHY_REG_MISC_PHY_RGS_STBEN_B1), |
| 5342 | MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1); |
| 5343 | } |
| 5344 | |
| 5345 | } |
| 5346 | |
| 5347 | if ((rxdqs_trans->dqs_lead[dqs_i] == 1) && |
| 5348 | (rxdqs_trans->dqs_lag[dqs_i] == 1)) { |
| 5349 | rxdqs_trans->dqs_high[dqs_i]++; |
| 5350 | rxdqs_trans->dqs_transition[dqs_i] = 1; |
| 5351 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5352 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5353 | rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] = |
| 5354 | rxdqs_cal->dqsien_dly_mck; |
| 5355 | rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] = |
| 5356 | rxdqs_cal->dqsien_dly_ui; |
| 5357 | rxdqs_trans->dqsien_dly_pi_leadlag[dqs_i] = |
| 5358 | rxdqs_cal->dqsien_dly_pi; |
| 5359 | } else if ((rxdqs_trans->dqs_high[dqs_i] * |
| 5360 | rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5361 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5362 | if (((rxdqs_trans->dqs_lead[dqs_i] == 1) && |
| 5363 | (rxdqs_trans->dqs_lag[dqs_i] == 0)) || |
| 5364 | ((rxdqs_trans->dqs_lead[dqs_i] == 0) && |
| 5365 | (rxdqs_trans->dqs_lag[dqs_i] == 1))) { |
| 5366 | rxdqs_trans->dqs_transition[dqs_i]++; |
| 5367 | } |
| 5368 | #if GATING_LEADLAG_LOW_LEVEL_CHECK |
| 5369 | else if ((rxdqs_trans->dqs_lead[dqs_i] == 0) && |
| 5370 | (rxdqs_trans->dqs_lag[dqs_i] == 0)){ |
| 5371 | if ((rxdqs_trans->dqs_low[dqs_i] * |
| 5372 | rxdqs_cal->dqsien_pi_adj_step) >= debounce_thrd_PI) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5373 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5374 | rxdqs_trans->dqs_transitioned[dqs_i] = 1; |
| 5375 | } |
| 5376 | rxdqs_trans->dqs_low[dqs_i]++; |
| 5377 | }else { |
| 5378 | rxdqs_trans->dqs_high[dqs_i] = 0; |
| 5379 | rxdqs_trans->dqs_low[dqs_i] = 0; |
| 5380 | } |
| 5381 | #else |
| 5382 | else { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5383 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5384 | rxdqs_trans->dqs_transitioned[dqs_i] = 1; |
| 5385 | } |
| 5386 | #endif |
| 5387 | } else { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5388 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5389 | rxdqs_trans->dqs_high[dqs_i] = 0; |
| 5390 | #if GATING_LEADLAG_LOW_LEVEL_CHECK |
| 5391 | rxdqs_trans->dqs_low[dqs_i] = 0; |
| 5392 | #endif |
| 5393 | } |
| 5394 | } |
| 5395 | } |
| 5396 | |
| 5397 | static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p, |
| 5398 | struct rxdqs_gating_trans *rxdqs_trans, |
| 5399 | struct rxdqs_gating_cal *rxdqs_cal, U8 *pass_byte_count, |
| 5400 | struct rxdqs_gating_best_win *best_win, U8 dly_ui, U8 dly_ui_end) |
| 5401 | { |
| 5402 | U8 gating_error[DQS_BYTE_NUMBER]; |
| 5403 | U32 debug_cnt[DQS_BYTE_NUMBER]; |
| 5404 | U32 debug_pass_cnt; |
| 5405 | U8 dqs_i; |
| 5406 | //U8 dqs_result_r, dqs_result_f; |
| 5407 | //U16 debug_cnt_per_byte; |
| 5408 | U8 passed_bytes; |
| 5409 | |
| 5410 | memset(debug_cnt, 0, sizeof(debug_cnt)); |
| 5411 | passed_bytes = *pass_byte_count; |
| 5412 | |
| 5413 | rxdqs_gating_sw_cal_trigger(p, rxdqs_cal); |
| 5414 | |
| 5415 | if (p->rank == RANK_0) { |
| 5416 | gating_error[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 5417 | DDRPHY_REG_MISC_STBERR_ALL), |
| 5418 | MISC_STBERR_ALL_GATING_ERROR_B0_RK0); |
| 5419 | gating_error[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 5420 | DDRPHY_REG_MISC_STBERR_ALL), |
| 5421 | MISC_STBERR_ALL_GATING_ERROR_B1_RK0); |
| 5422 | } else { |
| 5423 | gating_error[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 5424 | DDRPHY_REG_MISC_STBERR_ALL), |
| 5425 | MISC_STBERR_ALL_GATING_ERROR_B0_RK1); |
| 5426 | gating_error[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR( |
| 5427 | DDRPHY_REG_MISC_STBERR_ALL), |
| 5428 | MISC_STBERR_ALL_GATING_ERROR_B1_RK1); |
| 5429 | } |
| 5430 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5431 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5432 | debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0)); |
| 5433 | debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1)); |
| 5434 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5435 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5436 | rxdqs_gating_get_leadlag(p, rxdqs_trans, rxdqs_cal); |
| 5437 | |
| 5438 | mcSHOW_DBG_MSG2(("%2d %2d %2d | ", |
| 5439 | rxdqs_cal->dqsien_dly_mck, rxdqs_cal->dqsien_dly_ui, |
| 5440 | rxdqs_cal->dqsien_dly_pi)); |
| 5441 | mcSHOW_DBG_MSG2(("B1->B0 | %x %x | %x %x | (%d %d) (%d %d)\n", |
| 5442 | debug_cnt[1], debug_cnt[0], |
| 5443 | gating_error[1], gating_error[0], |
| 5444 | rxdqs_trans->dqs_lead[1], rxdqs_trans->dqs_lag[1], |
| 5445 | rxdqs_trans->dqs_lead[0], rxdqs_trans->dqs_lag[0])); |
| 5446 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5447 | debug_pass_cnt = GATING_GOLDEND_DQSCNT_LP5; |
| 5448 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5449 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5450 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) { |
| 5451 | if (passed_bytes & (1 << dqs_i)) |
| 5452 | continue; |
| 5453 | |
| 5454 | if ((gating_error[dqs_i] == 0) && (debug_cnt[dqs_i] == debug_pass_cnt)) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5455 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5456 | if (rxdqs_trans->dqs_transitioned[dqs_i] != 0) { |
| 5457 | U8 pass_count = rxdqs_trans->dqs_transition[dqs_i]; |
| 5458 | U8 offset = (pass_count * rxdqs_cal->dqsien_pi_adj_step) / 2; |
| 5459 | U8 mck2ui, ui2pi, freq_div; |
| 5460 | U8 tmp; |
| 5461 | |
| 5462 | mck2ui = rxdqs_cal->dqsien_ui_per_mck; |
| 5463 | ui2pi = rxdqs_cal->dqsien_pi_per_ui; |
| 5464 | freq_div = rxdqs_cal->dqsien_freq_div; |
| 5465 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5466 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5467 | tmp = rxdqs_trans->dqsien_dly_pi_leadlag[dqs_i] + offset; |
| 5468 | best_win->best_dqsien_dly_pi[dqs_i] = tmp % ui2pi; |
| 5469 | best_win->best_dqsien_dly_pi_p1[dqs_i] = |
| 5470 | best_win->best_dqsien_dly_pi[dqs_i]; |
| 5471 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5472 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5473 | tmp /= ui2pi; |
| 5474 | tmp = rxdqs_trans->dqsien_dly_ui_leadlag[dqs_i] + tmp; |
| 5475 | best_win->best_dqsien_dly_ui[dqs_i] = tmp % mck2ui; |
| 5476 | best_win->best_dqsien_dly_mck[dqs_i] = |
| 5477 | rxdqs_trans->dqsien_dly_mck_leadlag[dqs_i] + (tmp / mck2ui); |
| 5478 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5479 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5480 | best_win->best_dqsien_dly_ui_p1[dqs_i] = |
| 5481 | best_win->best_dqsien_dly_mck[dqs_i] * mck2ui + |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5482 | best_win->best_dqsien_dly_ui[dqs_i] + freq_div; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5483 | /*mcSHOW_DBG_MSG(("Total UI for P1: %d, mck2ui %d\n", |
| 5484 | best_win->best_dqsien_dly_mck_p1[dqs_i], mck2ui));*/ |
| 5485 | best_win->best_dqsien_dly_mck_p1[dqs_i] = |
| 5486 | best_win->best_dqsien_dly_ui_p1[dqs_i] / mck2ui; |
| 5487 | best_win->best_dqsien_dly_ui_p1[dqs_i] = |
| 5488 | best_win->best_dqsien_dly_ui_p1[dqs_i] % mck2ui; |
| 5489 | |
| 5490 | /*mcSHOW_DBG_MSG(("best dqsien dly found for B%d: " |
| 5491 | "(%2d, %2d, %2d)\n", dqs_i, |
| 5492 | best_win->best_dqsien_dly_mck[dqs_i], |
| 5493 | best_win->best_dqsien_dly_ui[dqs_i], |
| 5494 | best_win->best_dqsien_dly_pi[dqs_i]));*/ |
| 5495 | |
| 5496 | passed_bytes |= 1 << dqs_i; |
| 5497 | |
| 5498 | if ((p->data_width == DATA_WIDTH_16BIT) && |
| 5499 | (passed_bytes == 0x3)) { |
| 5500 | dly_ui = dly_ui_end; |
| 5501 | break; |
| 5502 | } |
| 5503 | } |
| 5504 | } else { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5505 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5506 | rxdqs_trans->dqs_high[dqs_i] = 0; |
| 5507 | rxdqs_trans->dqs_transition[dqs_i] = 0; |
| 5508 | rxdqs_trans->dqs_transitioned[dqs_i] = 0; |
| 5509 | } |
| 5510 | } |
| 5511 | |
| 5512 | *pass_byte_count = passed_bytes; |
| 5513 | return dly_ui; |
| 5514 | } |
| 5515 | |
| 5516 | static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p, |
| 5517 | U8 use_enhance_rdqs) |
| 5518 | { |
| 5519 | struct rxdqs_gating_cal rxdqs_cal; |
| 5520 | struct rxdqs_gating_trans rxdqs_trans; |
| 5521 | struct rxdqs_gating_best_win rxdqs_best_win; |
| 5522 | U8 dly_ui, dly_ui_start, dly_ui_end; |
| 5523 | U8 pi_per_ui, ui_per_mck, freq_div; |
| 5524 | U8 pass_byte_count; |
| 5525 | //U32 value; |
| 5526 | //U8 dqs_i; |
| 5527 | U8 u1GatingErrorFlag=0; |
| 5528 | |
| 5529 | if (p == NULL) { |
| 5530 | mcSHOW_ERR_MSG(("[Error] Context NULL\n")); |
| 5531 | return DRAM_FAIL; |
| 5532 | } |
| 5533 | |
| 5534 | memset(&rxdqs_cal, 0, sizeof(struct rxdqs_gating_cal)); |
| 5535 | memset(&rxdqs_trans, 0, sizeof(struct rxdqs_gating_trans)); |
| 5536 | memset(&rxdqs_best_win, 0, sizeof(struct rxdqs_gating_best_win)); |
| 5537 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5538 | pi_per_ui = DQS_GW_PI_PER_UI; |
| 5539 | ui_per_mck = DQS_GW_UI_PER_MCK; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5540 | if (vGet_Div_Mode(p) == DIV4_MODE) |
| 5541 | freq_div = 2; |
| 5542 | else |
| 5543 | freq_div = 4; |
| 5544 | |
| 5545 | if (u1IsPhaseMode(p)) |
| 5546 | rxdqs_cal.dqsien_pi_adj_step = (0x1 << 4); |
| 5547 | else |
| 5548 | rxdqs_cal.dqsien_pi_adj_step = DQS_GW_FINE_STEP; |
| 5549 | |
| 5550 | #if ENABLE_GATING_AUTOK_WA |
| 5551 | if (__wa__gating_swk_for_autok) |
| 5552 | rxdqs_cal.dqsien_pi_adj_step = pi_per_ui; |
| 5553 | #endif |
| 5554 | rxdqs_cal.dqsien_pi_per_ui = pi_per_ui; |
| 5555 | rxdqs_cal.dqsien_ui_per_mck = ui_per_mck; |
| 5556 | rxdqs_cal.dqsien_freq_div = freq_div; |
| 5557 | |
| 5558 | U32 reg_backup_address[ ] = { |
| 5559 | (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)), |
| 5560 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)), |
| 5561 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)), |
| 5562 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)), |
| 5563 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), |
| 5564 | }; |
| 5565 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5566 | DramcBackupRegisters(p, reg_backup_address, |
| 5567 | sizeof (reg_backup_address) / sizeof (U32)); |
| 5568 | |
| 5569 | if (!rxdqs_gating_bypass(p)) { |
| 5570 | rxdqs_gating_sw_cal_init(p, use_enhance_rdqs); |
| 5571 | |
| 5572 | #if 1 |
| 5573 | #if (LP5_DDR4266_RDBI_WORKAROUND) |
| 5574 | if((is_lp5_family(p)) && (p->frequency == 2133)) |
| 5575 | dly_ui_start = 15; |
| 5576 | else if((is_lp5_family(p)) && (p->frequency == 2750)) |
| 5577 | dly_ui_start = 12; |
| 5578 | else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5579 | dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5580 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5581 | dly_ui_start = u1GetGatingStartPos(p, AUTOK_OFF); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5582 | #endif |
| 5583 | |
| 5584 | dly_ui_end = dly_ui_start+ 32; |
| 5585 | pass_byte_count = 0; |
| 5586 | #else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5587 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5588 | dly_ui_start = 9; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5589 | if(p->freq_sel==LP4_DDR4266) |
| 5590 | { |
| 5591 | dly_ui_start = 16; |
| 5592 | } |
| 5593 | dly_ui_end = dly_ui_start + 32; |
| 5594 | pass_byte_count = 0; |
| 5595 | } |
| 5596 | #endif |
| 5597 | |
| 5598 | |
| 5599 | for (dly_ui = dly_ui_start; dly_ui < dly_ui_end; |
| 5600 | dly_ui += DQS_GW_COARSE_STEP) { |
| 5601 | rxdqs_gating_set_dqsien_dly(p, dly_ui, &rxdqs_cal); |
| 5602 | |
| 5603 | for (rxdqs_cal.dqsien_dly_pi = 0; rxdqs_cal.dqsien_dly_pi < |
| 5604 | pi_per_ui; rxdqs_cal.dqsien_dly_pi += |
| 5605 | rxdqs_cal.dqsien_pi_adj_step) { |
| 5606 | dly_ui = rxdqs_gating_sw_cal(p, &rxdqs_trans, &rxdqs_cal, |
| 5607 | &pass_byte_count, &rxdqs_best_win, dly_ui, dly_ui_end); |
| 5608 | |
| 5609 | if (dly_ui == dly_ui_end) |
| 5610 | break; |
| 5611 | } |
| 5612 | } |
| 5613 | |
| 5614 | DramcEngine2End(p); |
| 5615 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5616 | |
| 5617 | if (pass_byte_count == 0x3) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5618 | { |
| 5619 | u1GatingErrorFlag=0; |
| 5620 | vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_OK); |
| 5621 | } |
| 5622 | else |
| 5623 | { |
| 5624 | u1GatingErrorFlag=1; |
| 5625 | mcSHOW_ERR_MSG(("error, no all pass taps in DQS!,pass_byte_count=%d\n", pass_byte_count)); |
| 5626 | } |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 5627 | (void)u1GatingErrorFlag; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5628 | |
| 5629 | |
| 5630 | #if (ENABLE_GATING_AUTOK_WA) |
| 5631 | if (!u1GatingErrorFlag && __wa__gating_swk_for_autok) { |
| 5632 | U8 ui[DQS_BYTE_NUMBER], ui_min = 0xff; |
| 5633 | U8 dqs_i; |
| 5634 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++){ |
| 5635 | ui[dqs_i] = rxdqs_best_win.best_dqsien_dly_mck[dqs_i] * ui_per_mck + |
| 5636 | rxdqs_best_win.best_dqsien_dly_ui[dqs_i]; |
| 5637 | |
| 5638 | if (ui[dqs_i] < ui_min) |
| 5639 | ui_min = ui[dqs_i]; |
| 5640 | } |
| 5641 | __wa__gating_autok_init_ui[p->rank] = ui_min; |
| 5642 | |
| 5643 | DramcRestoreRegisters(p, reg_backup_address, |
| 5644 | sizeof (reg_backup_address) / sizeof (U32)); |
| 5645 | return DRAM_OK; |
| 5646 | } |
| 5647 | #endif |
| 5648 | } |
| 5649 | |
| 5650 | rxdqs_gating_fastk_save_restore(p, &rxdqs_best_win, &rxdqs_cal); |
| 5651 | rxdqs_gating_misc_process(p, &rxdqs_best_win); |
| 5652 | |
| 5653 | mcSHOW_DBG_MSG4(("[Gating] SW calibration Done\n")); |
| 5654 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5655 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5656 | rxdqs_gating_set_final_result(p, ui_per_mck, &rxdqs_best_win); |
| 5657 | |
| 5658 | DramcRestoreRegisters(p, reg_backup_address, |
| 5659 | sizeof (reg_backup_address) / sizeof (U32)); |
| 5660 | |
| 5661 | DramPhyReset(p); |
| 5662 | |
| 5663 | return DRAM_OK; |
| 5664 | } |
| 5665 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5666 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5667 | DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, |
| 5668 | u8 autok, U8 use_enhanced_rdqs) |
| 5669 | { |
| 5670 | DRAM_STATUS_T ret; |
| 5671 | |
| 5672 | vPrintCalibrationBasicInfo(p); |
| 5673 | |
| 5674 | mcSHOW_DBG_MSG(("[DramcGating] \n")); |
| 5675 | |
| 5676 | #if ENABLE_GATING_AUTOK_WA |
| 5677 | if (autok) { |
| 5678 | __wa__gating_swk_for_autok = 1; |
| 5679 | dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs); |
| 5680 | __wa__gating_swk_for_autok = 0; |
| 5681 | } |
| 5682 | #endif |
| 5683 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5684 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5685 | vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAIL); |
| 5686 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5687 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5688 | #if GATING_AUTO_K_SUPPORT |
| 5689 | if (autok) { |
| 5690 | #if ENABLE_GATING_AUTOK_WA |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5691 | if (rxdqs_gating_bypass(p)) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5692 | return DRAM_OK; |
| 5693 | #endif |
| 5694 | |
| 5695 | ret = dramc_rx_dqs_gating_auto_cal(p); |
| 5696 | if (ret == DRAM_OK) { |
| 5697 | return DRAM_OK; |
| 5698 | } |
| 5699 | |
| 5700 | mcSHOW_ERR_MSG(("[Error] Gating auto calibration fail!!\n")); |
| 5701 | } |
| 5702 | #endif |
| 5703 | |
| 5704 | mcSHOW_DBG_MSG(("SW mode calibration\n")); |
| 5705 | |
| 5706 | return dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs); |
| 5707 | } |
| 5708 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5709 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5710 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 5711 | void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p) |
| 5712 | { |
| 5713 | U8 dqs_i; //u1RankRxDVS = 0 |
| 5714 | U8 u1RankIdx, u1RankMax; //u1RankBak |
| 5715 | S8 s1ChangeDQSINCTL; |
| 5716 | #if XRTRTR_NEW_CROSS_RK_MODE |
| 5717 | U16 u2PHSINCTL = 0; |
| 5718 | U32 u4Rank_Sel_MCK_P0[2], u4Rank_Sel_MCK_P1[2], u4RANKINCTL_STB; |
| 5719 | #endif |
| 5720 | #if RDSEL_TRACKING_EN |
| 5721 | //U32 u4PI_value[2] = {0}; |
| 5722 | #endif |
| 5723 | U32 backup_rank; |
| 5724 | U32 u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R, reg_TX_dly_DQSgated_min = 0; |
| 5725 | //U32 u4ReadRODT, u4ReadTXDLY[RANK_MAX][DQS_BYTE_NUMBER], u4ReadTXDLY_P1[RANK_MAX][DQS_BYTE_NUMBER] |
| 5726 | U8 mck2ui_shift; |
| 5727 | |
| 5728 | backup_rank = u1GetRank(p); |
| 5729 | |
| 5730 | #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY |
| 5731 | if (vGet_Div_Mode(p) == DIV8_MODE) |
| 5732 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5733 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5734 | if (p->frequency >= 1333) |
| 5735 | { |
| 5736 | reg_TX_dly_DQSgated_min = 2; |
| 5737 | } |
| 5738 | else |
| 5739 | { |
| 5740 | reg_TX_dly_DQSgated_min = 1; |
| 5741 | } |
| 5742 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5743 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5744 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5745 | reg_TX_dly_DQSgated_min = 1; |
| 5746 | } |
| 5747 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5748 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5749 | if (p->frequency >= 1333) |
| 5750 | { |
| 5751 | reg_TX_dly_DQSgated_min = 3; |
| 5752 | } |
| 5753 | else |
| 5754 | { |
| 5755 | reg_TX_dly_DQSgated_min = 2; |
| 5756 | } |
| 5757 | #endif |
| 5758 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5759 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5760 | #if 0 |
| 5761 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ7), u1RankRxDVS, SHU_B0_DQ7_R_DMRANKRXDVS_B0); |
| 5762 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B1_DQ7), u1RankRxDVS, SHU_B1_DQ7_R_DMRANKRXDVS_B1); |
| 5763 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5764 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5765 | |
| 5766 | s1ChangeDQSINCTL = reg_TX_dly_DQSgated_min - u1TXDLY_Cal_min; |
| 5767 | |
| 5768 | //mcDUMP_REG_MSG(("\n[dumpRG] RxdqsGatingPostProcess\n")); |
| 5769 | |
| 5770 | mcSHOW_DBG_MSG(("[RxdqsGatingPostProcess] freq %d\n" |
| 5771 | "ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n", |
| 5772 | p->frequency, |
| 5773 | s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min)); |
| 5774 | /*mcDUMP_REG_MSG(("[RxdqsGatingPostProcess] freq %d\n" |
| 5775 | "ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n", |
| 5776 | p->frequency, |
| 5777 | s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min));*/ |
| 5778 | |
| 5779 | if (vGet_Div_Mode(p) == DIV16_MODE) |
| 5780 | mck2ui_shift = 4; |
| 5781 | else if (vGet_Div_Mode(p) == DIV8_MODE) |
| 5782 | mck2ui_shift = 3; |
| 5783 | else |
| 5784 | mck2ui_shift = 2; |
| 5785 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5786 | if (s1ChangeDQSINCTL != 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5787 | { |
| 5788 | u1TXDLY_Cal_min += s1ChangeDQSINCTL; |
| 5789 | u1TXDLY_Cal_max += s1ChangeDQSINCTL; |
| 5790 | |
| 5791 | if (p->support_rank_num == RANK_DUAL) |
| 5792 | u1RankMax = RANK_MAX; |
| 5793 | else |
| 5794 | u1RankMax = RANK_1; |
| 5795 | |
| 5796 | for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) |
| 5797 | { |
| 5798 | mcSHOW_DBG_MSG2(("Rank: %d\n", u1RankIdx)); |
| 5799 | //mcDUMP_REG_MSG(("Rank: %d\n", u1RankIdx)); |
| 5800 | |
| 5801 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) |
| 5802 | { |
| 5803 | #if 1 |
| 5804 | U8 total_ui, total_ui_P1; |
| 5805 | total_ui = (ucbest_coarse_mck_backup[u1RankIdx][dqs_i] << 4) + ucbest_coarse_ui_backup[u1RankIdx][dqs_i]; |
| 5806 | total_ui_P1 = (ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] << 4) + ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]; |
| 5807 | |
| 5808 | total_ui += (s1ChangeDQSINCTL << mck2ui_shift); |
| 5809 | total_ui_P1 += (s1ChangeDQSINCTL << mck2ui_shift); |
| 5810 | |
| 5811 | ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = (total_ui >> 4); |
| 5812 | ucbest_coarse_ui_backup[u1RankIdx][dqs_i] = total_ui & 0xf; |
| 5813 | |
| 5814 | ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = (total_ui_P1 >> 4); |
| 5815 | ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] = total_ui_P1 & 0xf; |
| 5816 | #else |
| 5817 | if (vGet_Div_Mode(p) == DIV8_MODE) |
| 5818 | { |
| 5819 | u4ReadTXDLY[u1RankIdx][dqs_i] = ucbest_coarse_mck_backup[u1RankIdx][dqs_i]; |
| 5820 | u4ReadTXDLY_P1[u1RankIdx][dqs_i] = ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i]; |
| 5821 | |
| 5822 | u4ReadTXDLY[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; |
| 5823 | u4ReadTXDLY_P1[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; |
| 5824 | |
| 5825 | ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = u4ReadTXDLY[u1RankIdx][dqs_i]; |
| 5826 | ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = u4ReadTXDLY_P1[u1RankIdx][dqs_i]; |
| 5827 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5828 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5829 | { |
| 5830 | u4ReadTXDLY[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_backup[u1RankIdx][dqs_i] >> 2) & 0x1)); |
| 5831 | u4ReadTXDLY_P1[u1RankIdx][dqs_i] = ((ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] << 1) + ((ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] >> 2) & 0x1)); |
| 5832 | |
| 5833 | u4ReadTXDLY[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; |
| 5834 | u4ReadTXDLY_P1[u1RankIdx][dqs_i] += s1ChangeDQSINCTL; |
| 5835 | |
| 5836 | ucbest_coarse_mck_backup[u1RankIdx][dqs_i] = (u4ReadTXDLY[u1RankIdx][dqs_i] >> 1); |
| 5837 | ucbest_coarse_ui_backup[u1RankIdx][dqs_i] = ((u4ReadTXDLY[u1RankIdx][dqs_i] & 0x1) << 2) + (ucbest_coarse_ui_backup[u1RankIdx][dqs_i] & 0x3); |
| 5838 | |
| 5839 | ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i] = (u4ReadTXDLY_P1[u1RankIdx][dqs_i] >> 1); |
| 5840 | ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] = ((u4ReadTXDLY_P1[u1RankIdx][dqs_i] & 0x1) << 2) + (ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] & 0x3); |
| 5841 | } |
| 5842 | #endif |
| 5843 | mcSHOW_DBG_MSG(("PostProcess best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i])); |
| 5844 | //mcDUMP_REG_MSG(("PostProcess best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i])); |
| 5845 | #ifdef FOR_HQA_REPORT_USED |
| 5846 | HQA_Log_Message_for_Report(p, p->channel, u1RankIdx, HQA_REPORT_FORMAT0, |
| 5847 | "Gating_Center_", "2T", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], NULL); |
| 5848 | HQA_Log_Message_for_Report(p, p->channel, u1RankIdx, HQA_REPORT_FORMAT0, |
| 5849 | "Gating_Center_", "05T", dqs_i, ucbest_coarse_ui_backup[u1RankIdx][dqs_i], NULL); |
| 5850 | #endif |
| 5851 | } |
| 5852 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) |
| 5853 | { |
| 5854 | mcSHOW_DBG_MSG(("PostProcess best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i])); |
| 5855 | //mcDUMP_REG_MSG(("PostProcess best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i])); |
| 5856 | } |
| 5857 | } |
| 5858 | |
| 5859 | for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++) |
| 5860 | { |
| 5861 | vSetRank(p, u1RankIdx); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5862 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5863 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY), |
| 5864 | P_Fld(ucbest_coarse_mck_backup[u1RankIdx][0], |
| 5865 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0) | |
| 5866 | P_Fld(ucbest_coarse_ui_backup[u1RankIdx][0], |
| 5867 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0) | |
| 5868 | P_Fld(ucbest_coarse_mck_P1_backup[u1RankIdx][0], |
| 5869 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0) | |
| 5870 | P_Fld(ucbest_coarse_ui_P1_backup[u1RankIdx][0], |
| 5871 | SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0)); |
| 5872 | |
| 5873 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY), |
| 5874 | P_Fld(ucbest_coarse_mck_backup[u1RankIdx][1], |
| 5875 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1) | |
| 5876 | P_Fld(ucbest_coarse_ui_backup[u1RankIdx][1], |
| 5877 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1) | |
| 5878 | P_Fld(ucbest_coarse_mck_P1_backup[u1RankIdx][1], |
| 5879 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1) | |
| 5880 | P_Fld(ucbest_coarse_ui_P1_backup[u1RankIdx][1], |
| 5881 | SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1)); |
| 5882 | #if RDSEL_TRACKING_EN |
| 5883 | if(p->frequency >= RDSEL_TRACKING_TH) |
| 5884 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5885 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5886 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI), |
| 5887 | (ucbest_coarse_mck_backup[u1RankIdx][0] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][0]), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5888 | SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0); |
| 5889 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5890 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI), |
| 5891 | (ucbest_coarse_mck_backup[u1RankIdx][1] << 4) | (ucbest_coarse_ui_backup[u1RankIdx][1]), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5892 | SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5893 | } |
| 5894 | #endif |
| 5895 | } |
| 5896 | } |
| 5897 | vSetRank(p, backup_rank); |
| 5898 | |
| 5899 | u4ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), |
| 5900 | MISC_SHU_RK_DQSCTL_DQSINCTL); |
| 5901 | //mcDUMP_REG_MSG(("u4ReadDQSINCTL=%d\n", u4ReadDQSINCTL)); |
| 5902 | u4ReadDQSINCTL -= s1ChangeDQSINCTL; |
| 5903 | |
| 5904 | #if ENABLE_READ_DBI |
| 5905 | if (p->DBI_R_onoff[p->dram_fsp]) |
| 5906 | { |
| 5907 | u4ReadDQSINCTL++; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5908 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5909 | u4ReadRODT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_RODT); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5910 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), u4ReadRODT + 1, SHU_ODTCTRL_RODT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5911 | #endif |
| 5912 | } |
| 5913 | #endif |
| 5914 | |
| 5915 | #if XRTRTR_NEW_CROSS_RK_MODE |
| 5916 | for (dqs_i = 0; dqs_i < DQS_BYTE_NUMBER; dqs_i++) |
| 5917 | { |
| 5918 | if (ucbest_coarse_mck_backup[RANK_0][dqs_i] > ucbest_coarse_mck_backup[RANK_1][dqs_i]) |
| 5919 | { |
| 5920 | u4Rank_Sel_MCK_P0[dqs_i] = (ucbest_coarse_mck_backup[RANK_0][dqs_i] > 0)? (ucbest_coarse_mck_backup[RANK_0][dqs_i] - 1): 0; |
| 5921 | u4Rank_Sel_MCK_P1[dqs_i] = (ucbest_coarse_mck_P1_backup[RANK_0][dqs_i] > 0)? (ucbest_coarse_mck_P1_backup[RANK_0][dqs_i] - 1): 0; |
| 5922 | } |
| 5923 | else |
| 5924 | { |
| 5925 | u4Rank_Sel_MCK_P0[dqs_i] = (ucbest_coarse_mck_backup[RANK_1][dqs_i] > 0)? (ucbest_coarse_mck_backup[RANK_1][dqs_i] - 1): 0; |
| 5926 | u4Rank_Sel_MCK_P1[dqs_i] = (ucbest_coarse_mck_P1_backup[RANK_1][dqs_i] > 0)? (ucbest_coarse_mck_P1_backup[RANK_1][dqs_i] - 1): 0; |
| 5927 | } |
| 5928 | } |
| 5929 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY), |
| 5930 | P_Fld(u4Rank_Sel_MCK_P0[0], SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0) | |
| 5931 | P_Fld(u4Rank_Sel_MCK_P1[0], SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0)); |
| 5932 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY), |
| 5933 | P_Fld(u4Rank_Sel_MCK_P0[1], SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1) | |
| 5934 | P_Fld(u4Rank_Sel_MCK_P1[1], SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1)); |
| 5935 | |
| 5936 | u4RANKINCTL_STB = (u4ReadDQSINCTL > 2)? (u4ReadDQSINCTL - 2): 0; |
| 5937 | u2PHSINCTL = (u4ReadDQSINCTL == 0)? 0: (u4ReadDQSINCTL - 1); |
| 5938 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), u4RANKINCTL_STB, MISC_SHU_RANKCTL_RANKINCTL_STB); |
| 5939 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RANK_SEL_STB), u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL); |
| 5940 | #endif |
| 5941 | |
| 5942 | #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5943 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5944 | if (u4ReadDQSINCTL >= 2) |
| 5945 | { |
| 5946 | u4RankINCTL_ROOT = u4ReadDQSINCTL - 2; |
| 5947 | } |
| 5948 | else |
| 5949 | { |
| 5950 | u4RankINCTL_ROOT = 0; |
| 5951 | mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n")); |
| 5952 | #if (__ETT__) |
| 5953 | while (1); |
| 5954 | #endif |
| 5955 | } |
| 5956 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5957 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5958 | if (u4ReadDQSINCTL >= 3) |
| 5959 | { |
| 5960 | u4RankINCTL_ROOT = u4ReadDQSINCTL - 3; |
| 5961 | } |
| 5962 | else |
| 5963 | { |
| 5964 | u4RankINCTL_ROOT = 0; |
| 5965 | mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <3, Risk for supporting 1066/RL8\n")); |
| 5966 | } |
| 5967 | #endif |
| 5968 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5969 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5970 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5971 | u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5972 | vSetRank(p, RANK_1); |
| 5973 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5974 | u4ReadDQSINCTL, MISC_SHU_RK_DQSCTL_DQSINCTL); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5975 | vSetRank(p, backup_rank); |
| 5976 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5977 | |
| 5978 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5979 | u4ReadDQSINCTL, MISC_SHU_RANKCTL_RANKINCTL_PHY); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5980 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5981 | u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5982 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5983 | u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5984 | |
| 5985 | #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY |
| 5986 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), |
| 5987 | u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_RXDLY); |
| 5988 | |
| 5989 | u4XRTR2R = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), SHU_ACTIM_XRT_XRTR2R); |
| 5990 | |
| 5991 | mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL)); |
| 5992 | mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); |
| 5993 | //mcDUMP_REG_MSG(("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL)); |
| 5994 | //mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); |
| 5995 | #else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5996 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 5997 | |
| 5998 | u4XRTR2R = 8 + u1TXDLY_Cal_max + 1; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 5999 | if (u4XRTR2R > 12) |
| 6000 | { |
| 6001 | u4XRTR2R = 12; |
| 6002 | mcSHOW_ERR_MSG(("XRTR2R > 12, Max value is 12\n")); |
| 6003 | } |
| 6004 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), u4XRTR2R, SHU_ACTIM_XRT_XRTR2R); |
| 6005 | |
| 6006 | mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL)); |
| 6007 | mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); |
| 6008 | //mcDUMP_REG_MSG(("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL)); |
| 6009 | //mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R)); |
| 6010 | #endif |
| 6011 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6012 | #if 0 |
| 6013 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6014 | U8 u1ReadROEN; |
| 6015 | u1ReadROEN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ODTCTRL), SHU_ODTCTRL_ROEN); |
| 6016 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RODTENSTB), P_Fld(0xff, SHU_RODTENSTB_RODTENSTB_EXT) | \ |
| 6017 | P_Fld(u1ReadROEN, SHU_RODTENSTB_RODTENSTB_TRACK_EN)); |
| 6018 | #endif |
| 6019 | |
| 6020 | #ifdef XRTR2W_PERFORM_ENHANCE_RODTEN |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6021 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6022 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), |
| 6023 | P_Fld(0x0fff, MISC_SHU_RODTENSTB_RODTENSTB_EXT) | |
| 6024 | P_Fld(1, MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE) | |
| 6025 | P_Fld(1, MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN)); |
| 6026 | #endif |
| 6027 | |
| 6028 | vSetRank(p, backup_rank); |
| 6029 | |
| 6030 | |
| 6031 | } |
| 6032 | #endif |
| 6033 | |
| 6034 | #if GATING_ADJUST_TXDLY_FOR_TRACKING |
| 6035 | void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p) |
| 6036 | { |
| 6037 | u1TXDLY_Cal_min = 0xff; |
| 6038 | u1TXDLY_Cal_max = 0; |
| 6039 | } |
| 6040 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6041 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6042 | |
| 6043 | #endif |
| 6044 | |
| 6045 | #if RDSEL_TRACKING_EN |
| 6046 | void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p) |
| 6047 | { |
| 6048 | S32 s4PosVH, s4NegVH; |
| 6049 | |
| 6050 | s4PosVH = divRoundClosest(400, ((1000000 / p->frequency) / 64)); |
| 6051 | s4NegVH = 1; |
| 6052 | |
| 6053 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RDSEL_TRACK), P_Fld(s4PosVH, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS) |
| 6054 | | P_Fld(s4NegVH, SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG)); |
| 6055 | } |
| 6056 | #endif |
| 6057 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6058 | #if RDDQC_PINMUX_WORKAROUND |
| 6059 | static void RDDQCPinmuxWorkaround(DRAMC_CTX_T *p) |
| 6060 | { |
| 6061 | U8 *uiLPDDR_RDDQC_Mapping; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6062 | const U8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_NUM][16] = |
| 6063 | { |
| 6064 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6065 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6066 | { |
| 6067 | 0, 1, 2, 3, 7, 4, 6, 5, |
| 6068 | 9, 8, 12, 14, 15, 10, 13, 11 |
| 6069 | }, |
| 6070 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6071 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6072 | { |
| 6073 | 0, 1, 7, 4, 3, 2, 6, 5, |
| 6074 | 9, 8, 12, 14, 15, 10, 11, 13 |
| 6075 | }, |
| 6076 | #endif |
| 6077 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6078 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6079 | { |
| 6080 | 0, 1, 2, 3, 7, 4, 6, 5, |
| 6081 | 9, 8, 12, 14, 15, 10, 13, 11 |
| 6082 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6083 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6084 | { |
| 6085 | 0, 1, 7, 4, 3, 2, 6, 5, |
| 6086 | 9, 8, 12, 14, 15, 10, 11, 13 |
| 6087 | }, |
| 6088 | #endif |
| 6089 | }, |
| 6090 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6091 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6092 | { |
| 6093 | 0, 1, 4, 3, 2, 5, 7, 6, |
| 6094 | 9, 8, 10, 11, 15, 13, 12, 14 |
| 6095 | }, |
| 6096 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6097 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6098 | { |
| 6099 | 0, 1, 2, 5, 3, 4, 7, 6, |
| 6100 | 8, 9, 10, 11, 15, 14, 13, 12 |
| 6101 | }, |
| 6102 | #endif |
| 6103 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6104 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6105 | { |
| 6106 | 0, 1, 2, 3, 4, 5, 6, 7, |
| 6107 | 8, 9, 10, 11, 12, 13, 14, 15 |
| 6108 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6109 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6110 | { |
| 6111 | 0, 1, 2, 3, 4, 5, 6, 7, |
| 6112 | 8, 9, 10, 11, 12, 13, 14, 15 |
| 6113 | }, |
| 6114 | #endif |
| 6115 | }, |
| 6116 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6117 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6118 | { |
| 6119 | 0, 1, 6, 2, 4, 7, 3, 5, |
| 6120 | 8, 9, 10, 12, 13, 11, 15, 14 |
| 6121 | }, |
| 6122 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6123 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6124 | { |
| 6125 | 0, 1, 7, 4, 2, 5, 6, 3, |
| 6126 | 9, 8, 10, 12, 11, 14, 13, 15 |
| 6127 | }, |
| 6128 | #endif |
| 6129 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6130 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6131 | { |
| 6132 | 1, 0, 3, 2, 4, 7, 6, 5, |
| 6133 | 8, 9, 10, 12, 15, 14, 11, 13 |
| 6134 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6135 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6136 | { |
| 6137 | 0, 1, 7, 4, 2, 5, 6, 3, |
| 6138 | 9, 8, 10, 12, 11, 14, 13, 15 |
| 6139 | }, |
| 6140 | #endif |
| 6141 | }, |
| 6142 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6143 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6144 | { |
| 6145 | 8, 9, 14, 15, 12, 13, 11, 10, |
| 6146 | 1, 0, 3, 2, 7, 6, 4, 5 |
| 6147 | }, |
| 6148 | #if (CHANNEL_NUM>1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6149 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6150 | { |
| 6151 | 9, 8, 13, 12, 15, 10, 11, 14, |
| 6152 | 0, 1, 3, 2, 4, 6, 5, 7 |
| 6153 | }, |
| 6154 | #endif |
| 6155 | #if (CHANNEL_NUM>2) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6156 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6157 | { |
| 6158 | 0, 1, 6, 7, 4, 5, 3, 2, |
| 6159 | 9, 8, 11, 10, 15, 14, 12, 13 |
| 6160 | }, |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6161 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6162 | { |
| 6163 | 1, 0, 5, 4, 7, 2, 3, 6, |
| 6164 | 8, 9, 11, 10, 12, 14, 13, 15 |
| 6165 | }, |
| 6166 | #endif |
| 6167 | } |
| 6168 | }; |
| 6169 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6170 | { |
| 6171 | uiLPDDR_RDDQC_Mapping = (U8 *)uiLPDDR4_RDDQC_Mapping_POP[p->DRAMPinmux][p->channel]; |
| 6172 | } |
| 6173 | |
| 6174 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6175 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6176 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1), P_Fld(uiLPDDR_RDDQC_Mapping[0], MRR_BIT_MUX1_MRR_BIT0_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[1], MRR_BIT_MUX1_MRR_BIT1_SEL) | |
| 6177 | P_Fld(uiLPDDR_RDDQC_Mapping[2], MRR_BIT_MUX1_MRR_BIT2_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[3], MRR_BIT_MUX1_MRR_BIT3_SEL)); |
| 6178 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2), P_Fld(uiLPDDR_RDDQC_Mapping[4], MRR_BIT_MUX2_MRR_BIT4_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[5], MRR_BIT_MUX2_MRR_BIT5_SEL) | |
| 6179 | P_Fld(uiLPDDR_RDDQC_Mapping[6], MRR_BIT_MUX2_MRR_BIT6_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[7], MRR_BIT_MUX2_MRR_BIT7_SEL)); |
| 6180 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3), P_Fld(uiLPDDR_RDDQC_Mapping[8], MRR_BIT_MUX3_MRR_BIT8_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[9], MRR_BIT_MUX3_MRR_BIT9_SEL) | |
| 6181 | P_Fld(uiLPDDR_RDDQC_Mapping[10], MRR_BIT_MUX3_MRR_BIT10_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[11], MRR_BIT_MUX3_MRR_BIT11_SEL)); |
| 6182 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4), P_Fld(uiLPDDR_RDDQC_Mapping[12], MRR_BIT_MUX4_MRR_BIT12_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[13], MRR_BIT_MUX4_MRR_BIT13_SEL) | |
| 6183 | P_Fld(uiLPDDR_RDDQC_Mapping[14], MRR_BIT_MUX4_MRR_BIT14_SEL) | P_Fld(uiLPDDR_RDDQC_Mapping[15], MRR_BIT_MUX4_MRR_BIT15_SEL)); |
| 6184 | |
| 6185 | } |
| 6186 | #endif |
| 6187 | |
| 6188 | #define RDDQCGOLDEN_LP5_MR30_BIT_CTRL_LOWER RDDQCGOLDEN_MR15_GOLDEN |
| 6189 | #define RDDQCGOLDEN_LP5_MR31_BIT_CTRL_UPPER RDDQCGOLDEN_MR20_GOLDEN |
| 6190 | #define RDDQCGOLDEN_LP5_MR32_PATTERN_A RDDQCGOLDEN_MR32_GOLDEN |
| 6191 | #define RDDQCGOLDEN_LP5_MR33_PATTERN_B RDDQCGOLDEN_MR40_GOLDEN |
| 6192 | static U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p) |
| 6193 | { |
| 6194 | //int i; |
| 6195 | //U8 *uiLPDDR_O1_Mapping; |
| 6196 | //U16 temp_value = 0; |
| 6197 | U8 RDDQC_Bit_Ctrl_Lower = 0x55; |
| 6198 | U8 RDDQC_Bit_Ctrl_Upper = 0x55; |
| 6199 | U8 RDDQC_Pattern_A = 0x5A; |
| 6200 | U8 RDDQC_Pattern_B = 0x3C; |
| 6201 | |
| 6202 | #if FOR_DV_SIMULATION_USED == 1 |
| 6203 | cal_sv_rand_args_t *psra = get_psra(); |
| 6204 | |
| 6205 | if (psra) { |
| 6206 | RDDQC_Bit_Ctrl_Lower = psra->low_byte_invert_golden & 0xFF; |
| 6207 | RDDQC_Bit_Ctrl_Upper = psra->upper_byte_invert_golden & 0xFF; |
| 6208 | RDDQC_Pattern_A = psra->mr_dq_a_golden; |
| 6209 | RDDQC_Pattern_B = psra->mr_dq_b_golden; |
| 6210 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6211 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6212 | } |
| 6213 | #endif |
| 6214 | |
| 6215 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6216 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), 0, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0); |
| 6217 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), 0, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1); |
| 6218 | |
| 6219 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK); |
| 6220 | |
| 6221 | #if RDDQC_PINMUX_WORKAROUND |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6222 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6223 | RDDQCPinmuxWorkaround(p); |
| 6224 | #endif |
| 6225 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6226 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6227 | { |
| 6228 | DramcModeRegWriteByRank(p, p->rank, 15, RDDQC_Bit_Ctrl_Lower); |
| 6229 | DramcModeRegWriteByRank(p, p->rank, 20, RDDQC_Bit_Ctrl_Upper); |
| 6230 | DramcModeRegWriteByRank(p, p->rank, 32, RDDQC_Pattern_A); |
| 6231 | DramcModeRegWriteByRank(p, p->rank, 40, RDDQC_Pattern_B); |
| 6232 | } |
| 6233 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6234 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6235 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RDDQCGOLDEN), |
| 6236 | P_Fld(RDDQC_Bit_Ctrl_Lower, RDDQCGOLDEN_LP5_MR30_BIT_CTRL_LOWER) | |
| 6237 | P_Fld(RDDQC_Bit_Ctrl_Upper, RDDQCGOLDEN_LP5_MR31_BIT_CTRL_UPPER) | |
| 6238 | P_Fld(RDDQC_Pattern_A, RDDQCGOLDEN_LP5_MR32_PATTERN_A) | |
| 6239 | P_Fld(RDDQC_Pattern_B, RDDQCGOLDEN_LP5_MR33_PATTERN_B)); |
| 6240 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6241 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6242 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), |
| 6243 | P_Fld(1, SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0)); |
| 6244 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8), |
| 6245 | P_Fld(1, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1)); |
| 6246 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6247 | return 0; |
| 6248 | } |
Ryan Chuang | 98affb6 | 2021-09-23 20:35:22 +0800 | [diff] [blame] | 6249 | #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6250 | static U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p) |
| 6251 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6252 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6253 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRSRK); |
| 6254 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6255 | return 0; |
| 6256 | } |
| 6257 | #endif |
| 6258 | static void SetRxVref(DRAMC_CTX_T *p, U8 u1Vref_B0, U8 u1Vref_B1) |
| 6259 | { |
| 6260 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
| 6261 | |
| 6262 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), |
| 6263 | P_Fld(u1Vref_B0, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | |
| 6264 | P_Fld(u1Vref_B0, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0)); |
| 6265 | if (!isLP4_DSC) |
| 6266 | { |
| 6267 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL), |
| 6268 | P_Fld(u1Vref_B1, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1) | |
| 6269 | P_Fld(u1Vref_B1, SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1)); |
| 6270 | } |
| 6271 | else |
| 6272 | { |
| 6273 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL), |
| 6274 | P_Fld(u1Vref_B1, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB) | |
| 6275 | P_Fld(u1Vref_B1, SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB)); |
| 6276 | } |
| 6277 | } |
| 6278 | #if 0 |
| 6279 | static void SetRxDqDelay(DRAMC_CTX_T *p, U8 ii, S16 iDelay) |
| 6280 | { |
| 6281 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + (ii * 4)), |
| 6282 | P_Fld(iDelay, SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | |
| 6283 | P_Fld(iDelay, SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); |
| 6284 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + (ii * 4)), |
| 6285 | P_Fld(iDelay, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | |
| 6286 | P_Fld(iDelay, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); |
| 6287 | } |
| 6288 | |
| 6289 | static void SetRxDqDqsDelay(DRAMC_CTX_T *p, S16 iDelay) |
| 6290 | { |
| 6291 | U8 ii; //u1ByteIdx |
| 6292 | //U32 u4value; |
| 6293 | |
| 6294 | if (iDelay <= 0) |
| 6295 | { |
| 6296 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), (-iDelay), SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0); |
| 6297 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), (-iDelay), SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1); |
| 6298 | //DramPhyReset(p); |
| 6299 | } |
| 6300 | else |
| 6301 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6302 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6303 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), iDelay, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); |
| 6304 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), iDelay, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); |
| 6305 | //DramPhyReset(p); |
| 6306 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6307 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6308 | for (ii = 0; ii < 4; ii++) |
| 6309 | SetRxDqDelay(p, ii, iDelay); |
| 6310 | |
| 6311 | } |
| 6312 | } |
| 6313 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6314 | |
| 6315 | static U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p) |
| 6316 | { |
| 6317 | U32 u4Result = 0, u4TmpResult; |
| 6318 | DRAM_STATUS_T u4Response = DRAM_FAIL; |
| 6319 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6320 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6321 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1), 1, SWCMD_CTRL1_RDDQC_LP_ENB); |
| 6322 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6323 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6324 | REG_TRANSFER_T TriggerReg = {DRAMC_REG_SWCMD_EN, SWCMD_EN_RDDQCEN}; |
| 6325 | REG_TRANSFER_T RepondsReg = {DRAMC_REG_SPCMDRESP, SPCMDRESP_RDDQC_RESPONSE}; |
| 6326 | u4Response = DramcTriggerAndWait(p, TriggerReg, RepondsReg); |
| 6327 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6328 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6329 | u4TmpResult = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RDQC_CMP)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6330 | u4Result = (0xFFFF) & ((u4TmpResult) | (u4TmpResult >> 16)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6331 | |
| 6332 | #if (FEATURE_RDDQC_K_DMI == TRUE) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6333 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6334 | u4TmpResult = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP0_ERR); |
| 6335 | u4TmpResult |= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RDQC_DQM_CMP), RDQC_DQM_CMP_RDDQC_DQM_CMP1_ERR); |
| 6336 | u4Result |= (u4TmpResult << 16); |
| 6337 | #endif |
| 6338 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6339 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6340 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RDDQCEN); |
| 6341 | |
| 6342 | return u4Result; |
| 6343 | } |
| 6344 | #endif |
| 6345 | DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, |
| 6346 | RX_PATTERN_OPTION_T u1UseTestEngine, |
| 6347 | U8 *u1AssignedVref, |
| 6348 | U8 isAutoK, |
| 6349 | U8 K_Type) |
| 6350 | { |
| 6351 | U8 u1BitIdx, u1ByteIdx; //ii |
| 6352 | //U32 u1vrefidx; |
| 6353 | //U8 ucbit_first, ucbit_last; |
| 6354 | //S16 iDelay = 0, S16DelayBegin = 0, u4DelayStep=1; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 6355 | //u16DelayEnd = 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6356 | //U32 uiFinishCount; |
| 6357 | //U32 u4err_value, u4fail_bit, u4value; |
| 6358 | PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]; //WinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM] |
| 6359 | S32 iDQSDlyPerbyte[DQS_BYTE_NUMBER], iDQMDlyPerbyte[DQS_BYTE_NUMBER];//, iFinalDQSDly[DQS_NUMBER]; |
| 6360 | U8 u1VrefScanEnable = FALSE; |
| 6361 | //U16 u2TempWinSum[DQS_BYTE_NUMBER]={0}, u2rx_window_sum[DQS_BYTE_NUMBER]={0}, u2TmpDQMSum=0; |
| 6362 | U16 u2FinalVref [DQS_BYTE_NUMBER]= {0xe, 0xe}; //u2VrefLevel |
| 6363 | U16 u2VrefBegin, u2VrefEnd, u2VrefStep; |
| 6364 | //U32 u4fail_bit_R, u4fail_bit_F; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 6365 | U8 u1RXEyeScanEnable=(K_Type==NORMAL_K ? DISABLE : ENABLE); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6366 | //U16 u1min_bit_by_vref[DQS_BYTE_NUMBER], u1min_winsize_by_vref[DQS_BYTE_NUMBER]; |
| 6367 | //U16 u1min_bit[DQS_BYTE_NUMBER], u1min_winsize[DQS_BYTE_NUMBER]={0}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6368 | //U32 u4PassFlags = 0xFFFF; |
| 6369 | |
| 6370 | U16 backup_RX_FinalVref_Value[DQS_BYTE_NUMBER]={0}; |
| 6371 | U32 backup_DQS_Dly_Value[DQS_BYTE_NUMBER]={0}; |
| 6372 | U32 backup_DQM_Dly_Value[DQS_BYTE_NUMBER]={0}; |
| 6373 | U32 backup_DQ_Dly_Value[DQ_DATA_WIDTH]={0}; |
| 6374 | #if ENABLE_EYESCAN_GRAPH |
| 6375 | U8 EyeScan_index[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM] = {0}; |
| 6376 | U8 u1pass_in_this_vref_flag[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]; |
| 6377 | #endif |
| 6378 | |
| 6379 | U8 backup_rank, rank_i, u1KnownVref[2]={0xff, 0xff}; |
| 6380 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
| 6381 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6382 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6383 | if (!p) |
| 6384 | { |
| 6385 | mcSHOW_ERR_MSG(("context NULL\n")); |
| 6386 | return DRAM_FAIL; |
| 6387 | } |
| 6388 | |
| 6389 | |
| 6390 | U32 u4RegBackupAddress[] = |
| 6391 | { |
| 6392 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10)), |
| 6393 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10)), |
| 6394 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG0)), |
| 6395 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_AUTOK_CFG1)), |
| 6396 | #if RDDQC_PINMUX_WORKAROUND |
| 6397 | (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX1)), |
| 6398 | (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX2)), |
| 6399 | (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX3)), |
| 6400 | (DRAMC_REG_ADDR(DRAMC_REG_MRR_BIT_MUX4)), |
| 6401 | #endif |
| 6402 | }; |
| 6403 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6404 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6405 | DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); |
| 6406 | |
| 6407 | #if (FEATURE_RDDQC_K_DMI == TRUE) |
| 6408 | if (u1UseTestEngine == PATTERN_RDDQC) |
| 6409 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6410 | iDQMDlyPerbyte[0] = -0xFFFFFF; |
| 6411 | iDQMDlyPerbyte[1] = -0xFFFFFF; |
| 6412 | } |
| 6413 | else |
| 6414 | #endif |
| 6415 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6416 | iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); |
| 6417 | iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); |
| 6418 | |
| 6419 | } |
| 6420 | |
| 6421 | |
| 6422 | if (u1RXEyeScanEnable) |
| 6423 | { |
| 6424 | backup_RX_FinalVref_Value[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0); |
| 6425 | if (!isLP4_DSC) |
| 6426 | backup_RX_FinalVref_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_PHY_VREF_SEL), SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1); |
| 6427 | else |
| 6428 | backup_RX_FinalVref_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_PHY_VREF_SEL), SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB); |
| 6429 | |
| 6430 | backup_DQS_Dly_Value[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0); |
| 6431 | backup_DQS_Dly_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1); |
| 6432 | |
| 6433 | backup_DQM_Dly_Value[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); |
| 6434 | backup_DQM_Dly_Value[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); |
| 6435 | |
| 6436 | for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) |
| 6437 | { |
| 6438 | backup_DQ_Dly_Value[u1BitIdx ] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0); |
| 6439 | backup_DQ_Dly_Value[u1BitIdx+1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0); |
| 6440 | backup_DQ_Dly_Value[u1BitIdx+8] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1); |
| 6441 | backup_DQ_Dly_Value[u1BitIdx+9] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1); |
| 6442 | } |
| 6443 | |
| 6444 | #if ENABLE_EYESCAN_GRAPH |
| 6445 | if (u1UseTestEngine == PATTERN_TEST_ENGINE) |
| 6446 | { |
| 6447 | for(u1vrefidx=0; u1vrefidx<EYESCAN_RX_VREF_RANGE_END;u1vrefidx++) |
| 6448 | { |
| 6449 | for (u1BitIdx = 0; u1BitIdx < DQ_DATA_WIDTH; u1BitIdx++) |
| 6450 | { |
| 6451 | for(ii=0; ii<EYESCAN_BROKEN_NUM; ii++) |
| 6452 | { |
| 6453 | gEyeScan_Min[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; |
| 6454 | gEyeScan_Max[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; |
| 6455 | |
| 6456 | gEyeScan_ContinueVrefHeight[u1BitIdx] = 0; |
| 6457 | gEyeScan_TotalPassCount[u1BitIdx] = 0; |
| 6458 | } |
| 6459 | } |
| 6460 | } |
| 6461 | } |
| 6462 | #endif |
| 6463 | } |
| 6464 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6465 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6466 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10), 1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0); |
| 6467 | if (!isLP4_DSC) |
| 6468 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ10), 1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1); |
| 6469 | else |
| 6470 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD10), 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA); |
| 6471 | |
| 6472 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6473 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6474 | vAutoRefreshSwitch(p, DISABLE); |
| 6475 | //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 6476 | |
| 6477 | backup_rank = u1GetRank(p); |
| 6478 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6479 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6480 | if (u1UseTestEngine == PATTERN_TEST_ENGINE) |
| 6481 | { |
| 6482 | if (u1RXEyeScanEnable == DISABLE) |
| 6483 | { |
| 6484 | vSetCalibrationResult(p, DRAM_CALIBRATION_RX_PERBIT, DRAM_FAIL); |
| 6485 | } |
| 6486 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6487 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6488 | if (isAutoK == TRUE) |
| 6489 | { |
| 6490 | DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); |
| 6491 | } |
| 6492 | else |
| 6493 | { |
| 6494 | #if ENABLE_K_WITH_WORST_SI_UI_SHIFT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6495 | DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6496 | #else |
| 6497 | DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern, 0, TE_NO_UI_SHIFT); |
| 6498 | #endif |
| 6499 | } |
| 6500 | } |
| 6501 | else |
| 6502 | { |
| 6503 | if (u1RXEyeScanEnable == DISABLE) |
| 6504 | { |
| 6505 | vSetCalibrationResult(p, DRAM_CALIBRATION_RX_RDDQC, DRAM_FAIL); |
| 6506 | } |
| 6507 | DramcRxWinRDDQCInit(p); |
| 6508 | } |
| 6509 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6510 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6511 | u2VrefBegin = 0; |
| 6512 | u2VrefEnd = 0; |
| 6513 | u2VrefStep = 1; |
| 6514 | |
Arthur Heymans | 8d7eff3 | 2023-04-19 10:11:33 +0200 | [diff] [blame] | 6515 | if (u1UseTestEngine == PATTERN_TEST_ENGINE) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6516 | { |
| 6517 | #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) |
| 6518 | if ((p->rank==RANK_0) || (p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) || (u1RXEyeScanEnable==1)) |
| 6519 | u1VrefScanEnable =1; |
| 6520 | #else |
| 6521 | u1VrefScanEnable =0; |
| 6522 | #endif |
| 6523 | } |
| 6524 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6525 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 6526 | if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) |
| 6527 | { |
| 6528 | mcSHOW_DBG_MSG(("[FAST_K] Bypass RX Calibration\n")); |
| 6529 | } |
| 6530 | else |
| 6531 | #endif |
| 6532 | { |
| 6533 | |
| 6534 | //mcDUMP_REG_MSG(("\n[dumpRG] %s\n",u1UseTestEngine==PATTERN_RDDQC?"RDDQC":"DramcRxWindowPerbitCal")); |
| 6535 | #if VENDER_JV_LOG |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6536 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6537 | if (u1UseTestEngine == 1) |
| 6538 | vPrintCalibrationBasicInfo_ForJV(p); |
| 6539 | #endif |
| 6540 | #else |
| 6541 | vPrintCalibrationBasicInfo(p); |
| 6542 | #endif |
| 6543 | //mcSHOW_DBG_MSG2(("Start DQ dly to find pass range UseTestEngine =%d\n", u1UseTestEngine)); |
| 6544 | } |
| 6545 | |
| 6546 | mcSHOW_DBG_MSG(("[RxWindowPerbitCal] UseTestEngine: %s, RX Vref Scan: %d, Autok:%d\n", u1UseTestEngine==PATTERN_RDDQC?"RDDQC":"DramcRxWindowPerbitCal", u1VrefScanEnable, isAutoK)); |
| 6547 | |
| 6548 | if (u1VrefScanEnable) |
| 6549 | { |
| 6550 | if ((Get_Vref_Calibration_OnOff(p) == VREF_CALI_OFF) && (u1RXEyeScanEnable == 0)) |
| 6551 | { |
| 6552 | u2VrefBegin = 0; |
| 6553 | u2VrefEnd = 0; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6554 | u1KnownVref[0] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][0]; |
| 6555 | u1KnownVref[1] = gFinalRXVrefDQForSpeedUp[p->channel][p->rank][p->odt_onoff][1]; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6556 | |
| 6557 | if (u1UseTestEngine == PATTERN_TEST_ENGINE && ((u1KnownVref[0] == 0) || (u1KnownVref[1] == 0))) |
| 6558 | { |
| 6559 | // mcSHOW_ERR_MSG(("\nWrong frequency K order= %d\n")); |
| 6560 | #if __ETT__ |
| 6561 | while (1); |
| 6562 | #endif |
| 6563 | } |
| 6564 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6565 | else if (u1AssignedVref != NULL) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6566 | { |
| 6567 | u2VrefBegin = 0; |
| 6568 | u2VrefEnd = 0; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6569 | u1KnownVref[0] = u1AssignedVref[0]; |
| 6570 | u1KnownVref[1] = u1AssignedVref[1]; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6571 | } |
| 6572 | else |
| 6573 | { |
| 6574 | #if (SW_CHANGE_FOR_SIMULATION || FOR_DV_SIMULATION_USED) |
| 6575 | u2VrefBegin = RX_VREF_RANGE_BEGIN; |
| 6576 | #else |
| 6577 | if (u1RXEyeScanEnable == 0) |
| 6578 | { |
| 6579 | if (p->odt_onoff) |
| 6580 | { |
| 6581 | u2VrefBegin = RX_VREF_RANGE_BEGIN_ODT_ON; |
| 6582 | } |
| 6583 | else |
| 6584 | { |
| 6585 | u2VrefBegin = RX_VREF_RANGE_BEGIN_ODT_OFF; |
| 6586 | } |
| 6587 | u2VrefEnd = RX_VREF_RANGE_END-1; |
| 6588 | |
| 6589 | //mcSHOW_DBG_MSG(("\nSet Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd)); |
| 6590 | } |
| 6591 | else |
| 6592 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6593 | u2VrefBegin = 0; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 6594 | (void)u2VrefBegin; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6595 | u2VrefEnd = EYESCAN_RX_VREF_RANGE_END-1; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 6596 | (void)u2VrefEnd; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6597 | //mcSHOW_DBG_MSG(("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd)); |
| 6598 | } |
| 6599 | #endif |
| 6600 | } |
| 6601 | |
| 6602 | if (u1RXEyeScanEnable == 0) |
| 6603 | { |
| 6604 | u2VrefStep = RX_VREF_RANGE_STEP; |
| 6605 | } |
| 6606 | else |
| 6607 | { |
| 6608 | u2VrefStep = EYESCAN_GRAPH_RX_VREF_STEP; |
| 6609 | } |
| 6610 | |
| 6611 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); |
| 6612 | if (!isLP4_DSC) |
| 6613 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); |
| 6614 | else |
| 6615 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD5), 1, CA_CMD5_RG_RX_ARCMD_VREF_EN); |
| 6616 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6617 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6618 | { |
| 6619 | u2VrefBegin = 0; |
| 6620 | u2VrefEnd = 0; |
| 6621 | u2VrefStep = 1; |
| 6622 | } |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 6623 | (void)u2VrefStep; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6624 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6625 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6626 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 6627 | if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) |
| 6628 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6629 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6630 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 6631 | { |
| 6632 | if (u1VrefScanEnable) |
| 6633 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6634 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6635 | #if ( SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL) |
| 6636 | u2FinalVref[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbitVref_Save[p->channel][p->rank][u1ByteIdx]; |
| 6637 | #endif |
| 6638 | } |
| 6639 | |
| 6640 | iDQSDlyPerbyte[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbit_DQS[p->channel][p->rank][u1ByteIdx]; |
| 6641 | iDQMDlyPerbyte[u1ByteIdx] = p->pSavetimeData->u1RxWinPerbit_DQM[p->channel][p->rank][u1ByteIdx]; |
| 6642 | } |
| 6643 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6644 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6645 | for (u1BitIdx = 0; u1BitIdx < 16; u1BitIdx++) |
| 6646 | { |
| 6647 | FinalWinPerBit[u1BitIdx].best_dqdly = p->pSavetimeData->u1RxWinPerbit_DQ[p->channel][p->rank][u1BitIdx]; |
| 6648 | } |
| 6649 | |
| 6650 | if (u1RXEyeScanEnable == DISABLE) |
| 6651 | { |
| 6652 | if (u1UseTestEngine == PATTERN_TEST_ENGINE) |
| 6653 | vSetCalibrationResult(p, DRAM_CALIBRATION_RX_PERBIT, DRAM_FAST_K); |
| 6654 | else |
| 6655 | vSetCalibrationResult(p, DRAM_CALIBRATION_RX_RDDQC, DRAM_FAST_K); |
| 6656 | } |
| 6657 | } |
| 6658 | #endif |
| 6659 | if (u1RXEyeScanEnable) |
| 6660 | { |
| 6661 | u2FinalVref[0] = backup_RX_FinalVref_Value[0]; |
| 6662 | u2FinalVref[1] = backup_RX_FinalVref_Value[1]; |
| 6663 | |
| 6664 | iDQSDlyPerbyte[0] = backup_DQS_Dly_Value[0]; |
| 6665 | iDQSDlyPerbyte[1] = backup_DQS_Dly_Value[1]; |
| 6666 | |
| 6667 | iDQMDlyPerbyte[0] = backup_DQM_Dly_Value[0]; |
| 6668 | iDQMDlyPerbyte[1] = backup_DQM_Dly_Value[1]; |
| 6669 | |
| 6670 | for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) |
| 6671 | { |
| 6672 | FinalWinPerBit[u1BitIdx ].best_dqdly = backup_DQ_Dly_Value[u1BitIdx ]; |
| 6673 | FinalWinPerBit[u1BitIdx + 1].best_dqdly = backup_DQ_Dly_Value[u1BitIdx+1]; |
| 6674 | FinalWinPerBit[u1BitIdx + 8].best_dqdly = backup_DQ_Dly_Value[u1BitIdx+8]; |
| 6675 | FinalWinPerBit[u1BitIdx + 9].best_dqdly = backup_DQ_Dly_Value[u1BitIdx+9]; |
| 6676 | } |
| 6677 | } |
| 6678 | |
| 6679 | if (u1VrefScanEnable == TRUE) |
| 6680 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6681 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6682 | for (rank_i = p->rank; rank_i < p->support_rank_num; rank_i++) |
| 6683 | { |
| 6684 | vSetRank(p, rank_i); |
| 6685 | |
| 6686 | SetRxVref(p, u2FinalVref[0], u2FinalVref[1]); |
| 6687 | |
| 6688 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 6689 | { |
| 6690 | mcSHOW_DBG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i)); |
| 6691 | //mcDUMP_REG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i)); |
| 6692 | |
| 6693 | gFinalRXVrefDQ[p->channel][rank_i][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx]; |
| 6694 | gFinalRXVrefDQForSpeedUp[p->channel][rank_i][p->odt_onoff][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx]; |
| 6695 | } |
| 6696 | } |
| 6697 | vSetRank(p, backup_rank); |
| 6698 | } |
| 6699 | mcSHOW_DBG_MSG(("\n")); |
| 6700 | |
| 6701 | #if DUMP_TA2_WINDOW_SIZE_RX_TX |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6702 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6703 | if (u1UseTestEngine == PATTERN_TEST_ENGINE) |
| 6704 | { |
| 6705 | U32 u4B0Tatal =0; |
| 6706 | U32 u4B1Tatal =0; |
| 6707 | mcSHOW_DBG_MSG(("RX window per bit CH[%d] Rank[%d] window size\n", p->channel, p->rank)); |
| 6708 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 6709 | { |
| 6710 | mcSHOW_DBG_MSG(("DQ[%d] size = %d\n", u1BitIdx, gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx])); |
| 6711 | if(u1BitIdx < 8) |
| 6712 | { |
| 6713 | u4B0Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]; |
| 6714 | } |
| 6715 | else |
| 6716 | { |
| 6717 | u4B1Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]; |
| 6718 | } |
| 6719 | } |
| 6720 | mcSHOW_DBG_MSG(("total rx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal)); |
| 6721 | } |
| 6722 | #endif |
| 6723 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6724 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6725 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5), |
| 6726 | P_Fld((U32)iDQSDlyPerbyte[0], SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0)); |
| 6727 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), |
| 6728 | P_Fld((U32)iDQMDlyPerbyte[0], SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0)); |
| 6729 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5), |
| 6730 | P_Fld((U32)iDQSDlyPerbyte[1], SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1)); |
| 6731 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), |
| 6732 | P_Fld((U32)iDQMDlyPerbyte[1], SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1)); |
| 6733 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6734 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6735 | for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx += 2) |
| 6736 | { |
| 6737 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0 + u1BitIdx * 2), |
| 6738 | P_Fld(((U32)FinalWinPerBit[u1BitIdx].best_dqdly), SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0) | |
| 6739 | P_Fld(((U32)FinalWinPerBit[u1BitIdx + 1].best_dqdly), SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0)); |
| 6740 | |
| 6741 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0 + u1BitIdx * 2), |
| 6742 | P_Fld((U32)FinalWinPerBit[u1BitIdx + 8].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) | |
| 6743 | P_Fld((U32)FinalWinPerBit[u1BitIdx + 9].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1)); |
| 6744 | |
| 6745 | //mcSHOW_DBG_MSG(("u1BitId %d Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2, |
| 6746 | // FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly, FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly)); |
| 6747 | } |
| 6748 | |
| 6749 | DramPhyReset(p); |
| 6750 | |
| 6751 | #if RDDQC_PINMUX_WORKAROUND |
| 6752 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 6753 | #endif |
| 6754 | |
| 6755 | vSetRank(p, backup_rank); |
| 6756 | //vPrintCalibrationBasicInfo(p); |
| 6757 | |
| 6758 | #ifdef ETT_PRINT_FORMAT |
| 6759 | mcSHOW_DBG_MSG(("\nDQS Delay:\nDQS0 = %d, DQS1 = %d\n" |
| 6760 | "DQM Delay:\nDQM0 = %d, DQM1 = %d\n", |
| 6761 | iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], |
| 6762 | iDQMDlyPerbyte[0], iDQMDlyPerbyte[1])); |
| 6763 | /*mcDUMP_REG_MSG(("\nDQS Delay:\nDQS0 = %d, DQS1 = %d\n" |
| 6764 | "DQM Delay:\nDQM0 = %d, DQM1 = %d\n", |
| 6765 | iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], |
| 6766 | iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));*/ |
| 6767 | #else |
| 6768 | mcSHOW_DBG_MSG(("\nDQS Delay:\nDQS0 = %2d, DQS1 = %2d\n" |
| 6769 | "DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n", |
| 6770 | iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], |
| 6771 | iDQMDlyPerbyte[0], iDQMDlyPerbyte[1])); |
| 6772 | /*mcDUMP_REG_MSG(("\nDQS Delay:\nDQS0 = %2d, DQS1 = %2d\n" |
| 6773 | "DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n", |
| 6774 | iDQSDlyPerbyte[0], iDQSDlyPerbyte[1], |
| 6775 | iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));*/ |
| 6776 | #endif |
| 6777 | mcSHOW_DBG_MSG(("DQ Delay:\n")); |
| 6778 | //mcDUMP_REG_MSG(("DQ Delay:\n")); |
| 6779 | |
| 6780 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx = u1BitIdx + 4) |
| 6781 | { |
| 6782 | #ifdef ETT_PRINT_FORMAT |
| 6783 | mcSHOW_DBG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); |
| 6784 | //mcDUMP_REG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); |
| 6785 | #else |
| 6786 | mcSHOW_DBG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); |
| 6787 | //mcDUMP_REG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly)); |
| 6788 | #endif |
| 6789 | } |
| 6790 | mcSHOW_DBG_MSG(("\n")); |
| 6791 | mcSHOW_DBG_MSG4(("[DramcRxWindowPerbitCal] Done\n")); |
| 6792 | |
| 6793 | #if LP5_DDR4266_RDBI_WORKAROUND |
| 6794 | if((is_lp5_family(p)) && (p->frequency >= 2133)) |
| 6795 | { |
| 6796 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), 1, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0); |
| 6797 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), 1, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1); |
| 6798 | } |
| 6799 | #endif |
| 6800 | |
| 6801 | return DRAM_OK; |
| 6802 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6803 | } |
| 6804 | |
| 6805 | #if SIMULATION_RX_DVS |
| 6806 | static U8 DramcRxDVSCal(DRAMC_CTX_T *p, U8 u1byte) |
| 6807 | { |
| 6808 | U8 u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag, u1lead_lag; |
| 6809 | |
| 6810 | if (u1byte == 0) |
| 6811 | { |
| 6812 | u1rising_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B0); |
| 6813 | u1falling_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B0); |
| 6814 | u1rising_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0); |
| 6815 | u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0); |
| 6816 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6817 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6818 | { |
| 6819 | u1rising_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1); |
| 6820 | u1falling_lead = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1); |
| 6821 | u1rising_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS0), MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1); |
| 6822 | u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1); |
| 6823 | } |
| 6824 | |
| 6825 | mcSHOW_DBG_MSG2(("Byte%d | LEAD(%d %d) | LAG(%d %d)\n", u1byte, u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag)); |
| 6826 | |
| 6827 | u1lead_lag = (u1rising_lead | u1falling_lead | u1rising_lag | u1falling_lag); |
| 6828 | |
| 6829 | return u1lead_lag; |
| 6830 | } |
| 6831 | |
| 6832 | DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p) |
| 6833 | { |
| 6834 | U8 ii, u1ByteIdx; |
| 6835 | S16 iDelay = 0, S16DelayBegin = 0; |
| 6836 | U16 u16DelayEnd = 0, u16DelayStep = 1; |
| 6837 | U32 u4err_value; |
| 6838 | |
| 6839 | U8 u1lead_lag, u1DVS_first_flag[DQS_BYTE_NUMBER]={0}, u1DVS_first_pass[DQS_BYTE_NUMBER]={0}, u1DVS_pass_window[DQS_BYTE_NUMBER]={0}, u1finish_flag[DQS_BYTE_NUMBER]={0}; |
| 6840 | U32 u4RegBackupAddress[] = |
| 6841 | { |
| 6842 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)), |
| 6843 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)), |
| 6844 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY0)), |
| 6845 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY0)), |
| 6846 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY5)), |
| 6847 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY5)), |
| 6848 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4)), |
| 6849 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4)), |
| 6850 | }; |
| 6851 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6852 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6853 | if (!p) |
| 6854 | { |
| 6855 | mcSHOW_ERR_MSG(("context NULL\n")); |
| 6856 | return DRAM_FAIL; |
| 6857 | } |
| 6858 | |
| 6859 | mcSHOW_DBG_MSG(("[RX DVS calibration]\n")); |
| 6860 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6861 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6862 | vAutoRefreshSwitch(p, DISABLE); |
| 6863 | //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); |
| 6864 | |
| 6865 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0); |
| 6866 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1); |
| 6867 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6868 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6869 | #if ENABLE_K_WITH_WORST_SI_UI_SHIFT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6870 | DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6871 | #else |
| 6872 | DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); |
| 6873 | #endif |
| 6874 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6875 | { |
| 6876 | u16DelayStep = 4; |
| 6877 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6878 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6879 | S16DelayBegin = -80; |
| 6880 | u16DelayEnd = 100; |
| 6881 | |
| 6882 | mcSHOW_DBG_MSG2(("\nRX Delay %d -> %d, step: %d\n", S16DelayBegin, u16DelayEnd, u16DelayStep)); |
| 6883 | |
| 6884 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6885 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6886 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), |
| 6887 | P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0) | |
| 6888 | P_Fld(0, SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0)); |
| 6889 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), |
| 6890 | P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1) | |
| 6891 | P_Fld(0, SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1)); |
| 6892 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6893 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6894 | for (ii = 0; ii < 4; ii++) |
| 6895 | SetRxDqDelay(p, ii, 0); |
| 6896 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6897 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6898 | for (iDelay = S16DelayBegin; iDelay <= u16DelayEnd; iDelay += u16DelayStep) |
| 6899 | { |
| 6900 | SetRxDqDqsDelay(p, iDelay); |
| 6901 | |
| 6902 | u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); |
| 6903 | |
| 6904 | mcSHOW_DBG_MSG2(("iDelay= %4d, err_value: 0x%x", iDelay, u4err_value)); |
| 6905 | |
| 6906 | for(u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) |
| 6907 | { |
| 6908 | u1lead_lag = DramcRxDVSCal(p, u1ByteIdx); |
| 6909 | |
| 6910 | if ((u1lead_lag == 0) && (u1DVS_first_flag[u1ByteIdx] == 0) && (((u4err_value >> (u1ByteIdx<<3)) & 0xff) == 0)) |
| 6911 | { |
| 6912 | u1DVS_first_pass[u1ByteIdx] = iDelay; |
| 6913 | u1DVS_first_flag[u1ByteIdx] = 1; |
| 6914 | |
| 6915 | mcSHOW_DBG_MSG2(("Byte%d find first pass delay\n")) |
| 6916 | } |
| 6917 | else if (((u1lead_lag == 1) || (((u4err_value >> (u1ByteIdx<<3)) & 0xff) != 0)) && (u1DVS_first_flag[u1ByteIdx] == 1) && (u1finish_flag[u1ByteIdx] == 0)) |
| 6918 | { |
| 6919 | u1DVS_pass_window[u1ByteIdx] = iDelay - u1DVS_first_pass[u1ByteIdx] - u16DelayStep; |
| 6920 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6921 | if (u1DVS_pass_window[u1ByteIdx] < 7) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6922 | { |
| 6923 | u1DVS_pass_window[u1ByteIdx] = 0; |
| 6924 | u1DVS_first_flag[u1ByteIdx] = 0; |
| 6925 | mcSHOW_DBG_MSG2(("Byte%d find fake window\n")) |
| 6926 | } |
| 6927 | else |
| 6928 | { |
| 6929 | u1finish_flag[u1ByteIdx] = 1; |
| 6930 | mcSHOW_DBG_MSG2(("Byte%d find pass window\n")) |
| 6931 | } |
| 6932 | } |
| 6933 | } |
| 6934 | |
| 6935 | if ((u1finish_flag[0]==1) && (u1finish_flag[1]==1)) |
| 6936 | { |
| 6937 | mcSHOW_DBG_MSG2(("Two byte DVS window find, early break!\n")); |
| 6938 | break; |
| 6939 | } |
| 6940 | } |
| 6941 | } |
| 6942 | } |
| 6943 | |
| 6944 | DramcEngine2End(p); |
| 6945 | |
| 6946 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 6947 | { |
| 6948 | u1DVS_increase[p->rank][u1ByteIdx] = (u1DVS_pass_window[u1ByteIdx] > 8)? ((u1DVS_pass_window[u1ByteIdx] - 8) >> 3): 0; |
| 6949 | mcSHOW_DBG_MSG(("\nByte %d final DVS window size(M) %d, DVS increase %d\n", u1ByteIdx, u1DVS_pass_window[u1ByteIdx], u1DVS_increase[p->rank][u1ByteIdx])); |
| 6950 | } |
| 6951 | |
| 6952 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 6953 | |
| 6954 | vAutoRefreshSwitch(p, ENABLE); |
| 6955 | |
| 6956 | DramPhyReset(p); |
| 6957 | |
| 6958 | vPrintCalibrationBasicInfo(p); |
| 6959 | |
| 6960 | mcSHOW_DBG_MSG(("\n\n")); |
| 6961 | mcSHOW_DBG_MSG4(("[DramcRxDVSWindowCal] Done\n")); |
| 6962 | |
| 6963 | return DRAM_OK; |
| 6964 | } |
| 6965 | |
| 6966 | void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p) |
| 6967 | { |
| 6968 | U8 rank_i, u1ByteIdx, u1DVS_increase_final, u1DVS_dly_final[DQS_BYTE_NUMBER]={0}; |
| 6969 | U8 backup_rank = p->rank; |
| 6970 | |
| 6971 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 6972 | { |
| 6973 | if (p->support_rank_num == RANK_DUAL) |
| 6974 | u1DVS_increase_final = (u1DVS_increase[RANK_0][u1ByteIdx] < u1DVS_increase[RANK_1][u1ByteIdx])? u1DVS_increase[RANK_0][u1ByteIdx] : u1DVS_increase[RANK_1][u1ByteIdx]; |
| 6975 | else |
| 6976 | u1DVS_increase_final = u1DVS_increase[p->rank][u1ByteIdx]; |
| 6977 | |
| 6978 | if (u1ByteIdx == 0) |
| 6979 | { |
| 6980 | u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0)); |
| 6981 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0); |
| 6982 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6983 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6984 | { |
| 6985 | u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1)); |
| 6986 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1); |
| 6987 | } |
| 6988 | mcSHOW_DBG_MSG(("Byte%d final DVS delay: %d\n", u1ByteIdx, u1DVS_dly_final[u1ByteIdx])); |
| 6989 | } |
| 6990 | |
| 6991 | for(rank_i=RANK_0; rank_i< p->support_rank_num; rank_i++) |
| 6992 | { |
| 6993 | vSetRank(p, rank_i); |
| 6994 | DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, DVS_CAL_KEEP_VREF, AUTOK_OFF, NORMAL_K); |
| 6995 | } |
| 6996 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 6997 | if ((DramcRxDVSCal(p, 0) == 1) || (DramcRxDVSCal(p, 1) == 1)) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 6998 | { |
| 6999 | mcSHOW_ERR_MSG(("Final DVS delay is out of RX window\n")); |
| 7000 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 7001 | { |
| 7002 | if (u1DVS_dly_final[u1ByteIdx] > 0) |
| 7003 | { |
| 7004 | u1DVS_dly_final[u1ByteIdx] -= 1; |
| 7005 | if (u1ByteIdx == 0) |
| 7006 | { |
| 7007 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0); |
| 7008 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7009 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7010 | { |
| 7011 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1); |
| 7012 | } |
| 7013 | } |
| 7014 | for(rank_i=RANK_0; rank_i< p->support_rank_num; rank_i++) |
| 7015 | { |
| 7016 | vSetRank(p, rank_i); |
| 7017 | DramcRxWindowPerbitCal(p, PATTERN_TEST_ENGINE, DVS_CAL_KEEP_VREF, AUTOK_OFF, NORMAL_K); |
| 7018 | } |
| 7019 | } |
| 7020 | } |
| 7021 | |
| 7022 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0); |
| 7023 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1); |
| 7024 | |
| 7025 | vSetRank(p, backup_rank); |
| 7026 | } |
| 7027 | #endif |
| 7028 | |
| 7029 | #if SIMULATION_DATLAT |
| 7030 | static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val) |
| 7031 | { |
| 7032 | U8 u1DATLAT_DSEL = 0; |
| 7033 | U8 u1DLECG_OptionEXT1 = 0; |
| 7034 | U8 u1DLECG_OptionEXT2 = 0; |
| 7035 | U8 u1DLECG_OptionEXT3 = 0; |
| 7036 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7037 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7038 | if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) |
| 7039 | { |
| 7040 | u1DATLAT_DSEL = curr_val; |
| 7041 | } |
| 7042 | else |
| 7043 | { |
| 7044 | if (curr_val < 1) |
| 7045 | u1DATLAT_DSEL = curr_val; |
| 7046 | else |
| 7047 | u1DATLAT_DSEL = curr_val - 1; |
| 7048 | } |
| 7049 | |
| 7050 | // mcSHOW_DBG_MSG(("DATLAT: %d, u1DATLAT_DSEL: %d\n", curr_val, u1DATLAT_DSEL)); |
| 7051 | |
| 7052 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT), |
| 7053 | P_Fld(curr_val, MISC_SHU_RDAT_DATLAT) | |
| 7054 | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL) | |
| 7055 | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY)); |
| 7056 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7057 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7058 | u1DLECG_OptionEXT1 = (curr_val >= 8)? (1): (0); |
| 7059 | u1DLECG_OptionEXT2 = (curr_val >= 14)? (1): (0); |
| 7060 | u1DLECG_OptionEXT3 = (curr_val >= 19)? (1): (0); |
| 7061 | // mcSHOW_DBG_MSG(("u1DLECG_OptionEXT1: %d, 2 for %d, 3 for %d\n", u1DLECG_OptionEXT1, u1DLECG_OptionEXT2, u1DLECG_OptionEXT3)); |
| 7062 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RX_CG_SET0), |
| 7063 | P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_READ_START_EXTEND1) | |
| 7064 | P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) | |
| 7065 | P_Fld((u1DLECG_OptionEXT2), SHU_RX_CG_SET0_READ_START_EXTEND2) | |
| 7066 | P_Fld((u1DLECG_OptionEXT2), SHU_RX_CG_SET0_DLE_LAST_EXTEND2) | |
| 7067 | P_Fld((u1DLECG_OptionEXT3), SHU_RX_CG_SET0_READ_START_EXTEND3) | |
| 7068 | P_Fld((u1DLECG_OptionEXT3), SHU_RX_CG_SET0_DLE_LAST_EXTEND3)); |
| 7069 | |
| 7070 | DramPhyReset(p); |
| 7071 | |
| 7072 | } |
| 7073 | |
| 7074 | static U8 aru1RxDatlatResult[RANK_MAX]; |
| 7075 | DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) |
| 7076 | { |
| 7077 | //U8 ii, ucStartCalVal = 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7078 | //U32 u4err_value = 0xffffffff; |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 7079 | U8 ucbest_step; //ucpipe_num = 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7080 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7081 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7082 | if (!p) |
| 7083 | { |
| 7084 | mcSHOW_ERR_MSG(("context NULL\n")); |
| 7085 | return DRAM_FAIL; |
| 7086 | } |
| 7087 | |
| 7088 | //mcDUMP_REG_MSG(("\n[dumpRG] DramcRxdatlatCal\n")); |
| 7089 | #if VENDER_JV_LOG |
| 7090 | vPrintCalibrationBasicInfo_ForJV(p); |
| 7091 | #else |
| 7092 | vPrintCalibrationBasicInfo(p); |
| 7093 | #endif |
| 7094 | mcSHOW_DBG_MSG(("[RxdatlatCal]\n")); |
| 7095 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7096 | |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 7097 | u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7098 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7099 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7100 | vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL); |
| 7101 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7102 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7103 | ucbest_step = (U8) u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT), MISC_SHU_RDAT_DATLAT); |
| 7104 | mcSHOW_DBG_MSG2(("DATLAT Default: 0x%x\n", ucbest_step)); |
| 7105 | //mcDUMP_REG_MSG(("DATLAT Default: 0x%x\n", ucbest_step)); |
| 7106 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7107 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7108 | DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7109 | |
| 7110 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) |
| 7111 | if (p->femmc_Ready == 1) |
| 7112 | { |
| 7113 | ucbest_step = p->pSavetimeData->u1RxDatlat_Save[p->channel][p->rank]; |
| 7114 | } |
| 7115 | #endif |
| 7116 | |
| 7117 | aru1RxDatlatResult[p->rank] = ucbest_step; |
| 7118 | |
| 7119 | mcSHOW_DBG_MSG(("best_step = %d\n\n", ucbest_step)); |
| 7120 | //mcDUMP_REG_MSG(("best_step=%d\n\n", ucbest_step)); |
| 7121 | |
| 7122 | #if __A60868_TO_BE_PORTING__ |
| 7123 | #if __ETT__ |
| 7124 | U8 _init_Datlat_value = vDramcACTimingGetDatLat(p); |
| 7125 | if ((_init_Datlat_value > (ucbest_step + 1)) || (_init_Datlat_value < (ucbest_step - 1))) |
| 7126 | { |
| 7127 | mcSHOW_DBG_MSG(("[WARNING!!] Datlat initial value(%d) = best_step(%d) %c %d, out of range!\n\n", |
| 7128 | _init_Datlat_value, |
| 7129 | ucbest_step, |
| 7130 | (ucbest_step > _init_Datlat_value)? '-': '+', |
| 7131 | abs(ucbest_step - _init_Datlat_value))); |
| 7132 | while (1); |
| 7133 | } |
| 7134 | #endif |
| 7135 | #endif |
| 7136 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) |
| 7137 | if (p->femmc_Ready == 1) |
| 7138 | { |
| 7139 | dle_factor_handler(p, ucbest_step); |
| 7140 | vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAST_K); |
| 7141 | } |
| 7142 | #endif |
| 7143 | |
| 7144 | mcSHOW_DBG_MSG4(("[DramcRxdatlatCal] Done\n")); |
| 7145 | return DRAM_OK; |
| 7146 | |
| 7147 | } |
| 7148 | |
| 7149 | DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p) |
| 7150 | { |
| 7151 | U8 u1FinalDatlat, u1Datlat0, u1Datlat1; |
| 7152 | |
| 7153 | u1Datlat0 = aru1RxDatlatResult[0]; |
| 7154 | u1Datlat1 = aru1RxDatlatResult[1]; |
| 7155 | |
| 7156 | if (p->support_rank_num == RANK_DUAL) |
| 7157 | { |
| 7158 | if (u1Datlat0 > u1Datlat1) |
| 7159 | { |
| 7160 | u1FinalDatlat = u1Datlat0; |
| 7161 | } |
| 7162 | else |
| 7163 | { |
| 7164 | u1FinalDatlat = u1Datlat1; |
| 7165 | } |
| 7166 | } |
| 7167 | else |
| 7168 | { |
| 7169 | u1FinalDatlat = u1Datlat0; |
| 7170 | } |
| 7171 | |
| 7172 | #if ENABLE_READ_DBI |
| 7173 | if (p->DBI_R_onoff[p->dram_fsp]) |
| 7174 | { |
| 7175 | u1FinalDatlat++; |
| 7176 | } |
| 7177 | #endif |
| 7178 | |
| 7179 | dle_factor_handler(p, u1FinalDatlat); |
| 7180 | |
| 7181 | #if RDSEL_TRACKING_EN |
| 7182 | if(p->frequency >= RDSEL_TRACKING_TH) |
| 7183 | { |
| 7184 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RDSEL_TRACK), u1FinalDatlat, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); |
| 7185 | } |
| 7186 | #endif |
| 7187 | |
| 7188 | mcSHOW_DBG_MSG(("[DualRankRxdatlatCal] RK0: %d, RK1: %d, Final_Datlat %d\n", u1Datlat0, u1Datlat1, u1FinalDatlat)); |
| 7189 | //mcDUMP_REG_MSG(("[DualRankRxdatlatCal] RK0: %d, RK1: %d, Final_Datlat %d\n", u1Datlat0, u1Datlat1, u1FinalDatlat)); |
| 7190 | |
| 7191 | |
| 7192 | #if defined(FOR_HQA_TEST_USED) && defined(FOR_HQA_REPORT_USED) |
| 7193 | { U8 backup_rank, rank_index; |
| 7194 | |
| 7195 | backup_rank = u1GetRank(p); |
| 7196 | for(rank_index = RANK_0; rank_index < p->support_rank_num; rank_index++) |
| 7197 | { |
| 7198 | vSetRank(p, rank_index); |
| 7199 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT2, "DATLAT", "", 0, u1FinalDatlat, NULL); |
| 7200 | } |
| 7201 | vSetRank(p, backup_rank); |
| 7202 | } |
| 7203 | #endif |
| 7204 | |
| 7205 | return DRAM_OK; |
| 7206 | |
| 7207 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7208 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7209 | |
| 7210 | #if SIMULATION_TX_PERBIT |
| 7211 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7212 | #if (SW_CHANGE_FOR_SIMULATION || FOR_DV_SIMULATION_USED) |
| 7213 | #define TX_VREF_RANGE_BEGIN 0 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7214 | #define TX_VREF_RANGE_END 2 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7215 | #define TX_VREF_RANGE_STEP 2 |
| 7216 | #else |
| 7217 | #define TX_VREF_RANGE_BEGIN 16 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7218 | #define TX_VREF_RANGE_END 50 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7219 | #define TX_VREF_RANGE_STEP 2 |
| 7220 | #endif |
| 7221 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7222 | #define TX_DQ_UI_TO_PI_TAP 64 |
| 7223 | #define TX_PHASE_DQ_UI_TO_PI_TAP 32 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7224 | #define LP4_TX_VREF_DATA_NUM 50 |
| 7225 | #define LP4_TX_VREF_PASS_CONDITION 0 |
| 7226 | #define TX_PASS_WIN_CRITERIA 7 |
| 7227 | #define LP4_TX_VREF_BOUNDARY_NOT_READY 0xff |
| 7228 | |
| 7229 | typedef struct _PASS_WIN_DATA_BY_VREF_T |
| 7230 | { |
| 7231 | U16 u2VrefUsed; |
| 7232 | U16 u2WinSum_byVref; |
| 7233 | U8 u1WorseBitWinSize_byVref; |
| 7234 | U8 u1WorseBitIdx_byVref; |
| 7235 | } PASS_WIN_DATA_BY_VREF_T; |
| 7236 | |
| 7237 | #if 0 |
| 7238 | static U16 WDQSMode2AcTxOEShift(DRAMC_CTX_T *p) |
| 7239 | { |
| 7240 | U16 u2TxDQOEShift = 0; |
| 7241 | |
| 7242 | switch (p->frequency) |
| 7243 | { |
| 7244 | case 1866: |
| 7245 | u2TxDQOEShift = 19; |
| 7246 | break; |
| 7247 | case 1600: |
| 7248 | case 1200: |
| 7249 | case 800: |
| 7250 | case 600: |
| 7251 | u2TxDQOEShift = 15; |
| 7252 | break; |
| 7253 | case 933: |
| 7254 | u2TxDQOEShift = 11; |
| 7255 | break; |
| 7256 | case 400: |
| 7257 | u2TxDQOEShift = 16; |
| 7258 | break; |
| 7259 | default: |
| 7260 | mcSHOW_ERR_MSG(("[WDQSMode2AcTxOEShift] frequency err!\n")); |
| 7261 | #if __ETT__ |
| 7262 | while (1); |
| 7263 | #endif |
| 7264 | } |
| 7265 | |
| 7266 | return u2TxDQOEShift; |
| 7267 | } |
| 7268 | #endif |
| 7269 | void TxWinTransferDelayToUIPI(DRAMC_CTX_T *p, U16 uiDelay, U8 u1AdjustPIToCenter, U8* pu1UILarge_DQ, U8* pu1UISmall_DQ, U8* pu1PI, U8* pu1UILarge_DQOE, U8* pu1UISmall_DQOE) |
| 7270 | { |
| 7271 | U8 u1Small_ui_to_large, u1PI = 0, u164PIto1UI, u1TxDQOEShift = 0; |
| 7272 | U16 u2TmpValue, u2DQOE_shift; |
| 7273 | DDR800_MODE_T eDdr800Mode = vGet_DDR_Loop_Mode(p); |
| 7274 | U8 u1PiTap = (u1IsPhaseMode(p) == TRUE) ? TX_PHASE_DQ_UI_TO_PI_TAP : TX_DQ_UI_TO_PI_TAP; |
| 7275 | |
| 7276 | u1Small_ui_to_large = u1MCK2UI_DivShift(p); |
| 7277 | |
| 7278 | #if ENABLE_WDQS_MODE_2 |
| 7279 | u1TxDQOEShift = WDQSMode2AcTxOEShift(p); |
| 7280 | #else |
| 7281 | u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4; |
| 7282 | #endif |
| 7283 | |
| 7284 | if(pu1PI != NULL) |
| 7285 | { |
| 7286 | u1PI = uiDelay & (u1PiTap-1); |
| 7287 | *pu1PI =u1PI; |
| 7288 | } |
| 7289 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7290 | if (u1IsLP4Div4DDR800(p) || u1IsPhaseMode(p)) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7291 | u164PIto1UI = 0; |
| 7292 | else |
| 7293 | u164PIto1UI = 1; |
| 7294 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7295 | u2TmpValue = (uiDelay /u1PiTap)<<u164PIto1UI; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7296 | |
| 7297 | if (u1AdjustPIToCenter && (pu1PI != NULL) && (eDdr800Mode == CLOSE_LOOP_MODE)) |
| 7298 | { |
| 7299 | if (u1PI < 10) |
| 7300 | { |
| 7301 | u1PI += (u1PiTap) >> 1; |
| 7302 | u2TmpValue --; |
| 7303 | } |
| 7304 | else if (u1PI > u1PiTap - 10) |
| 7305 | { |
| 7306 | u1PI -= (u1PiTap) >> 1; |
| 7307 | u2TmpValue ++; |
| 7308 | } |
| 7309 | |
| 7310 | *pu1PI = u1PI; |
| 7311 | } |
| 7312 | |
| 7313 | #if 0 |
| 7314 | *pu1UISmall_DQ = u2TmpValue % u1Small_ui_to_large; |
| 7315 | *pu1UILarge_DQ = u2TmpValue / u1Small_ui_to_large; |
| 7316 | #else |
| 7317 | *pu1UISmall_DQ = u2TmpValue - ((u2TmpValue >> u1Small_ui_to_large) << u1Small_ui_to_large); |
| 7318 | *pu1UILarge_DQ = (u2TmpValue >> u1Small_ui_to_large); |
| 7319 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7320 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7321 | { |
| 7322 | u2TmpValue -= u1TxDQOEShift; |
| 7323 | } |
| 7324 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7325 | if(((u1MR03Value[p->dram_fsp]&0x80)>>7)==1) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7326 | { |
| 7327 | if (vGet_Div_Mode(p) == DIV4_MODE) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7328 | u2DQOE_shift = 4; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7329 | else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7330 | u2DQOE_shift = 8; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7331 | |
| 7332 | u2TmpValue += u2DQOE_shift; |
| 7333 | } |
| 7334 | |
| 7335 | *pu1UISmall_DQOE = u2TmpValue - ((u2TmpValue >> u1Small_ui_to_large) << u1Small_ui_to_large); |
| 7336 | *pu1UILarge_DQOE = (u2TmpValue >> u1Small_ui_to_large); |
| 7337 | } |
| 7338 | |
| 7339 | #if 0 |
| 7340 | static void TxPrintWidnowInfo(DRAMC_CTX_T *p, PASS_WIN_DATA_T WinPerBitData[]) |
| 7341 | { |
| 7342 | U8 u1BitIdx; |
| 7343 | |
| 7344 | for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) |
| 7345 | { |
| 7346 | #ifdef ETT_PRINT_FORMAT |
| 7347 | mcSHOW_DBG_MSG(("TX Bit%d (%d~%d) %d %d, Bit%d (%d~%d) %d %d,", \ |
| 7348 | u1BitIdx, WinPerBitData[u1BitIdx].first_pass, WinPerBitData[u1BitIdx].last_pass, WinPerBitData[u1BitIdx].win_size, WinPerBitData[u1BitIdx].win_center, \ |
| 7349 | u1BitIdx + 8, WinPerBitData[u1BitIdx + 8].first_pass, WinPerBitData[u1BitIdx + 8].last_pass, WinPerBitData[u1BitIdx + 8].win_size, WinPerBitData[u1BitIdx + 8].win_center)); |
| 7350 | #else |
| 7351 | mcSHOW_DBG_MSG(("TX Bit%2d (%2d~%2d) %2d %2d, Bit%2d (%2d~%2d) %2d %2d,", \ |
| 7352 | u1BitIdx, WinPerBitData[u1BitIdx].first_pass, WinPerBitData[u1BitIdx].last_pass, WinPerBitData[u1BitIdx].win_size, WinPerBitData[u1BitIdx].win_center, \ |
| 7353 | u1BitIdx + 8, WinPerBitData[u1BitIdx + 8].first_pass, WinPerBitData[u1BitIdx + 8].last_pass, WinPerBitData[u1BitIdx + 8].win_size, WinPerBitData[u1BitIdx + 8].win_center)); |
| 7354 | #endif |
| 7355 | #if PIN_CHECK_TOOL |
| 7356 | PINInfo_flashtool.DQ_TX_WIN_SIZE[p->channel][p->rank][u1BitIdx] = WinPerBitData[u1BitIdx].win_size; |
| 7357 | PINInfo_flashtool.DQ_TX_WIN_SIZE[p->channel][p->rank][u1BitIdx+8] = WinPerBitData[u1BitIdx+8].win_size; |
| 7358 | #endif |
| 7359 | mcSHOW_DBG_MSG(("\n")); |
| 7360 | } |
| 7361 | mcSHOW_DBG_MSG(("\n")); |
| 7362 | #if DUMP_TA2_WINDOW_SIZE_RX_TX |
| 7363 | { |
| 7364 | U32 u4B0Tatal=0; |
| 7365 | U32 u4B1Tatal=0; |
| 7366 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 7367 | { |
| 7368 | if(u1BitIdx < 8) |
| 7369 | { |
| 7370 | u4B0Tatal += WinPerBitData[u1BitIdx].win_size; |
| 7371 | } |
| 7372 | else |
| 7373 | { |
| 7374 | u4B1Tatal += WinPerBitData[u1BitIdx].win_size; |
| 7375 | } |
| 7376 | } |
| 7377 | mcSHOW_DBG_MSG(("\ntotal tx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal)); |
| 7378 | } |
| 7379 | #endif |
| 7380 | } |
| 7381 | #endif |
| 7382 | |
| 7383 | static void TXPerbitCalibrationInit(DRAMC_CTX_T *p, U8 calType) |
| 7384 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7385 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7386 | if (calType != TX_DQ_DQS_MOVE_DQM_ONLY) |
| 7387 | { |
| 7388 | #if 1 |
| 7389 | #if PINMUX_AUTO_TEST_PER_BIT_TX |
| 7390 | if(gTX_check_per_bit_flag == 1) |
| 7391 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7392 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7393 | } |
| 7394 | else |
| 7395 | #endif |
| 7396 | { |
| 7397 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), 0); |
| 7398 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), 0); |
| 7399 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), 0); |
| 7400 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), 0); |
| 7401 | } |
| 7402 | #else |
| 7403 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_R0_B0_DQ0), P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0) |
| 7404 | | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0) |
| 7405 | | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0) |
| 7406 | | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0) |
| 7407 | | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0) |
| 7408 | | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0) |
| 7409 | | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0) |
| 7410 | | P_Fld(0x0, SHU_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0)); |
| 7411 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_R0_B1_DQ0), P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1) |
| 7412 | | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1) |
| 7413 | | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1) |
| 7414 | | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1) |
| 7415 | | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1) |
| 7416 | | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1) |
| 7417 | | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1) |
| 7418 | | P_Fld(0x0, SHU_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1)); |
| 7419 | #endif |
| 7420 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY3), 0x0, SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0); |
| 7421 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY3), 0x0, SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1); |
| 7422 | } |
| 7423 | |
| 7424 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7425 | |
| 7426 | } |
| 7427 | |
| 7428 | #define TX_TDQS2DQ_PRE_CAL 0 |
| 7429 | #if TX_TDQS2DQ_PRE_CAL |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7430 | |
| 7431 | U16 u2DQS2DQ_Pre_Cal[CHANNEL_NUM][RANK_MAX][2] = {0}; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7432 | #endif |
| 7433 | |
| 7434 | static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U16 *pu2Begin, U16 *pu2End) |
| 7435 | { |
| 7436 | U8 u1MCK2UI, u1UI2PI, u1ByteIdx; |
| 7437 | U32 u4RegValue_TXDLY, u4RegValue_dly; |
| 7438 | U8 ucdq_ui_large_bak[DQS_BYTE_NUMBER], ucdq_ui_small_bak[DQS_BYTE_NUMBER]; |
| 7439 | U16 u2TempVirtualDelay, u2SmallestVirtualDelay = 0xffff; |
| 7440 | U16 u2DQDelayBegin = 0, u2DQDelayEnd = 0; |
| 7441 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7442 | { |
| 7443 | u4RegValue_TXDLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0)); |
| 7444 | u4RegValue_dly = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1)); |
| 7445 | } |
| 7446 | |
| 7447 | u1MCK2UI = u1MCK2UI_DivShift(p); |
| 7448 | |
| 7449 | if (vGet_DDR_Loop_Mode(p) == DDR800_CLOSE_LOOP) |
| 7450 | u1UI2PI = 6; |
| 7451 | else |
| 7452 | u1UI2PI = 5; |
| 7453 | |
| 7454 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7455 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7456 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 7457 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7458 | ucdq_ui_large_bak[u1ByteIdx] = (u4RegValue_TXDLY >> (u1ByteIdx << 2)) & 0x7; |
| 7459 | ucdq_ui_small_bak[u1ByteIdx] = (u4RegValue_dly >> (u1ByteIdx << 2)) & 0x7; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7460 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7461 | u2TempVirtualDelay = (((ucdq_ui_large_bak[u1ByteIdx] << u1MCK2UI) + ucdq_ui_small_bak[u1ByteIdx]) << u1UI2PI) + wrlevel_dqs_final_delay[p->rank][u1ByteIdx]; |
| 7462 | |
| 7463 | if (u2TempVirtualDelay < u2SmallestVirtualDelay) |
| 7464 | { |
| 7465 | u2SmallestVirtualDelay = u2TempVirtualDelay; |
| 7466 | } |
| 7467 | |
| 7468 | //mcSHOW_DBG_MSG2(("Original DQS_B%d VirtualDelay %d = (%d %d %d)\n", u1ByteIdx, u2TempVirtualDelay, |
| 7469 | // ucdq_ui_large_bak[u1ByteIdx], ucdq_ui_small_bak[u1ByteIdx], wrlevel_dqs_final_delay[p->rank][u1ByteIdx])); |
| 7470 | } |
| 7471 | |
| 7472 | u2DQDelayBegin = u2SmallestVirtualDelay; |
| 7473 | |
| 7474 | #if TX_TDQS2DQ_PRE_CAL |
| 7475 | if (u1IsLP4Div4DDR800(p) == FALSE) |
| 7476 | { |
| 7477 | if (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] > 0) |
| 7478 | { |
| 7479 | U16 u2TmpShift; |
| 7480 | mcSHOW_DBG_MSG(("TX_TDQS2DQ_PRE_CAL : change DQ begin %d -->", u2DQDelayBegin)); |
| 7481 | |
| 7482 | u2TmpShift = (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)]* p->frequency) / 1000; |
| 7483 | if (u2TmpShift >= 15) |
| 7484 | u2TmpShift -= 15; |
| 7485 | else |
| 7486 | u2TmpShift = 0; |
| 7487 | |
| 7488 | u2DQDelayBegin += u2TmpShift; |
| 7489 | mcSHOW_DBG_MSG(("%d (+%d)\n", u2DQDelayBegin, u2TmpShift)); |
| 7490 | } |
| 7491 | } |
| 7492 | #endif |
| 7493 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7494 | #if TX_K_DQM_WITH_WDBI |
| 7495 | if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) |
| 7496 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7497 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7498 | u2DQDelayBegin -= (1 << (u1MCK2UI + 5)); |
| 7499 | } |
| 7500 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7501 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7502 | u2DQDelayEnd = u2DQDelayBegin + ((1 << u1MCK2UI) << u1UI2PI); |
| 7503 | |
| 7504 | *pu2Begin = u2DQDelayBegin; |
| 7505 | *pu2End = u2DQDelayEnd; |
| 7506 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7507 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7508 | mcSHOW_DBG_MSG(("TXScanRange_PI %d~%d\n", u2DQDelayBegin, u2DQDelayEnd)); |
| 7509 | #endif |
| 7510 | } |
| 7511 | |
| 7512 | |
| 7513 | static void TXScanRange_Vref(DRAMC_CTX_T *p, U8 u1VrefScanEnable, U16* pu2Range, U16 *pu2Begin, U16 *pu2End, U16 *pu2Setp) |
| 7514 | { |
| 7515 | U16 u2VrefBegin = 0, u2VrefEnd = 0; |
| 7516 | |
| 7517 | if (u1VrefScanEnable) |
| 7518 | { |
| 7519 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL) |
| 7520 | if (p->femmc_Ready == 1) |
| 7521 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7522 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7523 | u2VrefBegin = p->pSavetimeData->u1TxWindowPerbitVref_Save[p->channel][p->rank]; |
| 7524 | u2VrefEnd = u2VrefBegin + 1; |
| 7525 | } |
| 7526 | #endif |
| 7527 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7528 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7529 | { |
| 7530 | u2VrefBegin = 0; |
| 7531 | u2VrefEnd = 0; |
| 7532 | } |
| 7533 | |
| 7534 | *pu2Range = (!p->odt_onoff); |
| 7535 | *pu2Begin = u2VrefBegin; |
| 7536 | *pu2End = u2VrefEnd; |
| 7537 | *pu2Setp = TX_VREF_RANGE_STEP; |
| 7538 | |
| 7539 | } |
| 7540 | |
| 7541 | static U16 TxChooseVref(DRAMC_CTX_T *p, PASS_WIN_DATA_BY_VREF_T pVrefInfo[], U8 u1VrefNum) |
| 7542 | { |
| 7543 | U8 u1VrefIdx, u1WorseBitIdx = 0, u1WinSizeOfWorseBit = 0; |
| 7544 | //U8 u1VrefPassBegin = LP4_TX_VREF_BOUNDARY_NOT_READY, u1VrefPassEnd = LP4_TX_VREF_BOUNDARY_NOT_READY, u1TempPassNum = 0, u1MaxVerfPassNum = 0; |
| 7545 | //U8 u1VrefPassBegin_Final = LP4_TX_VREF_BOUNDARY_NOT_READY, u1VrefPassEnd_Final = LP4_TX_VREF_BOUNDARY_NOT_READY; |
| 7546 | U16 u2MaxWinSum = 0; |
| 7547 | U16 u2FinalVref = 0; |
| 7548 | |
| 7549 | for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++) |
| 7550 | { |
| 7551 | mcSHOW_DBG_MSG2(("TX Vref=%d, minBit %d, minWin=%d, winSum=%d\n", |
| 7552 | pVrefInfo[u1VrefIdx].u2VrefUsed, |
| 7553 | pVrefInfo[u1VrefIdx].u1WorseBitIdx_byVref, |
| 7554 | pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref, |
| 7555 | pVrefInfo[u1VrefIdx].u2WinSum_byVref)); |
| 7556 | |
| 7557 | #if LP4_TX_VREF_PASS_CONDITION |
| 7558 | if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > LP4_TX_VREF_PASS_CONDITION)) |
| 7559 | { |
| 7560 | if (u1VrefPassBegin == LP4_TX_VREF_BOUNDARY_NOT_READY) |
| 7561 | { |
| 7562 | u1VrefPassBegin = pVrefInfo[u1VrefIdx].u2VrefUsed; |
| 7563 | u1TempPassNum = 1; |
| 7564 | } |
| 7565 | else |
| 7566 | u1TempPassNum ++; |
| 7567 | |
| 7568 | if (u1VrefIdx == u1VrefNum - 1) |
| 7569 | { |
| 7570 | u1VrefPassEnd = pVrefInfo[u1VrefIdx].u2VrefUsed; |
| 7571 | if (u1TempPassNum > u1MaxVerfPassNum) |
| 7572 | { |
| 7573 | u1VrefPassBegin_Final = u1VrefPassBegin; |
| 7574 | u1VrefPassEnd_Final = u1VrefPassEnd; |
| 7575 | u1MaxVerfPassNum = u1TempPassNum; |
| 7576 | } |
| 7577 | } |
| 7578 | } |
| 7579 | else |
| 7580 | { |
| 7581 | if ((u1VrefPassBegin != LP4_TX_VREF_BOUNDARY_NOT_READY) && (u1VrefPassEnd == LP4_TX_VREF_BOUNDARY_NOT_READY)) |
| 7582 | { |
| 7583 | u1VrefPassEnd = pVrefInfo[u1VrefIdx].u2VrefUsed - TX_VREF_RANGE_STEP; |
| 7584 | if (u1TempPassNum > u1MaxVerfPassNum) |
| 7585 | { |
| 7586 | u1VrefPassBegin_Final = u1VrefPassBegin; |
| 7587 | u1VrefPassEnd_Final = u1VrefPassEnd; |
| 7588 | u1MaxVerfPassNum = u1TempPassNum; |
| 7589 | } |
| 7590 | u1VrefPassBegin = 0xff; |
| 7591 | u1VrefPassEnd = 0xff; |
| 7592 | u1TempPassNum = 0; |
| 7593 | } |
| 7594 | } |
| 7595 | #endif |
| 7596 | } |
| 7597 | |
| 7598 | #if LP4_TX_VREF_PASS_CONDITION |
| 7599 | //if((u1VrefPassBegin_Final !=LP4_TX_VREF_BOUNDARY_NOT_READY) && (u1VrefPassEnd_Final!=LP4_TX_VREF_BOUNDARY_NOT_READY)) |
| 7600 | if (u1MaxVerfPassNum > 0) |
| 7601 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7602 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7603 | u2FinalVref = (u1VrefPassBegin_Final + u1VrefPassEnd_Final) >> 1; |
| 7604 | mcSHOW_DBG_MSG(("[TxChooseVref] Window > %d, Vref (%d~%d), Final Vref %d\n", LP4_TX_VREF_PASS_CONDITION, u1VrefPassBegin_Final, u1VrefPassEnd_Final, u2FinalVref)); |
| 7605 | } |
| 7606 | else |
| 7607 | #endif |
| 7608 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7609 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7610 | for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++) |
| 7611 | { |
| 7612 | if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > u1WinSizeOfWorseBit) || |
| 7613 | ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref == u1WinSizeOfWorseBit) && (pVrefInfo[u1VrefIdx].u2WinSum_byVref > u2MaxWinSum))) |
| 7614 | { |
| 7615 | u1WinSizeOfWorseBit = pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref; |
| 7616 | u1WorseBitIdx = pVrefInfo[u1VrefIdx].u1WorseBitIdx_byVref; |
| 7617 | u2MaxWinSum = pVrefInfo[u1VrefIdx].u2WinSum_byVref; |
| 7618 | u2FinalVref = pVrefInfo[u1VrefIdx].u2VrefUsed; |
| 7619 | } |
| 7620 | } |
| 7621 | |
| 7622 | mcSHOW_DBG_MSG(("[TxChooseVref] Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", u1WorseBitIdx, u1WinSizeOfWorseBit, u2MaxWinSum, u2FinalVref)); |
| 7623 | //mcDUMP_REG_MSG(("[TxChooseVref] Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", u1WorseBitIdx, u1WinSizeOfWorseBit, u2MaxWinSum, u2FinalVref)); |
| 7624 | } |
| 7625 | |
| 7626 | return u2FinalVref; |
| 7627 | } |
| 7628 | |
| 7629 | |
| 7630 | static void DramcTXSetVref(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefValue) |
| 7631 | { |
| 7632 | U8 u1TempOPValue; |
| 7633 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7634 | u1TempOPValue = ((u1VrefValue & 0x3f) | (u1VrefRange << 6)); |
| 7635 | |
| 7636 | u1MR14Value[p->channel][p->rank][p->dram_fsp] = u1TempOPValue; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7637 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7638 | |
| 7639 | DramcModeRegWriteByRank(p, p->rank, 14, u1TempOPValue); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7640 | |
| 7641 | #if CALIBRATION_SPEED_UP_DEBUG |
| 7642 | mcSHOW_DBG_MSG2(("Yulia TX Vref : CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u1VrefRange, (u1VrefValue & 0x3f))); |
| 7643 | #endif |
| 7644 | } |
| 7645 | |
| 7646 | |
| 7647 | static void TXSetFinalVref(DRAMC_CTX_T *p, U16 u2FinalRange, U16 u2FinalVref) |
| 7648 | { |
| 7649 | DramcTXSetVref(p, u2FinalRange, u2FinalVref); |
| 7650 | |
| 7651 | #ifdef FOR_HQA_TEST_USED |
| 7652 | gFinalTXVrefDQ[p->channel][p->rank] = (U8) u2FinalVref; |
| 7653 | #endif |
| 7654 | |
| 7655 | #if VENDER_JV_LOG |
| 7656 | mcSHOW_DBG_MSG5(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref)); |
| 7657 | #else |
| 7658 | mcSHOW_DBG_MSG(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref)); |
| 7659 | #endif |
| 7660 | |
| 7661 | #if CALIBRATION_SPEED_UP_DEBUG |
| 7662 | mcSHOW_DBG_MSG2(("Yulia TX Vref Final: CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u2FinalRange, u2FinalVref)); |
| 7663 | #endif |
| 7664 | } |
| 7665 | |
| 7666 | |
| 7667 | #if ENABLE_TX_TRACKING |
| 7668 | #if !BYPASS_CALIBRATION |
| 7669 | static |
| 7670 | #endif |
| 7671 | void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]) |
| 7672 | { |
| 7673 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQM_ONLY) |
| 7674 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7675 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7676 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) |
| 7677 | { |
| 7678 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), |
| 7679 | P_Fld(ucdq_pi[0], SHURK_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_pi[1], SHURK_PI_RK0_ARPI_DQ_B1)); |
| 7680 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7681 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7682 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL1), |
| 7683 | P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1) | |
| 7684 | P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7685 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7686 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL2), |
| 7687 | P_Fld(ucdq_pi[1], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1) | |
| 7688 | P_Fld(ucdq_pi[0], SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0)); |
| 7689 | } |
| 7690 | |
| 7691 | //if(calType ==TX_DQ_DQS_MOVE_DQM_ONLY || (calType ==TX_DQ_DQS_MOVE_DQ_ONLY)) |
| 7692 | { |
| 7693 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), |
| 7694 | P_Fld(ucdqm_pi[0], SHURK_PI_RK0_ARPI_DQM_B0) | P_Fld(ucdqm_pi[1], SHURK_PI_RK0_ARPI_DQM_B1)); |
| 7695 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7696 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7697 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQS2DQ_CAL5), |
| 7698 | P_Fld(ucdqm_pi[1], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1) | |
| 7699 | P_Fld(ucdqm_pi[0], SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0)); |
| 7700 | } |
| 7701 | } |
| 7702 | |
| 7703 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7704 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7705 | vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI + (CHANNEL_A << POS_BANK_NUM), \ |
| 7706 | P_Fld(ucdq_final_pi[0], SHURK0_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_final_pi[1], SHURK0_PI_RK0_ARPI_DQ_B1)); |
| 7707 | |
| 7708 | vIO32WriteFldMulti(DRAMC_REG_SHURK0_PI + SHIFT_TO_CHB_ADDR, \ |
| 7709 | P_Fld(ucdq_final_pi[2], SHURK0_PI_RK0_ARPI_DQ_B0) | P_Fld(ucdq_final_pi[3], SHURK0_PI_RK0_ARPI_DQ_B1)); |
| 7710 | #endif |
| 7711 | |
| 7712 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7713 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7714 | |
| 7715 | #if !BYPASS_CALIBRATION |
| 7716 | static |
| 7717 | #endif |
| 7718 | void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdq_ui_large[], U8 ucdq_oen_ui_large[], U8 ucdq_ui_small[], U8 ucdq_oen_ui_small[], U8 ucdql_pi[]) |
| 7719 | { |
| 7720 | if (u1UpdateRegUI) |
| 7721 | { |
| 7722 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ |
| 7723 | P_Fld(ucdq_ui_large[0], SHURK_SELPH_DQ0_TXDLY_DQ0) | |
| 7724 | P_Fld(ucdq_ui_large[1], SHURK_SELPH_DQ0_TXDLY_DQ1) | |
| 7725 | P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | |
| 7726 | P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ0_TXDLY_OEN_DQ1)); |
| 7727 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7728 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7729 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ |
| 7730 | P_Fld(ucdq_ui_small[0], SHURK_SELPH_DQ2_DLY_DQ0) | |
| 7731 | P_Fld(ucdq_ui_small[1], SHURK_SELPH_DQ2_DLY_DQ1) | |
| 7732 | P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ2_DLY_OEN_DQ0) | |
| 7733 | P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ2_DLY_OEN_DQ1)); |
| 7734 | } |
| 7735 | |
| 7736 | |
| 7737 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdql_pi[0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); |
| 7738 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdql_pi[1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1); |
| 7739 | } |
| 7740 | |
| 7741 | #if !BYPASS_CALIBRATION |
| 7742 | static |
| 7743 | #endif |
| 7744 | void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]) |
| 7745 | { |
| 7746 | if (u1UpdateRegUI) |
| 7747 | { |
| 7748 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), |
| 7749 | P_Fld(ucdqm_ui_large[0], SHURK_SELPH_DQ1_TXDLY_DQM0) | |
| 7750 | P_Fld(ucdqm_ui_large[1], SHURK_SELPH_DQ1_TXDLY_DQM1) | |
| 7751 | P_Fld(ucdqm_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | |
| 7752 | P_Fld(ucdqm_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1)); |
| 7753 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7754 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7755 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), |
| 7756 | P_Fld(ucdqm_ui_small[0], SHURK_SELPH_DQ3_DLY_DQM0) | |
| 7757 | P_Fld(ucdqm_ui_small[1], SHURK_SELPH_DQ3_DLY_DQM1) | |
| 7758 | P_Fld(ucdqm_oen_ui_small[0], SHURK_SELPH_DQ3_DLY_OEN_DQM0) | |
| 7759 | P_Fld(ucdqm_oen_ui_small[1], SHURK_SELPH_DQ3_DLY_OEN_DQM1)); |
| 7760 | } |
| 7761 | |
| 7762 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdqm_pi[0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); |
| 7763 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdqm_pi[1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1); |
| 7764 | } |
| 7765 | |
| 7766 | #if TX_AUTO_K_SUPPORT |
| 7767 | static void Tx_Auto_K_Init(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi, U8 u1PI_Len) |
| 7768 | { |
| 7769 | u8 pi_thrd = 0xa; |
| 7770 | //u8 early_break = 0x0; |
| 7771 | |
| 7772 | #if FOR_DV_SIMULATION_USED == 1 |
| 7773 | cal_sv_rand_args_t *psra = get_psra(); |
| 7774 | |
| 7775 | if (psra) { |
| 7776 | pi_thrd = psra->tx_atk_pass_pi_thrd & 0xFF; |
| 7777 | early_break = psra->tx_atk_early_break & 0xFF; |
| 7778 | } |
| 7779 | #endif |
| 7780 | |
| 7781 | #if ENABLE_PA_IMPRO_FOR_TX_AUTOK |
| 7782 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 0x1, DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK); |
| 7783 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0), 0x1, TX_CG_SET0_TX_ATK_CLKRUN); |
| 7784 | #endif |
| 7785 | |
| 7786 | if (calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 7787 | { |
| 7788 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7789 | P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN) | |
| 7790 | P_Fld(0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7791 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7792 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | |
| 7793 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) | |
| 7794 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | |
| 7795 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7796 | } |
| 7797 | else if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) |
| 7798 | { |
| 7799 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DQM_PI_EN); |
| 7800 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), |
| 7801 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | |
| 7802 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); |
| 7803 | } |
| 7804 | else |
| 7805 | { |
| 7806 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DQ_PI_EN); |
| 7807 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), |
| 7808 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | |
| 7809 | P_Fld(ucdq_pi, TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT)); |
| 7810 | } |
| 7811 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7812 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7813 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7814 | P_Fld(u1PI_Len, TX_ATK_SET1_TX_ATK_PI_LEN) | |
| 7815 | P_Fld(pi_thrd, TX_ATK_SET1_TX_ATK_PASS_PI_THRD)); |
| 7816 | #if (fcFOR_CHIP_ID == fcIPM) |
| 7817 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), early_break, TX_ATK_SET1_TX_ATK_EARLY_BREAK); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7818 | #endif |
| 7819 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7820 | { |
| 7821 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), |
| 7822 | P_Fld(0x3, SHU_TX_SET0_TXOEN_AUTOSET_OFFSET) | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7823 | P_Fld(0x1, SHU_TX_SET0_TXOEN_AUTOSET_EN)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7824 | } |
| 7825 | |
| 7826 | #if TX_AUTO_K_DEBUG_ENABLE |
| 7827 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_DBG_EN); |
| 7828 | #endif |
| 7829 | } |
| 7830 | |
| 7831 | static void Tx_Auto_K_complete_check(DRAMC_CTX_T *p) |
| 7832 | { |
| 7833 | U32 u4loop_count = 0; |
| 7834 | |
| 7835 | while ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_RESULT8), TX_ATK_RESULT8_TX_ATK_DONE) != 0x1)) |
| 7836 | { |
| 7837 | mcDELAY_US(1); |
| 7838 | u4loop_count++; |
| 7839 | //mcSHOW_DBG_MSG(("Wait! TX auto K is not done!\n")); |
| 7840 | if (u4loop_count > 100000) |
| 7841 | { |
| 7842 | mcSHOW_ERR_MSG(("Error! TX auto K is not done!\n")); |
| 7843 | break; |
| 7844 | } |
| 7845 | } |
| 7846 | |
| 7847 | if ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_RESULT8), TX_ATK_RESULT8_TX_ATK_FIND_PW) == 0x1)) |
| 7848 | { |
| 7849 | vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK); |
| 7850 | mcSHOW_DBG_MSG(("Tx auto K, all bit find passs window\n")); |
| 7851 | } |
| 7852 | else |
| 7853 | { |
| 7854 | mcSHOW_ERR_MSG(("Error! TX auto K is fail!\n")); |
| 7855 | } |
| 7856 | } |
| 7857 | |
| 7858 | static void Tx_Auto_K_Clear(DRAMC_CTX_T *p) |
| 7859 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7860 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_TRIG); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7861 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_TXOEN_AUTOSET_EN); |
| 7862 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0x1, MISC_CTRL1_R_DMARPIDQ_SW); |
| 7863 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_DBG_EN); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7864 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_CLR); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7865 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x0, TX_ATK_SET1_TX_ATK_CLR); |
| 7866 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), |
| 7867 | P_Fld(0x0, TX_ATK_SET1_TX_ATK_PI_LEN) | |
| 7868 | P_Fld(0x0, TX_ATK_SET1_TX_ATK_DQ_PI_EN) | |
| 7869 | P_Fld(0x0, TX_ATK_SET1_TX_ATK_DQM_PI_EN)); |
| 7870 | #if ENABLE_PA_IMPRO_FOR_TX_AUTOK |
| 7871 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0), 0x0, TX_CG_SET0_TX_ATK_CLKRUN); |
| 7872 | #endif |
| 7873 | } |
| 7874 | |
| 7875 | #if TX_AUTO_K_WORKAROUND |
| 7876 | static void Tx_Auto_K_DQM_Workaround(DRAMC_CTX_T *p) |
| 7877 | { |
| 7878 | //U32 u4DQM_MCK, u4DQM_UI, u4DQM_PI_B0, u4DQM_PI_B1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7879 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7880 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), u4DQM_MCK_RK1_backup); |
| 7881 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), u4DQM_UI_RK1_backup); |
| 7882 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQM_PI_RK1_backup[0]); |
| 7883 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u4DQM_PI_RK1_backup[1]); |
| 7884 | } |
| 7885 | static void Tx_Auto_K_DQ_Workaround(DRAMC_CTX_T *p) |
| 7886 | { |
| 7887 | //U32 u4DQ_MCK, u4DQ_UI, u4DQ_PI_B0, u4DQ_PI_B1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7888 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7889 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), u4DQ_MCK_RK1_backup); |
| 7890 | vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), u4DQ_UI_RK1_backup); |
| 7891 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), u4DQ_PI_RK1_backup[0]); |
| 7892 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), u4DQ_PI_RK1_backup[1]); |
| 7893 | } |
| 7894 | #endif |
| 7895 | |
| 7896 | #if TX_AUTO_K_DEBUG_ENABLE |
| 7897 | static void Tx_Auto_K_Debug_Message(DRAMC_CTX_T *p, U8 u1PI_Len) |
| 7898 | { |
| 7899 | U8 u1bit_num = 0, u1BitIdx; |
| 7900 | U16 u2Length = 0, u2Length_max = 0; |
| 7901 | U32 u4status; |
| 7902 | U32 u4status_bit[4][DQ_DATA_WIDTH]; |
| 7903 | |
| 7904 | if (u1PI_Len == 0) |
| 7905 | u2Length_max = 48; |
| 7906 | else |
| 7907 | u2Length_max = 32 * (1 + u1PI_Len); |
| 7908 | |
| 7909 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 7910 | { |
| 7911 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), u1BitIdx, TX_ATK_SET1_TX_ATK_DBG_BIT_SEL); |
| 7912 | |
| 7913 | u4status_bit[0][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS1)); |
| 7914 | u4status_bit[1][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS2)); |
| 7915 | u4status_bit[2][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS3)); |
| 7916 | u4status_bit[3][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS4)); |
| 7917 | } |
| 7918 | |
| 7919 | mcSHOW_DBG_MSG2(("Debug TX DQ PASS/FAIL status:\n")); |
| 7920 | |
| 7921 | for (u2Length = 0; u2Length < u2Length_max; u2Length++) |
| 7922 | { |
| 7923 | mcSHOW_DBG_MSG2(("Delay=%3d ", u2Length)); |
| 7924 | |
| 7925 | for (u1bit_num = 0; u1bit_num < p->data_width; u1bit_num++) |
| 7926 | { |
| 7927 | u4status = ((u4status_bit[u2Length / 32][u1bit_num] >> (u2Length % 32)) & 0x1); |
| 7928 | |
| 7929 | if (u4status == 0) |
| 7930 | { |
| 7931 | mcSHOW_DBG_MSG2(("x")); |
| 7932 | } |
| 7933 | else |
| 7934 | { |
| 7935 | mcSHOW_DBG_MSG2(("o")); |
| 7936 | } |
| 7937 | |
| 7938 | if (u1bit_num == (p->data_width - 1)) |
| 7939 | { |
| 7940 | mcSHOW_DBG_MSG2((" \n")); |
| 7941 | } |
| 7942 | } |
| 7943 | } |
| 7944 | |
| 7945 | //mcSHOW_DBG_MSG(("Debug DQ PASS(1)/FAIL(0) bit: %d, STATUS1: 0x%x, STATUS2: 0x%x, STATUS3: 0x%x, STATUS4: 0x%x,\n",u1BitIdx,u4status_bit[0][u1BitIdx],u4status_bit[1][u1BitIdx],u4status_bit[2][u1BitIdx],u4status_bit[3][u1BitIdx])); |
| 7946 | } |
| 7947 | #endif |
| 7948 | #endif |
| 7949 | |
| 7950 | #if TX_K_DQM_WITH_WDBI |
| 7951 | void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff) |
| 7952 | { |
| 7953 | S8 u1TXShiftMCK; |
| 7954 | |
| 7955 | u1TXShiftMCK = (u1OnOff)? -1: 1; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7956 | DramcWriteShiftMCKForWriteDBI(p, u1TXShiftMCK); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7957 | |
| 7958 | SetDramModeRegForWriteDBIOnOff(p, p->dram_fsp, u1OnOff); |
| 7959 | DramcWriteDBIOnOff(p, u1OnOff); |
| 7960 | |
| 7961 | #if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND) |
| 7962 | if (p->rank == RANK_1) |
| 7963 | { |
| 7964 | u4DQ_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)); |
| 7965 | u4DQ_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)); |
| 7966 | u4DQ_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)); |
| 7967 | u4DQ_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)); |
| 7968 | } |
| 7969 | #endif |
| 7970 | } |
| 7971 | #endif |
| 7972 | |
| 7973 | DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK) |
| 7974 | { |
| 7975 | U8 u1BitTemp, u1BitIdx, u1ByteIdx, u1RankIdx, backup_rank; |
| 7976 | U32 uiFinishCount; |
| 7977 | PASS_WIN_DATA_T WinPerBit[DQ_DATA_WIDTH], VrefWinPerBit[DQ_DATA_WIDTH], FinalWinPerBit[DQ_DATA_WIDTH]; |
| 7978 | |
| 7979 | U16 uiDelay, u2DQDelayBegin, u2DQDelayEnd, u2DQDelayStep = 1; |
| 7980 | |
| 7981 | U8 ucdq_pi, ucdq_ui_small, ucdq_ui_large, ucdq_oen_ui_small, ucdq_oen_ui_large; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7982 | U8 ucdq_ui_small_reg_value, u1UpdateRegUI; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7983 | |
| 7984 | U8 ucdq_reg_pi[DQS_BYTE_NUMBER], ucdq_reg_ui_large[DQS_BYTE_NUMBER], ucdq_reg_ui_small[DQS_BYTE_NUMBER]; |
| 7985 | U8 ucdq_reg_oen_ui_large[DQS_BYTE_NUMBER], ucdq_reg_oen_ui_small[DQS_BYTE_NUMBER]; |
| 7986 | |
| 7987 | U8 ucdq_reg_dqm_pi[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_ui_small[DQS_BYTE_NUMBER] = {0}; |
| 7988 | U8 ucdq_reg_dqm_oen_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_reg_dqm_oen_ui_small[DQS_BYTE_NUMBER] = {0}; |
| 7989 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 7990 | #if 1 |
| 7991 | U16 u2DQM_Delay; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 7992 | U16 u2Center_min[DQS_BYTE_NUMBER] = {0}, u2Center_max[DQS_BYTE_NUMBER] = {0}; |
| 7993 | #endif |
| 7994 | U8 u1EnableDelayCell = 0; |
| 7995 | U16 u2DelayCellOfst[DQ_DATA_WIDTH] = {0}; |
| 7996 | U32 u4err_value, u4fail_bit; |
| 7997 | U16 u2FinalRange = 0, u2FinalVref; |
| 7998 | U16 u2VrefLevel, u2VrefBegin = 0, u2VrefEnd = 0, u2VrefStep; |
| 7999 | U16 u2TempWinSum, u2MaxWindowSum = 0;//, u2tx_window_sum[LP4_TX_VREF_DATA_NUM]={0}; |
| 8000 | //U32 u4TempRegValue; |
| 8001 | U8 u1min_bit, u1min_winsize = 0; |
| 8002 | U8 u1VrefIdx = 0; |
| 8003 | U8 u1PIDiff; |
| 8004 | PASS_WIN_DATA_BY_VREF_T VrefInfo[LP4_TX_VREF_DATA_NUM]; |
| 8005 | |
| 8006 | if (!p) |
| 8007 | { |
| 8008 | mcSHOW_ERR_MSG(("context NULL\n")); |
| 8009 | return DRAM_FAIL; |
| 8010 | } |
| 8011 | |
| 8012 | #if TX_AUTO_K_SUPPORT |
| 8013 | U8 u1PI_Len, u1dq_shift; |
| 8014 | U32 PwMaxInitReg[4] = {DRAMC_REG_TX_ATK_RESULT0, DRAMC_REG_TX_ATK_RESULT1, DRAMC_REG_TX_ATK_RESULT2, DRAMC_REG_TX_ATK_RESULT3}; |
| 8015 | U32 PwMaxLenReg[4] = {DRAMC_REG_TX_ATK_RESULT4, DRAMC_REG_TX_ATK_RESULT5, DRAMC_REG_TX_ATK_RESULT6, DRAMC_REG_TX_ATK_RESULT7}; |
| 8016 | U32 u4Length = 0; |
| 8017 | #if TX_AUTO_K_WORKAROUND |
| 8018 | U8 u1backup_Rank = 0; |
| 8019 | #endif |
| 8020 | #if TX_AUTO_K_WORKAROUND |
| 8021 | U32 u4RegBackupAddress[] = |
| 8022 | { |
| 8023 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)), |
| 8024 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)), |
| 8025 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)), |
| 8026 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)), |
| 8027 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)), |
| 8028 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)), |
| 8029 | }; |
| 8030 | #endif |
| 8031 | #endif |
| 8032 | #if 0 |
| 8033 | if(0)//(p->channel==CHANNEL_D) |
| 8034 | { |
| 8035 | ucdq_reg_ui_large[0] = ucdq_reg_ui_large[1] = 2; |
| 8036 | ucdq_reg_ui_small[0] = ucdq_reg_ui_small[1] = 1; |
| 8037 | ucdq_reg_oen_ui_large[0] = ucdq_reg_oen_ui_large[1] = 1; |
| 8038 | ucdq_reg_oen_ui_small[0] = ucdq_reg_oen_ui_small[1] = 6; |
| 8039 | ucdq_reg_pi[0] = ucdq_reg_pi[1] = 20; |
| 8040 | |
| 8041 | |
| 8042 | ucdq_reg_dqm_ui_large[0] = ucdq_reg_dqm_ui_large[1] = 2; |
| 8043 | ucdq_reg_dqm_ui_small[0] = ucdq_reg_dqm_ui_small[1] = 1; |
| 8044 | ucdq_reg_dqm_oen_ui_large[0] = ucdq_reg_dqm_oen_ui_large[1] = 1; |
| 8045 | ucdq_reg_dqm_oen_ui_small[0] = ucdq_reg_dqm_oen_ui_small[1] = 6; |
| 8046 | ucdq_reg_dqm_pi[0] = ucdq_reg_dqm_pi[1] = 20; |
| 8047 | |
| 8048 | TXSetDelayReg_DQ(p, TRUE, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi); |
| 8049 | TXSetDelayReg_DQM(p, TRUE, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi); |
| 8050 | return; |
| 8051 | } |
| 8052 | #endif |
| 8053 | //mcDUMP_REG_MSG(("\n[dumpRG] DramcTxWindowPerbitCal\n")); |
| 8054 | #if VENDER_JV_LOG |
| 8055 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) |
| 8056 | vPrintCalibrationBasicInfo_ForJV(p); |
| 8057 | #else |
| 8058 | vPrintCalibrationBasicInfo(p); |
| 8059 | #endif |
| 8060 | mcSHOW_DBG_MSG(("[TxWindowPerbitCal] caltype:%d Autok:%d\n", calType, isAutoK)); |
| 8061 | |
| 8062 | backup_rank = u1GetRank(p); |
| 8063 | |
| 8064 | TXPerbitCalibrationInit(p, calType); |
| 8065 | TXScanRange_PI(p, calType, &u2DQDelayBegin, &u2DQDelayEnd); |
| 8066 | TXScanRange_Vref(p, u1VrefScanEnable, &u2FinalRange, &u2VrefBegin, &u2VrefEnd, &u2VrefStep); |
| 8067 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8068 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8069 | vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_FAIL); |
| 8070 | |
| 8071 | if (isAutoK) |
| 8072 | { |
| 8073 | #if TX_AUTO_K_SUPPORT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8074 | //CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8075 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8076 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8077 | u1UpdateRegUI = 1; |
| 8078 | uiDelay = u2DQDelayBegin; |
| 8079 | u1PI_Len = 3; |
| 8080 | TxWinTransferDelayToUIPI(p, uiDelay, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); |
| 8081 | |
| 8082 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 8083 | { |
| 8084 | if (u1UpdateRegUI) |
| 8085 | { |
| 8086 | ucdq_reg_ui_large[u1ByteIdx] = ucdq_ui_large; |
| 8087 | ucdq_reg_ui_small[u1ByteIdx] = ucdq_ui_small; |
| 8088 | ucdq_reg_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; |
| 8089 | ucdq_reg_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; |
| 8090 | |
| 8091 | ucdq_reg_dqm_ui_large[u1ByteIdx] = ucdq_ui_large; |
| 8092 | ucdq_reg_dqm_ui_small[u1ByteIdx] = ucdq_ui_small; |
| 8093 | ucdq_reg_dqm_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; |
| 8094 | ucdq_reg_dqm_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; |
| 8095 | } |
| 8096 | |
| 8097 | ucdq_reg_pi[u1ByteIdx] = ucdq_pi; |
| 8098 | ucdq_reg_dqm_pi[u1ByteIdx] = ucdq_pi; |
| 8099 | } |
| 8100 | |
| 8101 | #if TX_AUTO_K_WORKAROUND |
| 8102 | if (p->rank == 1) |
| 8103 | { |
| 8104 | u1backup_Rank = 1; |
| 8105 | p->rank = 0; |
| 8106 | DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 8107 | } |
| 8108 | #endif |
| 8109 | |
| 8110 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 8111 | { |
| 8112 | TXSetDelayReg_DQ(p, u1UpdateRegUI, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi); |
| 8113 | mcSHOW_DBG_MSG2(("TX Auto-K set begin delay DQ MCK: %d, UI: %d, PI: %d\n", ucdq_reg_ui_large[0], ucdq_reg_ui_small[0], ucdq_reg_pi[0])); |
| 8114 | |
| 8115 | #if TX_AUTO_K_WORKAROUND |
| 8116 | if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1backup_Rank == 1)) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8117 | Tx_Auto_K_DQM_Workaround(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8118 | #endif |
| 8119 | } |
| 8120 | if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 8121 | { |
| 8122 | TXSetDelayReg_DQM(p, u1UpdateRegUI, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi); |
| 8123 | |
| 8124 | mcSHOW_DBG_MSG2(("TX Auto-K set begin delay DQM MCK: %d, UI: %d, PI: %d\n", ucdq_reg_dqm_ui_large[0], ucdq_reg_dqm_ui_small[0], ucdq_reg_dqm_pi[0])); |
| 8125 | |
| 8126 | #if TX_AUTO_K_WORKAROUND |
| 8127 | if ((calType == TX_DQ_DQS_MOVE_DQM_ONLY) && (u1backup_Rank == 1)) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8128 | Tx_Auto_K_DQ_Workaround(p); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8129 | #endif |
| 8130 | } |
| 8131 | |
| 8132 | #if TX_AUTO_K_WORKAROUND |
| 8133 | if (u1backup_Rank == 1) |
| 8134 | p->rank = 1; |
| 8135 | #endif |
| 8136 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8137 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8138 | #endif |
| 8139 | } |
| 8140 | else |
| 8141 | { |
| 8142 | if (vGet_DDR_Loop_Mode(p) == SEMI_OPEN_LOOP_MODE) |
| 8143 | u2DQDelayStep = (1 << 3); |
| 8144 | else if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) |
| 8145 | u2DQDelayStep = (1 << 4); |
| 8146 | else if (calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 8147 | u2DQDelayStep = 2; |
| 8148 | else |
| 8149 | u2DQDelayStep = 1; |
Ryan Chuang | 98affb6 | 2021-09-23 20:35:22 +0800 | [diff] [blame] | 8150 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8151 | #if (FOR_DV_SIMULATION_USED == 1) |
| 8152 | u2DQDelayStep = (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE) ? 16 : 8; |
| 8153 | #endif |
| 8154 | } |
| 8155 | |
| 8156 | #if 0 |
| 8157 | mcSHOW_DBG_MSG(("[TxWindowPerbitCal] calType=%d, VrefScanEnable %d (Range %d, VrefBegin %d, u2VrefEnd %d)\n" |
| 8158 | "\nBegin, DQ Scan Range %d~%d\n", |
| 8159 | calType, u1VrefScanEnable, u2FinalRange, u2VrefBegin, u2VrefEnd, u2DQDelayBegin, u2DQDelayEnd)); |
| 8160 | #endif |
| 8161 | |
| 8162 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 8163 | if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW)) |
| 8164 | { |
| 8165 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 8166 | { |
| 8167 | u2Center_min[u1ByteIdx] = p->pSavetimeData->u1TxCenter_min_Save[p->channel][p->rank][u1ByteIdx]; |
| 8168 | u2Center_max[u1ByteIdx] = p->pSavetimeData->u1TxCenter_max_Save[p->channel][p->rank][u1ByteIdx]; |
| 8169 | |
| 8170 | for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) |
| 8171 | { |
| 8172 | u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; |
| 8173 | FinalWinPerBit[u1BitTemp].win_center = p->pSavetimeData->u1Txwin_center_Save[p->channel][p->rank][u1BitTemp]; |
| 8174 | } |
| 8175 | } |
| 8176 | vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_FAST_K); |
| 8177 | } |
| 8178 | else |
| 8179 | #endif |
| 8180 | { |
| 8181 | #if ENABLE_K_WITH_WORST_SI_UI_SHIFT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8182 | DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8183 | #else |
| 8184 | DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); |
| 8185 | #endif |
| 8186 | |
| 8187 | for (u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep) |
| 8188 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8189 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8190 | if (u1VrefScanEnable) |
| 8191 | { |
| 8192 | #if (!REDUCE_LOG_FOR_PRELOADER) |
| 8193 | mcSHOW_DBG_MSG2(("\n\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel)); |
| 8194 | #endif |
| 8195 | |
| 8196 | #if VENDER_JV_LOG |
| 8197 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) |
| 8198 | { |
| 8199 | mcSHOW_DBG_MSG5(("\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel)); |
| 8200 | } |
| 8201 | #endif |
| 8202 | |
| 8203 | DramcTXSetVref(p, u2FinalRange, u2VrefLevel); |
| 8204 | } |
| 8205 | else |
| 8206 | { |
| 8207 | mcSHOW_DBG_MSG(("\n\tTX Vref Scan disable\n")); |
| 8208 | } |
| 8209 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8210 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8211 | uiFinishCount = 0; |
| 8212 | u2TempWinSum = 0; |
| 8213 | ucdq_ui_small_reg_value = 0xff; |
| 8214 | |
| 8215 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 8216 | { |
| 8217 | WinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; |
| 8218 | WinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; |
| 8219 | VrefWinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; |
| 8220 | VrefWinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; |
| 8221 | } |
| 8222 | |
| 8223 | if (isAutoK) |
| 8224 | { |
| 8225 | #if TX_AUTO_K_SUPPORT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8226 | Tx_Auto_K_Init(p, calType, ucdq_pi, u1PI_Len); |
| 8227 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET1), 0x1, TX_ATK_SET1_TX_ATK_TRIG); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8228 | #endif |
| 8229 | } |
| 8230 | else |
| 8231 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8232 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8233 | for (uiDelay = u2DQDelayBegin; uiDelay < u2DQDelayEnd; uiDelay += u2DQDelayStep) |
| 8234 | { |
| 8235 | TxWinTransferDelayToUIPI(p, uiDelay, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); |
| 8236 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8237 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8238 | if (ucdq_ui_small_reg_value != ucdq_ui_small) |
| 8239 | { |
| 8240 | u1UpdateRegUI = 1; |
| 8241 | ucdq_ui_small_reg_value = ucdq_ui_small; |
| 8242 | } |
| 8243 | else |
| 8244 | u1UpdateRegUI = 0; |
| 8245 | |
| 8246 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 8247 | { |
| 8248 | if (u1UpdateRegUI) |
| 8249 | { |
| 8250 | ucdq_reg_ui_large[u1ByteIdx] = ucdq_ui_large; |
| 8251 | ucdq_reg_ui_small[u1ByteIdx] = ucdq_ui_small; |
| 8252 | ucdq_reg_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; |
| 8253 | ucdq_reg_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; |
| 8254 | |
| 8255 | ucdq_reg_dqm_ui_large[u1ByteIdx] = ucdq_ui_large; |
| 8256 | ucdq_reg_dqm_ui_small[u1ByteIdx] = ucdq_ui_small; |
| 8257 | ucdq_reg_dqm_oen_ui_large[u1ByteIdx] = ucdq_oen_ui_large; |
| 8258 | ucdq_reg_dqm_oen_ui_small[u1ByteIdx] = ucdq_oen_ui_small; |
| 8259 | } |
| 8260 | |
| 8261 | ucdq_reg_pi[u1ByteIdx] = ucdq_pi; |
| 8262 | ucdq_reg_dqm_pi[u1ByteIdx] = ucdq_pi; |
| 8263 | } |
| 8264 | |
| 8265 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 8266 | { |
| 8267 | TXSetDelayReg_DQ(p, u1UpdateRegUI, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi); |
| 8268 | } |
| 8269 | |
| 8270 | if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 8271 | { |
| 8272 | TXSetDelayReg_DQM(p, u1UpdateRegUI, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi); |
| 8273 | } |
| 8274 | |
| 8275 | u4err_value = 0; |
| 8276 | #if ENABLE_K_WITH_WORST_SI_UI_SHIFT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8277 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8278 | u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); |
| 8279 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8280 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8281 | DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); |
| 8282 | u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); |
| 8283 | DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); |
| 8284 | u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); |
| 8285 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8286 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8287 | |
| 8288 | if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY)) |
| 8289 | { |
| 8290 | //mcSHOW_DBG_MSG(("Delay=%3d |%2d %2d %3d| %2d %2d| 0x%8x [0]",uiDelay, ucdq_ui_large,ucdq_ui_small, ucdq_pi, ucdq_oen_ui_large,ucdq_oen_ui_small, u4err_value)); |
| 8291 | #ifdef ETT_PRINT_FORMAT |
| 8292 | if (u4err_value != 0) |
| 8293 | { |
| 8294 | mcSHOW_DBG_MSG3(("%d |%d %d %d|[0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi)); |
| 8295 | } |
| 8296 | #else |
| 8297 | mcSHOW_DBG_MSG3(("Delay=%3d |%2d %2d %3d| 0x%8x [0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi, u4err_value)); |
| 8298 | #endif |
| 8299 | } |
| 8300 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8301 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8302 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 8303 | { |
| 8304 | u4fail_bit = u4err_value & ((U32)1 << u1BitIdx); |
| 8305 | |
| 8306 | if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY)) |
| 8307 | { |
| 8308 | if(u4err_value != 0) |
| 8309 | { |
| 8310 | if (u1BitIdx % DQS_BIT_NUMBER == 0) |
| 8311 | { |
| 8312 | mcSHOW_DBG_MSG3((" ")); |
| 8313 | } |
| 8314 | |
| 8315 | if (u4fail_bit == 0) |
| 8316 | { |
| 8317 | mcSHOW_DBG_MSG3(("o")); |
| 8318 | } |
| 8319 | else |
| 8320 | { |
| 8321 | mcSHOW_DBG_MSG3(("x")); |
| 8322 | } |
| 8323 | } |
| 8324 | } |
| 8325 | |
| 8326 | if (WinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA) |
| 8327 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8328 | if (u4fail_bit == 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8329 | { |
| 8330 | WinPerBit[u1BitIdx].first_pass = uiDelay; |
| 8331 | |
| 8332 | #if TX_TDQS2DQ_PRE_CAL |
| 8333 | if ((u1IsLP4Div4DDR800(p) == FALSE) && (calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1VrefScanEnable == FALSE)) |
| 8334 | { |
| 8335 | if (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] == 0) |
| 8336 | { |
| 8337 | u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] = ((uiDelay - u2DQDelayBegin)* 1000) / p->frequency; |
| 8338 | } |
| 8339 | |
| 8340 | if (uiDelay == u2DQDelayBegin) |
| 8341 | { |
| 8342 | mcSHOW_ERR_MSG(("TX_TDQS2DQ_PRE_CAL: Warning, possible miss TX window boundary\n")); |
| 8343 | #if __ETT__ |
| 8344 | while (1); |
| 8345 | #endif |
| 8346 | } |
| 8347 | } |
| 8348 | #endif |
| 8349 | } |
| 8350 | } |
| 8351 | else if (WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA) |
| 8352 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8353 | if (u4fail_bit != 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8354 | { |
| 8355 | WinPerBit[u1BitIdx].last_pass = uiDelay - u2DQDelayStep; |
| 8356 | } |
| 8357 | else if (uiDelay >= (u2DQDelayEnd - u2DQDelayStep)) |
| 8358 | { |
| 8359 | WinPerBit[u1BitIdx].last_pass = uiDelay; |
| 8360 | mcSHOW_ERR_MSG(("\nTx last pass not found!!\n")); |
| 8361 | #if __ETT__ |
| 8362 | while(1); |
| 8363 | #endif |
| 8364 | } |
| 8365 | |
| 8366 | if (WinPerBit[u1BitIdx].last_pass != PASS_RANGE_NA) |
| 8367 | { |
| 8368 | if ((WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass) >= (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass)) |
| 8369 | { |
| 8370 | if ((VrefWinPerBit[u1BitIdx].last_pass != PASS_RANGE_NA) && (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass) > 0) |
| 8371 | { |
| 8372 | mcSHOW_DBG_MSG2(("Bit[%d] Bigger window update %d > %d, window broken?\n", u1BitIdx, \ |
| 8373 | (WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass), (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass))); |
| 8374 | } |
| 8375 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8376 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8377 | if (((WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass) > TX_PASS_WIN_CRITERIA) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8378 | ||((u2DQDelayStep>=16) && (WinPerBit[u1BitIdx].first_pass!=PASS_RANGE_NA))) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8379 | uiFinishCount |= (1 << u1BitIdx); |
| 8380 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8381 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8382 | VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass; |
| 8383 | VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass; |
| 8384 | } |
| 8385 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8386 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8387 | WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA; |
| 8388 | WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA; |
| 8389 | } |
| 8390 | } |
| 8391 | } |
| 8392 | |
| 8393 | if(u1VrefScanEnable==0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY)) |
| 8394 | { |
| 8395 | if(u4err_value != 0) |
| 8396 | { |
| 8397 | mcSHOW_DBG_MSG3((" [MSB]\n")); |
| 8398 | } |
| 8399 | } |
| 8400 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8401 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8402 | if (uiFinishCount == 0xffff) |
| 8403 | { |
| 8404 | vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK); |
| 8405 | #if !REDUCE_LOG_FOR_PRELOADER |
| 8406 | #ifdef ETT_PRINT_FORMAT |
| 8407 | mcSHOW_DBG_MSG3(("TX calibration finding left boundary early break. PI DQ delay=0x%B\n", uiDelay)); |
| 8408 | #else |
| 8409 | mcSHOW_DBG_MSG3(("TX calibration finding left boundary early break. PI DQ delay=0x%2x\n", uiDelay)); |
| 8410 | #endif |
| 8411 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8412 | break; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8413 | } |
| 8414 | } |
| 8415 | } |
| 8416 | |
| 8417 | if (isAutoK) |
| 8418 | { |
| 8419 | #if TX_AUTO_K_SUPPORT |
| 8420 | Tx_Auto_K_complete_check(p); |
| 8421 | #if TX_AUTO_K_DEBUG_ENABLE |
| 8422 | Tx_Auto_K_Debug_Message(p, u1PI_Len); |
| 8423 | #endif |
| 8424 | #endif |
| 8425 | } |
| 8426 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8427 | u1min_winsize = 0xff; |
| 8428 | u1min_bit = 0xff; |
| 8429 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 8430 | { |
| 8431 | if (isAutoK) |
| 8432 | { |
| 8433 | #if TX_AUTO_K_SUPPORT |
| 8434 | u1dq_shift = ((u1BitIdx % 4) * 8); |
| 8435 | VrefWinPerBit[u1BitIdx].first_pass = u2DQDelayBegin - ucdq_pi + ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxInitReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift); |
| 8436 | VrefWinPerBit[u1BitIdx].last_pass = ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxLenReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift) + VrefWinPerBit[u1BitIdx].first_pass; |
| 8437 | VrefWinPerBit[u1BitIdx].win_size = ((u4IO32Read4B(DRAMC_REG_ADDR(PwMaxLenReg[u1BitIdx / 4])) & (0xff << u1dq_shift)) >> u1dq_shift); |
| 8438 | |
| 8439 | if (u1PI_Len == 0) |
| 8440 | u4Length = 48; |
| 8441 | else |
| 8442 | u4Length = 32 * (1 + u1PI_Len); |
| 8443 | |
| 8444 | if ((VrefWinPerBit[u1BitIdx].first_pass == (int)(u2DQDelayBegin - ucdq_pi)) || (VrefWinPerBit[u1BitIdx].last_pass == (int)(u2DQDelayBegin + u4Length))) |
| 8445 | { |
| 8446 | mcSHOW_ERR_MSG(("Error! Probably miss pass window!\n")); |
| 8447 | } |
| 8448 | |
| 8449 | mcSHOW_DBG_MSG(("TX DQ bit %d, first pass: %d, last pass: %d\n", u1BitIdx, VrefWinPerBit[u1BitIdx].first_pass, VrefWinPerBit[u1BitIdx].last_pass)); |
| 8450 | #else |
| 8451 | //if(VrefWinPerBit[u1BitIdx].last_pass == VrefWinPerBit[u1BitIdx].first_pass) |
| 8452 | if (VrefWinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA) |
| 8453 | VrefWinPerBit[u1BitIdx].win_size = 0; |
| 8454 | else |
| 8455 | VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass + u2DQDelayStep; |
| 8456 | #endif |
| 8457 | } |
| 8458 | else |
| 8459 | { |
| 8460 | if (VrefWinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA) |
| 8461 | VrefWinPerBit[u1BitIdx].win_size = 0; |
| 8462 | else |
| 8463 | VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass + u2DQDelayStep; |
| 8464 | } |
| 8465 | |
| 8466 | if (VrefWinPerBit[u1BitIdx].win_size < u1min_winsize) |
| 8467 | { |
| 8468 | u1min_bit = u1BitIdx; |
| 8469 | u1min_winsize = VrefWinPerBit[u1BitIdx].win_size; |
| 8470 | } |
| 8471 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8472 | u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8473 | |
| 8474 | #if VENDER_JV_LOG |
| 8475 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) |
| 8476 | { |
| 8477 | mcSHOW_DBG_MSG5(("TX Bit%d, %d%%\n", u1BitIdx, (VrefWinPerBit[u1BitIdx].win_size * 100 + 31) / 32)); |
| 8478 | } |
| 8479 | #endif |
| 8480 | |
| 8481 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8482 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8483 | VrefWinPerBit[u1BitIdx].win_center = (VrefWinPerBit[u1BitIdx].first_pass + VrefWinPerBit[u1BitIdx].last_pass) >> 1; |
| 8484 | #if PINMUX_AUTO_TEST_PER_BIT_TX |
| 8485 | gFinalTXPerbitFirstPass[p->channel][u1BitIdx] = VrefWinPerBit[u1BitIdx].first_pass; |
| 8486 | #endif |
| 8487 | } |
| 8488 | |
| 8489 | |
| 8490 | #if (__ETT__ || PIN_CHECK_TOOL) |
| 8491 | if (u1VrefScanEnable == 0) |
| 8492 | { |
| 8493 | //mcSHOW_DBG_MSG(("\n\tCH=%d, VrefRange= %d, VrefLevel = %d\n", p->channel, u2FinalRange, u2VrefLevel)); |
| 8494 | TxPrintWidnowInfo(p, VrefWinPerBit); |
| 8495 | } |
| 8496 | #endif |
| 8497 | |
| 8498 | if (u1VrefScanEnable == 1) |
| 8499 | { |
| 8500 | if (u2TempWinSum > u2MaxWindowSum) |
| 8501 | u2MaxWindowSum = u2TempWinSum; |
| 8502 | |
| 8503 | VrefInfo[u1VrefIdx].u2VrefUsed = u2VrefLevel; |
| 8504 | VrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref = u1min_winsize; |
| 8505 | VrefInfo[u1VrefIdx].u1WorseBitIdx_byVref = u1min_bit; |
| 8506 | VrefInfo[u1VrefIdx].u2WinSum_byVref = u2TempWinSum; |
| 8507 | u1VrefIdx ++; |
| 8508 | } |
| 8509 | |
| 8510 | #if TX_AUTO_K_SUPPORT |
| 8511 | if (isAutoK) |
| 8512 | Tx_Auto_K_Clear(p); |
| 8513 | #endif |
| 8514 | |
| 8515 | #if LP4_TX_VREF_PASS_CONDITION |
| 8516 | if (u1VrefScanEnable && (u2TempWinSum < (u2MaxWindowSum * 95 / 100)) && (u1min_winsize < LP4_TX_VREF_PASS_CONDITION)) |
| 8517 | #else |
| 8518 | if (u1VrefScanEnable && (u2TempWinSum < (u2MaxWindowSum * 95 / 100)) && (u1min_winsize > TX_PASS_WIN_CRITERIA)) |
| 8519 | #endif |
| 8520 | { |
| 8521 | mcSHOW_DBG_MSG(("\nTX Vref early break, caculate TX vref\n")); |
| 8522 | break; |
| 8523 | } |
| 8524 | |
| 8525 | #if TX_AUTO_K_SUPPORT |
| 8526 | Tx_Auto_K_Clear(p); |
| 8527 | #endif |
| 8528 | } |
| 8529 | |
| 8530 | DramcEngine2End(p); |
| 8531 | |
| 8532 | #if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND) |
| 8533 | if ((isAutoK) && (p->rank == RANK_1)) |
| 8534 | { |
| 8535 | vSetRank(p, RANK_0); |
| 8536 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 8537 | vSetRank(p, backup_rank); |
| 8538 | } |
| 8539 | #endif |
| 8540 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8541 | if (u1VrefScanEnable == 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8542 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8543 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8544 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 8545 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8546 | #if 1 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8547 | u2Center_min[u1ByteIdx] = 0xffff; |
| 8548 | u2Center_max[u1ByteIdx] = 0; |
| 8549 | #endif |
| 8550 | |
| 8551 | for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) |
| 8552 | { |
| 8553 | u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; |
| 8554 | memcpy(FinalWinPerBit, VrefWinPerBit, sizeof(PASS_WIN_DATA_T) * DQ_DATA_WIDTH); |
| 8555 | |
| 8556 | if (FinalWinPerBit[u1BitTemp].win_center < u2Center_min[u1ByteIdx]) |
| 8557 | u2Center_min[u1ByteIdx] = FinalWinPerBit[u1BitTemp].win_center; |
| 8558 | |
| 8559 | if (FinalWinPerBit[u1BitTemp].win_center > u2Center_max[u1ByteIdx]) |
| 8560 | u2Center_max[u1ByteIdx] = FinalWinPerBit[u1BitTemp].win_center; |
| 8561 | |
| 8562 | #ifdef FOR_HQA_TEST_USED |
| 8563 | if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1VrefScanEnable == 0)) |
| 8564 | { |
| 8565 | gFinalTXPerbitWin[p->channel][p->rank][u1BitTemp] = FinalWinPerBit[u1BitTemp].win_size; |
| 8566 | } |
| 8567 | #endif |
| 8568 | } |
| 8569 | } |
| 8570 | } |
| 8571 | } |
| 8572 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8573 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8574 | if (u1VrefScanEnable) |
| 8575 | { |
| 8576 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_VREF_CAL |
| 8577 | if (p->femmc_Ready == 1 && (p->Bypass_TXWINDOW)) |
| 8578 | { |
| 8579 | u2FinalVref = p->pSavetimeData->u1TxWindowPerbitVref_Save[p->channel][p->rank]; |
| 8580 | } |
| 8581 | else |
| 8582 | #endif |
| 8583 | { |
| 8584 | u2FinalVref = TxChooseVref(p, VrefInfo, u1VrefIdx); |
| 8585 | } |
| 8586 | |
| 8587 | TXSetFinalVref(p, u2FinalRange, u2FinalVref); |
| 8588 | return DRAM_OK; |
| 8589 | } |
| 8590 | |
| 8591 | #ifdef FOR_HQA_TEST_USED |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8592 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8593 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) |
| 8594 | { |
| 8595 | gFinalTXPerbitWin_min_max[p->channel][p->rank] = u1min_winsize; |
| 8596 | if(u1min_winsize<16) |
| 8597 | { |
| 8598 | mcSHOW_ERR_MSG(("[WARNING] Smaller TX win !!\n")); |
| 8599 | #if CHECK_HQA_CRITERIA |
| 8600 | while(1); |
| 8601 | #endif |
| 8602 | } |
| 8603 | } |
| 8604 | #endif |
| 8605 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8606 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8607 | if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (p->frequency >= 1333) && (p->u2DelayCellTimex100 != 0)) |
| 8608 | { |
| 8609 | u1EnableDelayCell = 1; |
| 8610 | mcSHOW_DBG_MSG(("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100)); |
| 8611 | //mcDUMP_REG_MSG(("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100)); |
| 8612 | } |
| 8613 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8614 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8615 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 8616 | { |
| 8617 | mcSHOW_DBG_MSG((" == TX Byte %d ==\n", u1ByteIdx)); |
| 8618 | //mcDUMP_REG_MSG((" == TX Byte %d ==\n", u1ByteIdx)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8619 | u2DQM_Delay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx]) >> 1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8620 | |
| 8621 | if (u1EnableDelayCell == 0) |
| 8622 | { |
| 8623 | uiDelay = u2DQM_Delay; |
| 8624 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8625 | else |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8626 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8627 | uiDelay = u2Center_min[u1ByteIdx]; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8628 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8629 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8630 | for (u1BitIdx = 0; u1BitIdx < DQS_BIT_NUMBER; u1BitIdx++) |
| 8631 | { |
| 8632 | u1BitTemp = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; |
| 8633 | u1PIDiff = FinalWinPerBit[u1BitTemp].win_center - u2Center_min[u1ByteIdx]; |
| 8634 | if (p->u2DelayCellTimex100 != 0) |
| 8635 | { |
| 8636 | u2DelayCellOfst[u1BitTemp] = (u1PIDiff * 100000000 / (DDRPhyGetRealFreq(p)<< 6)) / p->u2DelayCellTimex100; |
| 8637 | mcSHOW_DBG_MSG(("u2DelayCellOfst[%d]=%d cells (%d PI)\n", u1BitTemp, u2DelayCellOfst[u1BitTemp], u1PIDiff)); |
| 8638 | //mcDUMP_REG_MSG(("u2DelayCellOfst[%d]=%d cells (%d PI)\n", u1BitTemp, u2DelayCellOfst[u1BitTemp], u1PIDiff)); |
| 8639 | |
| 8640 | |
| 8641 | if(u2DelayCellOfst[u1BitTemp]>255) |
| 8642 | { |
| 8643 | mcSHOW_DBG_MSG(("[WARNING] TX DQ%d delay cell %d >255, adjust to 255 cell\n", u1BitIdx, u2DelayCellOfst[u1BitTemp])); |
| 8644 | u2DelayCellOfst[u1BitTemp] =255; |
| 8645 | } |
| 8646 | } |
| 8647 | else |
| 8648 | { |
| 8649 | mcSHOW_ERR_MSG(("Error: Cell time (p->u2DelayCellTimex100) is 0 \n")); |
| 8650 | break; |
| 8651 | } |
| 8652 | } |
| 8653 | |
| 8654 | } |
| 8655 | |
| 8656 | TxWinTransferDelayToUIPI(p, uiDelay, 1, &ucdq_reg_ui_large[u1ByteIdx], &ucdq_reg_ui_small[u1ByteIdx], &ucdq_reg_pi[u1ByteIdx], \ |
| 8657 | &ucdq_reg_oen_ui_large[u1ByteIdx], &ucdq_reg_oen_ui_small[u1ByteIdx]); |
| 8658 | |
| 8659 | TxWinTransferDelayToUIPI(p, u2DQM_Delay, 1, &ucdq_reg_dqm_ui_large[u1ByteIdx], &ucdq_reg_dqm_ui_small[u1ByteIdx], &ucdq_reg_dqm_pi[u1ByteIdx], \ |
| 8660 | &ucdq_reg_dqm_oen_ui_large[u1ByteIdx], &ucdq_reg_dqm_oen_ui_small[u1ByteIdx]); |
| 8661 | |
| 8662 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 8663 | { |
| 8664 | mcSHOW_DBG_MSG(("Update DQ dly =%d (%d ,%d, %d) DQ OEN =(%d ,%d)\n", |
| 8665 | uiDelay, ucdq_reg_ui_large[u1ByteIdx], ucdq_reg_ui_small[u1ByteIdx], ucdq_reg_pi[u1ByteIdx], \ |
| 8666 | ucdq_reg_oen_ui_large[u1ByteIdx], ucdq_reg_oen_ui_small[u1ByteIdx])); |
| 8667 | /*mcDUMP_REG_MSG(("Update DQ dly =%d (%d ,%d, %d) DQ OEN =(%d ,%d)\n", |
| 8668 | uiDelay, ucdq_reg_ui_large[u1ByteIdx], ucdq_reg_ui_small[u1ByteIdx], ucdq_reg_pi[u1ByteIdx], \ |
| 8669 | ucdq_reg_oen_ui_large[u1ByteIdx], ucdq_reg_oen_ui_small[u1ByteIdx]));*/ |
| 8670 | } |
| 8671 | |
| 8672 | //if(calType ==TX_DQ_DQS_MOVE_DQM_ONLY || calType== TX_DQ_DQS_MOVE_DQ_DQM) |
| 8673 | { |
| 8674 | mcSHOW_DBG_MSG(("Update DQM dly =%d (%d ,%d, %d) DQM OEN =(%d ,%d)\n", |
| 8675 | u2DQM_Delay, ucdq_reg_dqm_ui_large[u1ByteIdx], ucdq_reg_dqm_ui_small[u1ByteIdx], ucdq_reg_dqm_pi[u1ByteIdx], \ |
| 8676 | ucdq_reg_dqm_oen_ui_large[u1ByteIdx], ucdq_reg_dqm_oen_ui_small[u1ByteIdx])); |
| 8677 | /*mcDUMP_REG_MSG(("Update DQM dly =%d (%d ,%d, %d) DQM OEN =(%d ,%d)\n", |
| 8678 | u2DQM_Delay, ucdq_reg_dqm_ui_large[u1ByteIdx], ucdq_reg_dqm_ui_small[u1ByteIdx], ucdq_reg_dqm_pi[u1ByteIdx], \ |
| 8679 | ucdq_reg_dqm_oen_ui_large[u1ByteIdx], ucdq_reg_dqm_oen_ui_small[u1ByteIdx]));*/ |
| 8680 | } |
| 8681 | mcSHOW_DBG_MSG(("\n")); |
| 8682 | |
| 8683 | #ifdef FOR_HQA_REPORT_USED |
| 8684 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY) |
| 8685 | { |
| 8686 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "BYTE", u1ByteIdx, uiDelay, NULL); |
| 8687 | |
| 8688 | for (u1BitIdx = u1ByteIdx*8; u1BitIdx < u1ByteIdx*8+8; u1BitIdx++) |
| 8689 | { |
| 8690 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "DQ", u1BitIdx, FinalWinPerBit[u1BitIdx].win_center, NULL); |
| 8691 | } |
| 8692 | } |
| 8693 | |
| 8694 | #if TX_K_DQM_WITH_WDBI |
| 8695 | if ((p->DBI_W_onoff[p->dram_fsp]!=DBI_ON)) |
| 8696 | { |
| 8697 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY && u1VrefScanEnable == FALSE) |
| 8698 | { |
| 8699 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "DQM", u1ByteIdx, u2DQM_Delay, NULL); |
| 8700 | } |
| 8701 | } |
| 8702 | else |
| 8703 | { |
| 8704 | if (calType == TX_DQ_DQS_MOVE_DQM_ONLY) |
| 8705 | { |
| 8706 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "DQM", u1ByteIdx, u2DQM_Delay, NULL); |
| 8707 | } |
| 8708 | } |
| 8709 | #else |
| 8710 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY && u1VrefScanEnable == FALSE) |
| 8711 | { |
| 8712 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "DQM", u1ByteIdx, u2DQM_Delay, NULL); |
| 8713 | } |
| 8714 | #endif |
| 8715 | |
| 8716 | |
| 8717 | #if 0 |
| 8718 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT1, "TX_Window_Center_", "LargeUI", u1ByteIdx, ucdq_reg_ui_large[u1ByteIdx], NULL); |
| 8719 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "SmallUI", u1ByteIdx, ucdq_reg_ui_small[u1ByteIdx], NULL); |
| 8720 | HQA_Log_Message_for_Report(p, p->channel, p->rank, HQA_REPORT_FORMAT0, "TX_Window_Center_", "PI", u1ByteIdx, ucdq_reg_pi[u1ByteIdx], NULL); |
| 8721 | #endif |
| 8722 | #endif |
| 8723 | |
| 8724 | } |
| 8725 | |
| 8726 | |
| 8727 | #if REG_ACCESS_PORTING_DGB |
| 8728 | RegLogEnable = 1; |
| 8729 | #endif |
| 8730 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8731 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8732 | for (u1RankIdx = p->rank; u1RankIdx < RANK_MAX; u1RankIdx++) |
| 8733 | { |
| 8734 | vSetRank(p, u1RankIdx); |
| 8735 | |
| 8736 | if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM) |
| 8737 | { |
| 8738 | TXSetDelayReg_DQ(p, TRUE, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi); |
| 8739 | } |
| 8740 | |
| 8741 | TXSetDelayReg_DQM(p, TRUE, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi); |
| 8742 | |
| 8743 | if (u1EnableDelayCell) |
| 8744 | { |
| 8745 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY0), |
| 8746 | P_Fld(u2DelayCellOfst[3], SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0) |
| 8747 | | P_Fld(u2DelayCellOfst[2], SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0) |
| 8748 | | P_Fld(u2DelayCellOfst[1], SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0) |
| 8749 | | P_Fld(u2DelayCellOfst[0], SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0)); |
| 8750 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_TXDLY1), |
| 8751 | P_Fld(u2DelayCellOfst[7], SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0) |
| 8752 | | P_Fld(u2DelayCellOfst[6], SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0) |
| 8753 | | P_Fld(u2DelayCellOfst[5], SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0) |
| 8754 | | P_Fld(u2DelayCellOfst[4], SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0)); |
| 8755 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY0), |
| 8756 | P_Fld(u2DelayCellOfst[11], SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1) |
| 8757 | | P_Fld(u2DelayCellOfst[10], SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1) |
| 8758 | | P_Fld(u2DelayCellOfst[9], SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1) |
| 8759 | | P_Fld(u2DelayCellOfst[8], SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1)); |
| 8760 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_TXDLY1), |
| 8761 | P_Fld(u2DelayCellOfst[15], SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1) |
| 8762 | | P_Fld(u2DelayCellOfst[14], SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1) |
| 8763 | | P_Fld(u2DelayCellOfst[13], SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1) |
| 8764 | | P_Fld(u2DelayCellOfst[12], SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1)); |
| 8765 | } |
| 8766 | #if ENABLE_TX_TRACKING |
| 8767 | TXUpdateTXTracking(p, calType, ucdq_reg_pi, ucdq_reg_dqm_pi); |
| 8768 | #endif |
| 8769 | } |
| 8770 | |
| 8771 | vSetRank(p, backup_rank); |
| 8772 | |
| 8773 | if (isAutoK) |
| 8774 | { |
| 8775 | #if TX_AUTO_K_SUPPORT |
| 8776 | #if TX_AUTO_K_WORKAROUND |
| 8777 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_SET0), |
| 8778 | P_Fld(ucdq_reg_pi[0], TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT) | |
| 8779 | P_Fld(ucdq_reg_pi[1], TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT) | |
| 8780 | P_Fld(ucdq_reg_dqm_pi[0], TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT) | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8781 | P_Fld(ucdq_reg_dqm_pi[1], TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT)); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8782 | #endif |
| 8783 | #endif |
| 8784 | } |
| 8785 | |
| 8786 | #if REG_ACCESS_PORTING_DGB |
| 8787 | RegLogEnable = 0; |
| 8788 | #endif |
| 8789 | |
| 8790 | #if (TX_AUTO_K_SUPPORT && TX_AUTO_K_WORKAROUND) |
| 8791 | if ((isAutoK) && (p->rank == RANK_1) && (calType == TX_DQ_DQS_MOVE_DQ_DQM)) |
| 8792 | { |
| 8793 | u4DQM_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)); |
| 8794 | u4DQM_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)); |
| 8795 | u4DQM_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)); |
| 8796 | u4DQM_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)); |
| 8797 | u4DQ_MCK_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)); |
| 8798 | u4DQ_UI_RK1_backup = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)); |
| 8799 | u4DQ_PI_RK1_backup[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)); |
| 8800 | u4DQ_PI_RK1_backup[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)); |
| 8801 | } |
| 8802 | #endif |
| 8803 | |
| 8804 | mcSHOW_DBG_MSG4(("[TxWindowPerbitCal] Done\n\n")); |
| 8805 | |
| 8806 | #if 0 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8807 | vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_PADCTL4), 1, PADCTL4_CKEFIXON); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8808 | #endif |
| 8809 | |
| 8810 | return DRAM_OK; |
| 8811 | } |
| 8812 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8813 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8814 | |
| 8815 | #if ENABLE_EYESCAN_GRAPH |
| 8816 | void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p) |
| 8817 | { |
| 8818 | U8 ucindex, u1BitIdx, u1ByteIdx; |
| 8819 | U8 ii, backup_rank, u1PrintWinData, u1vrefidx; |
| 8820 | PASS_WIN_DATA_T WinPerBit[DQ_DATA_WIDTH], VrefWinPerBit[DQ_DATA_WIDTH], FinalWinPerBit[DQ_DATA_WIDTH]; |
| 8821 | U16 tx_pi_delay[4], tx_dqm_pi_delay[4]; |
| 8822 | U16 u2DQDelayBegin, uiDelay; |
| 8823 | U16 u2VrefLevel, u2VrefBegin, u2VrefEnd, u2VrefStep, u2VrefRange; |
| 8824 | U8 ucdq_pi, ucdq_ui_small, ucdq_ui_large,ucdq_oen_ui_small, ucdq_oen_ui_large; |
| 8825 | U32 uiFinishCount; |
| 8826 | U16 u2TempWinSum, u2tx_window_sum=0; |
| 8827 | U32 u4err_value, u4fail_bit; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8828 | #if 1 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8829 | U16 u2Center_min[DQS_BYTE_NUMBER],u2Center_max[DQS_BYTE_NUMBER]; |
| 8830 | #endif |
| 8831 | |
| 8832 | U16 TXPerbitWin_min_max = 0; |
| 8833 | U32 min_bit, min_winsize; |
| 8834 | |
| 8835 | U16 u2FinalVref=0xd; |
| 8836 | U16 u2FinalRange=0; |
| 8837 | |
| 8838 | U8 EyeScan_index[DQ_DATA_WIDTH]; |
| 8839 | |
| 8840 | U16 backup_u1MR14Value; |
| 8841 | U8 u1pass_in_this_vref_flag[DQ_DATA_WIDTH]; |
| 8842 | |
| 8843 | U8 u1MCK2UI, u1UI2PI; |
| 8844 | |
| 8845 | U32 u4RegBackupAddress[] = |
| 8846 | { |
| 8847 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0)), |
| 8848 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2)), |
| 8849 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1)), |
| 8850 | (DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3)), |
| 8851 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0)), |
| 8852 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0)), |
| 8853 | }; |
| 8854 | |
| 8855 | //if (gTX_EYE_Scan_only_higheset_freq_flag==1 && p->frequency != u2DFSGetHighestFreq(p)) return; |
| 8856 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8857 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8858 | DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); |
| 8859 | |
| 8860 | backup_u1MR14Value = u1MR14Value[p->channel][p->rank][p->dram_fsp]; |
| 8861 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8862 | if (gFinalTXVrefDQ[p->channel][p->rank] ==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8863 | gFinalTXVrefDQ[p->channel][p->rank] = u1MR14Value[p->channel][p->rank][p->dram_fsp]; |
| 8864 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8865 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8866 | for(u1vrefidx=0; u1vrefidx<=VREF_VOLTAGE_TABLE_NUM_LP5-1;u1vrefidx++) |
| 8867 | { |
| 8868 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 8869 | { |
| 8870 | for(ii=0; ii<EYESCAN_BROKEN_NUM; ii++) |
| 8871 | { |
| 8872 | gEyeScan_Min[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; |
| 8873 | gEyeScan_Max[u1vrefidx][u1BitIdx][ii] = EYESCAN_DATA_INVALID; |
| 8874 | } |
| 8875 | gEyeScan_ContinueVrefHeight[u1BitIdx] = 0; |
| 8876 | gEyeScan_TotalPassCount[u1BitIdx] = 0; |
| 8877 | } |
| 8878 | } |
| 8879 | |
| 8880 | |
| 8881 | u1MCK2UI = u1MCK2UI_DivShift(p); |
| 8882 | |
| 8883 | //if (vGet_DDR800_Mode(p) == DDR800_CLOSE_LOOP) |
| 8884 | // u1UI2PI = 6; |
| 8885 | //else |
| 8886 | u1UI2PI = 5; |
| 8887 | |
| 8888 | |
| 8889 | for(u1ByteIdx=0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 8890 | { |
| 8891 | if (u1ByteIdx == 0) |
| 8892 | { |
| 8893 | tx_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ0)<<(u1MCK2UI+u1UI2PI)) + |
| 8894 | (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ0)<<u1UI2PI) + |
| 8895 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); |
| 8896 | |
| 8897 | tx_dqm_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM0)<<(u1MCK2UI+u1UI2PI)) + |
| 8898 | (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM0)<<u1UI2PI) + |
| 8899 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); |
| 8900 | } |
| 8901 | else |
| 8902 | { |
| 8903 | tx_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_DQ1)<<(u1MCK2UI+u1UI2PI)) + |
| 8904 | (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_DQ1)<<u1UI2PI) + |
| 8905 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQ_B1); |
| 8906 | |
| 8907 | tx_dqm_pi_delay[u1ByteIdx] = (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), SHURK_SELPH_DQ1_TXDLY_DQM1)<<(u1MCK2UI+u1UI2PI)) + |
| 8908 | (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), SHURK_SELPH_DQ3_DLY_DQM1)<<u1UI2PI) + |
| 8909 | u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), SHU_R0_B1_DQ0_SW_ARPI_DQM_B1); |
| 8910 | } |
| 8911 | } |
| 8912 | |
| 8913 | if (tx_pi_delay[0] < tx_pi_delay[1]) |
| 8914 | { |
| 8915 | u2DQDelayBegin = tx_pi_delay[0]-32; |
| 8916 | } |
| 8917 | else |
| 8918 | { |
| 8919 | u2DQDelayBegin = tx_pi_delay[1]-32; |
| 8920 | } |
| 8921 | |
| 8922 | u2VrefRange = 0; |
| 8923 | u2VrefBegin = 0; |
| 8924 | u2VrefEnd = (p->dram_type==TYPE_LPDDR5?VREF_VOLTAGE_TABLE_NUM_LP5:VREF_VOLTAGE_TABLE_NUM_LP4)-1; |
| 8925 | u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP; |
| 8926 | mcSHOW_DBG_MSG3(("\nTX Vref %d -> %d, step: %d\n", u2VrefBegin, u2VrefEnd, u2VrefStep)); |
| 8927 | |
| 8928 | #if ENABLE_K_WITH_WORST_SI_UI_SHIFT |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8929 | DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8930 | #else |
| 8931 | DramcEngine2Init(p, p->test2_1, p->test2_2, TEST_XTALK_PATTERN, 0, TE_NO_UI_SHIFT); |
| 8932 | #endif |
| 8933 | |
| 8934 | |
| 8935 | for(u2VrefLevel = u2VrefBegin; u2VrefLevel <= u2VrefEnd; u2VrefLevel += u2VrefStep) |
| 8936 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8937 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8938 | DramcTXSetVref(p, u2VrefRange, u2VrefLevel); |
| 8939 | mcSHOW_DBG_MSG3(("\n\n Set TX VrefRange %d, VrefLevel=%d\n", u2VrefRange, u2VrefLevel)); |
| 8940 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 8941 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 8942 | uiFinishCount = 0; |
| 8943 | u2TempWinSum =0; |
| 8944 | |
| 8945 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 8946 | { |
| 8947 | WinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; |
| 8948 | WinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; |
| 8949 | VrefWinPerBit[u1BitIdx].first_pass = (S16)PASS_RANGE_NA; |
| 8950 | VrefWinPerBit[u1BitIdx].last_pass = (S16)PASS_RANGE_NA; |
| 8951 | |
| 8952 | gEyeScan_DelayCellPI[u1BitIdx] = 0; |
| 8953 | |
| 8954 | EyeScan_index[u1BitIdx] = 0; |
| 8955 | u1pass_in_this_vref_flag[u1BitIdx] = 0; |
| 8956 | } |
| 8957 | |
| 8958 | for (uiDelay=0; uiDelay<64; uiDelay+=(u1IsPhaseMode(p)==TRUE ? 8 : 1)) |
| 8959 | { |
| 8960 | TxWinTransferDelayToUIPI(p, tx_pi_delay[0]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); |
| 8961 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ |
| 8962 | P_Fld(ucdq_ui_large, SHURK_SELPH_DQ0_TXDLY_DQ0) | \ |
| 8963 | P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ0_TXDLY_OEN_DQ0)); |
| 8964 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ |
| 8965 | P_Fld(ucdq_ui_small, SHURK_SELPH_DQ2_DLY_DQ0) | \ |
| 8966 | P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ2_DLY_OEN_DQ0)); |
| 8967 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdq_pi, SHU_R0_B0_DQ0_SW_ARPI_DQ_B0); |
| 8968 | |
| 8969 | TxWinTransferDelayToUIPI(p, tx_pi_delay[1]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); |
| 8970 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ |
| 8971 | P_Fld(ucdq_ui_large, SHURK_SELPH_DQ0_TXDLY_DQ1) | \ |
| 8972 | P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ0_TXDLY_OEN_DQ1)); |
| 8973 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ |
| 8974 | P_Fld(ucdq_ui_small, SHURK_SELPH_DQ2_DLY_DQ1) | \ |
| 8975 | P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ2_DLY_OEN_DQ1)); |
| 8976 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdq_pi, SHU_R0_B1_DQ0_SW_ARPI_DQ_B1); |
| 8977 | |
| 8978 | TxWinTransferDelayToUIPI(p, tx_dqm_pi_delay[0]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); |
| 8979 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \ |
| 8980 | P_Fld(ucdq_ui_large, SHURK_SELPH_DQ1_TXDLY_DQM0) | \ |
| 8981 | P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ1_TXDLY_OEN_DQM0)); |
| 8982 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \ |
| 8983 | P_Fld(ucdq_ui_small, SHURK_SELPH_DQ3_DLY_DQM0) | \ |
| 8984 | P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ3_DLY_OEN_DQM0)); |
| 8985 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0), ucdq_pi, SHU_R0_B0_DQ0_SW_ARPI_DQM_B0); |
| 8986 | |
| 8987 | TxWinTransferDelayToUIPI(p, tx_dqm_pi_delay[1]+uiDelay-32, 0, &ucdq_ui_large, &ucdq_ui_small, &ucdq_pi, &ucdq_oen_ui_large, &ucdq_oen_ui_small); |
| 8988 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \ |
| 8989 | P_Fld(ucdq_ui_large, SHURK_SELPH_DQ1_TXDLY_DQM1) | \ |
| 8990 | P_Fld(ucdq_oen_ui_large, SHURK_SELPH_DQ1_TXDLY_OEN_DQM1)); |
| 8991 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \ |
| 8992 | P_Fld(ucdq_ui_small, SHURK_SELPH_DQ3_DLY_DQM1) | \ |
| 8993 | P_Fld(ucdq_oen_ui_small, SHURK_SELPH_DQ3_DLY_OEN_DQM1)); |
| 8994 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0), ucdq_pi, SHU_R0_B1_DQ0_SW_ARPI_DQM_B1); |
| 8995 | |
| 8996 | u4err_value=0; |
| 8997 | #if ENABLE_K_WITH_WORST_SI_UI_SHIFT |
| 8998 | //DramcEngine2SetPat(p, p->test_pattern, 0, 0, TE_UI_SHIFT); |
| 8999 | u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern); |
| 9000 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9001 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9002 | DramcEngine2SetPat(p, TEST_AUDIO_PATTERN, 0, 0, TE_NO_UI_SHIFT); |
| 9003 | u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN); |
| 9004 | DramcEngine2SetPat(p, TEST_XTALK_PATTERN, 0, 1, TE_NO_UI_SHIFT); |
| 9005 | u4err_value |= DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN); |
| 9006 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9007 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9008 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 9009 | { |
| 9010 | u4fail_bit = u4err_value&((U32)1<<u1BitIdx); |
| 9011 | |
| 9012 | if (u4fail_bit == 0) |
| 9013 | { |
| 9014 | gEyeScan_TotalPassCount[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP; |
| 9015 | } |
| 9016 | |
| 9017 | if(WinPerBit[u1BitIdx].first_pass== PASS_RANGE_NA) |
| 9018 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9019 | if(u4fail_bit==0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9020 | { |
| 9021 | WinPerBit[u1BitIdx].first_pass = uiDelay; |
| 9022 | u1pass_in_this_vref_flag[u1BitIdx] = 1; |
| 9023 | } |
| 9024 | } |
| 9025 | else if(WinPerBit[u1BitIdx].last_pass == PASS_RANGE_NA) |
| 9026 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9027 | if(u4fail_bit !=0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9028 | { |
| 9029 | WinPerBit[u1BitIdx].last_pass = (uiDelay-1); |
| 9030 | } |
| 9031 | else if (uiDelay>=63) |
| 9032 | { |
| 9033 | WinPerBit[u1BitIdx].last_pass = 63; |
| 9034 | } |
| 9035 | |
| 9036 | if(WinPerBit[u1BitIdx].last_pass !=PASS_RANGE_NA) |
| 9037 | { |
| 9038 | if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >= (VrefWinPerBit[u1BitIdx].last_pass -VrefWinPerBit[u1BitIdx].first_pass)) |
| 9039 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9040 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9041 | if((WinPerBit[u1BitIdx].last_pass -WinPerBit[u1BitIdx].first_pass) >7) |
| 9042 | uiFinishCount |= (1<<u1BitIdx); |
| 9043 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9044 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9045 | VrefWinPerBit[u1BitIdx].first_pass = WinPerBit[u1BitIdx].first_pass; |
| 9046 | VrefWinPerBit[u1BitIdx].last_pass = WinPerBit[u1BitIdx].last_pass; |
| 9047 | } |
| 9048 | |
| 9049 | |
| 9050 | if (EyeScan_index[u1BitIdx] < EYESCAN_BROKEN_NUM) |
| 9051 | { |
| 9052 | #if VENDER_JV_LOG || defined(RELEASE) |
| 9053 | gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].first_pass; |
| 9054 | gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass; |
| 9055 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9056 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9057 | gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].first_pass; |
| 9058 | gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].last_pass; |
| 9059 | mcSHOW_DBG_MSG3(("VrefRange %d, VrefLevel=%d, u1BitIdx=%d, index=%d (%d, %d)==\n",u2VrefRange,u2VrefLevel, u1BitIdx, EyeScan_index[u1BitIdx], gEyeScan_Min[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]], gEyeScan_Max[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]])); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9060 | gEyeScan_MinMax_store_delay[u1BitIdx/8] = tx_pi_delay[u1BitIdx/8]-32; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9061 | #endif |
| 9062 | EyeScan_index[u1BitIdx]=EyeScan_index[u1BitIdx]+1; |
| 9063 | } |
| 9064 | |
| 9065 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9066 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9067 | WinPerBit[u1BitIdx].first_pass = PASS_RANGE_NA; |
| 9068 | WinPerBit[u1BitIdx].last_pass = PASS_RANGE_NA; |
| 9069 | } |
| 9070 | } |
| 9071 | } |
| 9072 | } |
| 9073 | |
| 9074 | min_winsize = 0xffff; |
| 9075 | min_bit = 0xff; |
| 9076 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 9077 | { |
| 9078 | VrefWinPerBit[u1BitIdx].win_size = VrefWinPerBit[u1BitIdx].last_pass- VrefWinPerBit[u1BitIdx].first_pass +(VrefWinPerBit[u1BitIdx].last_pass==VrefWinPerBit[u1BitIdx].first_pass?0:1); |
| 9079 | |
| 9080 | if (VrefWinPerBit[u1BitIdx].win_size < min_winsize) |
| 9081 | { |
| 9082 | min_bit = u1BitIdx; |
| 9083 | min_winsize = VrefWinPerBit[u1BitIdx].win_size; |
| 9084 | } |
| 9085 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9086 | u2TempWinSum += VrefWinPerBit[u1BitIdx].win_size; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9087 | |
| 9088 | gEyeScan_WinSize[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx] = VrefWinPerBit[u1BitIdx].win_size; |
| 9089 | |
| 9090 | #ifdef FOR_HQA_TEST_USED |
| 9091 | if((((backup_u1MR14Value>>6)&1) == u2VrefRange) && ((backup_u1MR14Value&0x3f)==u2VrefLevel)) |
| 9092 | { |
| 9093 | gFinalTXPerbitWin[p->channel][p->rank][u1BitIdx] = VrefWinPerBit[u1BitIdx].win_size; |
| 9094 | } |
| 9095 | #endif |
| 9096 | |
| 9097 | } |
| 9098 | |
| 9099 | if ((min_winsize > TXPerbitWin_min_max) || ((min_winsize == TXPerbitWin_min_max) && (u2TempWinSum >u2tx_window_sum))) |
| 9100 | { |
| 9101 | TXPerbitWin_min_max = min_winsize; |
| 9102 | u2tx_window_sum =u2TempWinSum; |
| 9103 | u2FinalRange = u2VrefRange; |
| 9104 | u2FinalVref = u2VrefLevel; |
| 9105 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9106 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9107 | for (u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) |
| 9108 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9109 | #if 1 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9110 | u2Center_min[u1ByteIdx] = 0xffff; |
| 9111 | u2Center_max[u1ByteIdx] = 0; |
| 9112 | #endif |
| 9113 | |
| 9114 | for (u1BitIdx=0; u1BitIdx<DQS_BIT_NUMBER; u1BitIdx++) |
| 9115 | { |
| 9116 | ucindex = u1ByteIdx * DQS_BIT_NUMBER + u1BitIdx; |
| 9117 | FinalWinPerBit[ucindex].first_pass = VrefWinPerBit[ucindex].first_pass; |
| 9118 | FinalWinPerBit[ucindex].last_pass = VrefWinPerBit[ucindex].last_pass; |
| 9119 | FinalWinPerBit[ucindex].win_size = VrefWinPerBit[ucindex].win_size; |
| 9120 | FinalWinPerBit[ucindex].win_center = (FinalWinPerBit[ucindex].first_pass + FinalWinPerBit[ucindex].last_pass) >> 1; |
| 9121 | |
| 9122 | if(FinalWinPerBit[ucindex].win_center < u2Center_min[u1ByteIdx]) |
| 9123 | u2Center_min[u1ByteIdx] = FinalWinPerBit[ucindex].win_center; |
| 9124 | |
| 9125 | if(FinalWinPerBit[ucindex].win_center > u2Center_max[u1ByteIdx]) |
| 9126 | u2Center_max[u1ByteIdx] = FinalWinPerBit[ucindex].win_center; |
| 9127 | } |
| 9128 | } |
| 9129 | } |
| 9130 | |
| 9131 | |
| 9132 | if(u2VrefRange==0 && u2VrefLevel ==50 && p->dram_type!=TYPE_LPDDR5) |
| 9133 | { |
| 9134 | u2VrefRange = 1; |
| 9135 | u2VrefLevel = 20; |
| 9136 | } |
| 9137 | |
| 9138 | for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++) |
| 9139 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9140 | if (u1pass_in_this_vref_flag[u1BitIdx]) gEyeScan_ContinueVrefHeight[u1BitIdx]+=EYESCAN_GRAPH_CATX_VREF_STEP; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9141 | } |
| 9142 | } |
| 9143 | |
| 9144 | DramcEngine2End(p); |
| 9145 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9146 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9147 | for (u1ByteIdx=0; u1ByteIdx<DQS_BYTE_NUMBER; u1ByteIdx++) |
| 9148 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9149 | uiDelay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx])>>1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9150 | |
| 9151 | #if VENDER_JV_LOG || defined(RELEASE) |
| 9152 | gEyeScan_CaliDelay[u1ByteIdx] = uiDelay; |
| 9153 | #else |
| 9154 | gEyeScan_CaliDelay[u1ByteIdx] = uiDelay + tx_pi_delay[u1ByteIdx]-32; |
| 9155 | #endif |
| 9156 | } |
| 9157 | |
| 9158 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9159 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9160 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32)); |
| 9161 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9162 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9163 | { |
| 9164 | u2VrefRange = backup_u1MR14Value>>6; |
| 9165 | u2VrefLevel = backup_u1MR14Value & 0x3f; |
| 9166 | } |
| 9167 | DramcTXSetVref(p, u2VrefRange, u2VrefLevel); |
| 9168 | u1MR14Value[p->channel][p->rank][p->dram_fsp] = backup_u1MR14Value; |
| 9169 | |
| 9170 | } |
| 9171 | #endif |
| 9172 | |
| 9173 | #if TX_OE_CALIBATION |
| 9174 | #define TX_OE_PATTERN_USE_TA2 1 |
| 9175 | #define TX_OE_SCAN_FULL_RANGE 0 |
| 9176 | |
| 9177 | void DramcTxOECalibration(DRAMC_CTX_T *p) |
| 9178 | { |
| 9179 | U8 u1ByteIdx; //ucBegin[2] = {0xff, 0xff}, ucEnd[2] = {0xff, 0xff}, ucbest_step[2]; |
| 9180 | //U8 ucbegin=0xff, , ucfirst, ucsum, ucbest_step; |
| 9181 | //U32 u4RegValue_TXDLY, u4RegValue_dly, u4err_value; |
| 9182 | //U16 u2Delay, u2TempVirtualDelay, u2SmallestVirtualDelay = 0xffff; |
| 9183 | //U16 u2DQOEN_DelayBegin, u2DQEN_DelayEnd; |
| 9184 | //U8 ucdq_ui_large_bak[DQS_BYTE_NUMBER], ucdq_ui_small_bak[DQS_BYTE_NUMBER]; |
| 9185 | U8 ucdq_oen_ui_large[2] = {0}, ucdq_oen_ui_small[2] = {0}; |
| 9186 | //U8 ucdq_current_ui_large, ucdq_current_ui_small; |
| 9187 | //U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff; |
| 9188 | //U8 ucdq_final_dqm_oen_ui_large[DQS_BYTE_NUMBER] = {0}, ucdq_final_dqm_oen_ui_small[DQS_BYTE_NUMBER] = {0}; |
| 9189 | //DRAM_STATUS_T KResult; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9190 | |
| 9191 | //mcDUMP_REG_MSG(("\n[dumpRG] DramcTXOECalibration\n")); |
| 9192 | #if VENDER_JV_LOG |
| 9193 | vPrintCalibrationBasicInfo_ForJV(p); |
| 9194 | #else |
| 9195 | vPrintCalibrationBasicInfo(p); |
| 9196 | #endif |
| 9197 | |
| 9198 | #if TX_OE_PATTERN_USE_TA2 |
| 9199 | mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] TA2\n")); |
| 9200 | #else |
| 9201 | mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] DMA\n")); |
| 9202 | #endif |
| 9203 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9204 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9205 | vSetCalibrationResult(p, DRAM_CALIBRATION_TX_OE, DRAM_FAIL); |
| 9206 | |
| 9207 | #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION) |
| 9208 | if (p->femmc_Ready == 1) |
| 9209 | { |
| 9210 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 9211 | { |
| 9212 | ucdq_oen_ui_large[u1ByteIdx] = p->pSavetimeData->u1TX_OE_DQ_MCK[p->channel][p->rank][u1ByteIdx]; |
| 9213 | ucdq_oen_ui_small[u1ByteIdx] = p->pSavetimeData->u1TX_OE_DQ_UI[p->channel][p->rank][u1ByteIdx]; |
| 9214 | } |
| 9215 | vSetCalibrationResult(p, DRAM_CALIBRATION_TX_OE, DRAM_FAST_K); |
| 9216 | } |
| 9217 | #endif |
| 9218 | |
| 9219 | for (u1ByteIdx = 0; u1ByteIdx < DQS_BYTE_NUMBER; u1ByteIdx++) |
| 9220 | { |
| 9221 | mcSHOW_DBG_MSG(("Byte%d TX OE(2T, 0.5T) = (%d, %d)\n", u1ByteIdx, ucdq_oen_ui_large[u1ByteIdx], ucdq_oen_ui_small[u1ByteIdx])); |
| 9222 | //mcDUMP_REG_MSG(("Byte%d TX OE(2T, 0.5T) = (%d, %d)\n", u1ByteIdx, ucdq_oen_ui_large[u1ByteIdx], ucdq_oen_ui_small[u1ByteIdx])); |
| 9223 | } |
| 9224 | mcSHOW_DBG_MSG(("\n\n")); |
| 9225 | |
| 9226 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \ |
| 9227 | P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | \ |
| 9228 | P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ0_TXDLY_OEN_DQ1)); |
| 9229 | |
| 9230 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ1), \ |
| 9231 | P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ1_TXDLY_OEN_DQM0) | \ |
| 9232 | P_Fld(ucdq_oen_ui_large[1], SHURK_SELPH_DQ1_TXDLY_OEN_DQM1)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9233 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9234 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), \ |
| 9235 | P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ2_DLY_OEN_DQ0) | \ |
| 9236 | P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ2_DLY_OEN_DQ1) ); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9237 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9238 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ3), \ |
| 9239 | P_Fld(ucdq_oen_ui_small[0], SHURK_SELPH_DQ3_DLY_OEN_DQM0) | \ |
| 9240 | P_Fld(ucdq_oen_ui_small[1], SHURK_SELPH_DQ3_DLY_OEN_DQM1)); |
| 9241 | |
| 9242 | } |
| 9243 | #endif |
| 9244 | |
| 9245 | #define fld_val(_reg, _fld) \ |
| 9246 | ((_reg & Fld2Msk32(_fld)) >> Fld_shft(_fld)) |
| 9247 | static void OECKCKE_Control(DRAMC_CTX_T *p, U32 option) |
| 9248 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9249 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9250 | static U32 u4CA_CMD2_backup = 0; |
| 9251 | static U32 u4SHU_CA_CMD13_backup = 0; |
| 9252 | static U32 u4CS_CTRL_backup = 0; |
| 9253 | static U32 u4CKE_CTRL_backup = 0; |
| 9254 | static U32 u4backup_done = 0; |
| 9255 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
| 9256 | |
| 9257 | if (option == DISABLE) { |
| 9258 | if (u4backup_done == 1) { |
| 9259 | mcSHOW_ERR_MSG(("[%s] Backup OE again without restored??\n", __func__)); |
| 9260 | #if __ETT__ |
| 9261 | while (1); |
| 9262 | #else |
| 9263 | ASSERT(0); |
| 9264 | #endif |
| 9265 | } |
| 9266 | if (!isLP4_DSC) |
| 9267 | { |
| 9268 | u4CA_CMD2_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2)); |
| 9269 | u4SHU_CA_CMD13_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)); |
| 9270 | u4CS_CTRL_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL)); |
| 9271 | } |
| 9272 | else |
| 9273 | { |
| 9274 | u4CA_CMD2_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)); |
| 9275 | u4SHU_CA_CMD13_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)); |
| 9276 | u4CKE_CTRL_backup = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL)); |
| 9277 | } |
| 9278 | u4backup_done = 1; |
| 9279 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9280 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9281 | if (!isLP4_DSC) |
| 9282 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9283 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9284 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \ |
| 9285 | | P_Fld( 1, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \ |
| 9286 | | P_Fld( 0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \ |
| 9287 | | P_Fld( 0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9288 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9289 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL), P_Fld( 0, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)); |
| 9290 | } |
| 9291 | else |
| 9292 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9293 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9294 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld( 0, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1) \ |
| 9295 | | P_Fld( 1, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9296 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9297 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \ |
| 9298 | | P_Fld( 1, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) \ |
| 9299 | | P_Fld( 0, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \ |
| 9300 | | P_Fld( 0xff, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1)); |
| 9301 | } |
| 9302 | |
| 9303 | mcDELAY_US(1); |
| 9304 | if (!isLP4_DSC) |
| 9305 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9306 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9307 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA) \ |
| 9308 | | P_Fld( 1, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA)); |
| 9309 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9310 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9311 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( 0, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \ |
| 9312 | | P_Fld( 1, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA)); |
| 9313 | } |
| 9314 | else |
| 9315 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9316 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9317 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0, B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1) \ |
| 9318 | | P_Fld( 1, B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1)); |
| 9319 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9320 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9321 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld( 0, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1) \ |
| 9322 | | P_Fld( 1, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1)); |
| 9323 | } |
| 9324 | } else { |
| 9325 | U32 u4CKOE_TieSel, u4CKOE_TieEn; |
| 9326 | U32 u4CKBOE_TieSel, u4CKBOE_TieEn; |
| 9327 | U32 u4CSOE_TieSel, u4CSOE_TieEn; |
| 9328 | U32 u4CAOE_TieSel, u4CAOE_TieEn; |
| 9329 | U32 u4CKEOE_TieSel, u4CKEOE_TieEN; |
| 9330 | |
| 9331 | if (u4backup_done == 0) { |
| 9332 | mcSHOW_ERR_MSG(("[%s] Restore OE while not backup??\n", __func__)); |
| 9333 | #if __ETT__ |
| 9334 | while (1); |
| 9335 | #else |
| 9336 | ASSERT(0); |
| 9337 | #endif |
| 9338 | } |
| 9339 | |
| 9340 | u4CKOE_TieSel = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA); |
| 9341 | u4CKOE_TieEn = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA); |
| 9342 | u4CKBOE_TieSel = fld_val(u4SHU_CA_CMD13_backup, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA); |
| 9343 | u4CKBOE_TieEn = fld_val(u4SHU_CA_CMD13_backup, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA); |
| 9344 | u4CAOE_TieSel = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA); |
| 9345 | u4CAOE_TieEn = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA); |
| 9346 | if(!isLP4_DSC) |
| 9347 | { |
| 9348 | u4CSOE_TieSel = fld_val(u4CS_CTRL_backup, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0); |
| 9349 | u4CSOE_TieEn = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA); |
| 9350 | u4CKEOE_TieSel = fld_val(u4CA_CMD2_backup, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9351 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9352 | u4CKEOE_TieEN = u4CSOE_TieEn; |
| 9353 | } |
| 9354 | else |
| 9355 | { |
| 9356 | u4CSOE_TieSel = fld_val(u4CA_CMD2_backup, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1); |
| 9357 | u4CSOE_TieEn = fld_val(u4CA_CMD2_backup, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1); |
| 9358 | u4CKEOE_TieSel = fld_val(u4CKE_CTRL_backup, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1); |
| 9359 | u4CKEOE_TieEN = fld_val(u4CKE_CTRL_backup, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1); |
| 9360 | } |
| 9361 | |
| 9362 | if (!isLP4_DSC) |
| 9363 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9364 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9365 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( u4CKOE_TieSel, CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA) \ |
| 9366 | | P_Fld( u4CKOE_TieEn, CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA)); |
| 9367 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9368 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9369 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( u4CKBOE_TieSel, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \ |
| 9370 | | P_Fld( u4CKBOE_TieEn, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA)); |
| 9371 | } |
| 9372 | else |
| 9373 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9374 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9375 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( u4CKOE_TieSel, B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1) \ |
| 9376 | | P_Fld( u4CKOE_TieEn, B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1)); |
| 9377 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9378 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9379 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), P_Fld( u4CKBOE_TieSel, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \ |
| 9380 | | P_Fld( u4CKBOE_TieEn, SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1)); |
| 9381 | } |
| 9382 | |
| 9383 | mcDELAY_US(1); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9384 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9385 | if (!isLP4_DSC) |
| 9386 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9387 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9388 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_TX_ARCS_CTRL), P_Fld( u4CSOE_TieSel, CA_TX_ARCS_CTRL_RG_TX_ARCS_OE_TIE_SEL_C0)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9389 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9390 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( u4CKEOE_TieSel, CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA) \ |
| 9391 | | P_Fld( u4CSOE_TieEn, CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA) \ |
| 9392 | | P_Fld( u4CAOE_TieSel, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA) \ |
| 9393 | | P_Fld( u4CAOE_TieEn, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA)); |
| 9394 | } |
| 9395 | else |
| 9396 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9397 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9398 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( u4CSOE_TieSel, B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1) \ |
| 9399 | | P_Fld( u4CSOE_TieEn, B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1) \ |
| 9400 | | P_Fld( u4CAOE_TieSel, B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1) \ |
| 9401 | | P_Fld( u4CAOE_TieEn, B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9402 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9403 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_TX_CKE_CTRL), P_Fld( u4CKEOE_TieSel, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_SEL_B1) \ |
| 9404 | | P_Fld( u4CKEOE_TieEN, B1_TX_CKE_CTRL_RG_TX_ARCKE_OE_TIE_EN_B1)); |
| 9405 | } |
| 9406 | |
| 9407 | u4backup_done = 0; |
| 9408 | } |
| 9409 | } |
| 9410 | |
| 9411 | static void OEDisable(DRAMC_CTX_T *p) |
| 9412 | { |
| 9413 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
| 9414 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9415 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9416 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), P_Fld( 0 , B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0 ) \ |
| 9417 | | P_Fld( 1 , B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0 ) \ |
| 9418 | | P_Fld( 0 , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \ |
| 9419 | | P_Fld( 1 , B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0 ) \ |
| 9420 | | P_Fld( 0 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0 ) \ |
| 9421 | | P_Fld( 1 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 ) \ |
| 9422 | | P_Fld( 0 , B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0 ) \ |
| 9423 | | P_Fld( 1 , B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0 ) \ |
| 9424 | | P_Fld( 0 , B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0 ) \ |
| 9425 | | P_Fld( 0xff , B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0 ) ); |
| 9426 | if (!isLP4_DSC) |
| 9427 | { |
| 9428 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), P_Fld( 0 , B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1 ) \ |
| 9429 | | P_Fld( 1 , B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1 ) \ |
| 9430 | | P_Fld( 0 , B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 ) \ |
| 9431 | | P_Fld( 1 , B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1 ) \ |
| 9432 | | P_Fld( 0 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1 ) \ |
| 9433 | | P_Fld( 1 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 ) \ |
| 9434 | | P_Fld( 0 , B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1 ) \ |
| 9435 | | P_Fld( 1 , B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1 ) \ |
| 9436 | | P_Fld( 0 , B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1 ) \ |
| 9437 | | P_Fld( 0xff , B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1) ); |
| 9438 | } |
| 9439 | else |
| 9440 | { |
| 9441 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld( 0 , CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA ) \ |
| 9442 | | P_Fld( 1 , CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA ) \ |
| 9443 | | P_Fld( 0 , CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA ) \ |
| 9444 | | P_Fld( 1 , CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA ) \ |
| 9445 | | P_Fld( 0 , CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA ) \ |
| 9446 | | P_Fld( 0xff , CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA) ); |
| 9447 | } |
| 9448 | |
| 9449 | OECKCKE_Control(p, DISABLE); |
| 9450 | |
| 9451 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( 0 , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 ) \ |
| 9452 | | P_Fld( 1 , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 )); |
| 9453 | if (!isLP4_DSC) |
| 9454 | { |
| 9455 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( 0 , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \ |
| 9456 | | P_Fld( 1 , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 )); |
| 9457 | } |
| 9458 | else |
| 9459 | { |
| 9460 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13) , P_Fld( 0 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \ |
| 9461 | | P_Fld( 1 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA )); |
| 9462 | } |
| 9463 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9464 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9465 | } |
| 9466 | |
| 9467 | #ifdef FOR_HQA_TEST_USED |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9468 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9469 | VCORE_DELAYCELL_T gVcoreDelayCellTable[49]={ {500000, 512}, |
| 9470 | {506250, 496}, |
| 9471 | {512500, 482}, |
| 9472 | {518750, 469}, |
| 9473 | {525000, 457}, |
| 9474 | {531250, 445}, |
| 9475 | {537500, 434}, |
| 9476 | {543750, 423}, |
| 9477 | {550000, 412}, |
| 9478 | {556250, 402}, |
| 9479 | {562500, 393}, |
| 9480 | {568750, 384}, |
| 9481 | {575000, 377}, |
| 9482 | {581250, 369}, |
| 9483 | {587500, 362}, |
| 9484 | {593750, 355}, |
| 9485 | {600000, 348}, |
| 9486 | {606250, 341}, |
| 9487 | {612500, 335}, |
| 9488 | {618750, 328}, |
| 9489 | {625000, 322}, |
| 9490 | {631250, 317}, |
| 9491 | {637500, 312}, |
| 9492 | {643750, 307}, |
| 9493 | {650000, 302}, |
| 9494 | {656250, 297}, |
| 9495 | {662500, 292}, |
| 9496 | {668750, 288}, |
| 9497 | {675000, 284}, |
| 9498 | {681250, 280}, |
| 9499 | {687500, 276}, |
| 9500 | {693750, 272}, |
| 9501 | {700000, 269}, |
| 9502 | {706250, 265}, |
| 9503 | {712500, 262}, |
| 9504 | {718750, 258}, |
| 9505 | {725000, 255}, |
| 9506 | {731250, 252}, |
| 9507 | {737500, 249}, |
| 9508 | {743750, 246}, |
| 9509 | {750000, 243}, |
| 9510 | {756250, 241}, |
| 9511 | {762500, 238}, |
| 9512 | {768750, 236}, |
| 9513 | {775000, 233}, |
| 9514 | {781250, 231}, |
| 9515 | {787500, 229}, |
| 9516 | {793750, 227}, |
| 9517 | {800000, 225}, |
| 9518 | //{825000, 718}, |
| 9519 | //{831250, 717}, |
| 9520 | //{837500, 715}, |
| 9521 | //{843750, 713}, |
| 9522 | //{850000, 708}, |
| 9523 | //{856250, 705}, |
| 9524 | //{862500, 702}, |
| 9525 | //{868750, 700}, |
| 9526 | //{875000, 698} |
| 9527 | }; |
| 9528 | |
| 9529 | static U16 GetVcoreDelayCellTimeFromTable(DRAMC_CTX_T *p) |
| 9530 | { |
| 9531 | U32 i; |
| 9532 | U32 get_vcore = 0; |
| 9533 | U16 delay_cell_ps = 0; |
| 9534 | U8 u1delay_cell_cnt = 0; |
| 9535 | VCORE_DELAYCELL_T *pVcoreDelayCellTable; |
| 9536 | |
| 9537 | #if (defined(DRAM_HQA) || __ETT__) && (FOR_DV_SIMULATION_USED == 0) |
| 9538 | get_vcore = dramc_get_vcore_voltage(); |
| 9539 | #endif |
| 9540 | |
| 9541 | pVcoreDelayCellTable = (VCORE_DELAYCELL_T *)gVcoreDelayCellTable; |
| 9542 | u1delay_cell_cnt = sizeof(gVcoreDelayCellTable)/sizeof(gVcoreDelayCellTable[0]); |
| 9543 | |
| 9544 | for(i=0; i<u1delay_cell_cnt; i++) |
| 9545 | { |
| 9546 | if (get_vcore <= pVcoreDelayCellTable[i].u2Vcore) |
| 9547 | { |
| 9548 | delay_cell_ps = pVcoreDelayCellTable[i].u2DelayCell; |
| 9549 | break; |
| 9550 | } |
| 9551 | } |
| 9552 | |
| 9553 | mcSHOW_DBG_MSG(("[GetVcoreDelayCellTimeFromTable(%d)] VCore=%d(x100), DelayCell=%d(x100)\n", u1delay_cell_cnt, get_vcore, delay_cell_ps)); |
| 9554 | |
| 9555 | return delay_cell_ps; |
| 9556 | } |
| 9557 | #endif |
| 9558 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9559 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9560 | #if ENABLE_8PHASE_CALIBRATION || defined(ENABLE_MIOCK_JMETER) |
| 9561 | static void DramcJmeterInit(DRAMC_CTX_T *p, U8 u1IsJmtrK) |
| 9562 | { |
| 9563 | OEDisable(p); |
| 9564 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9565 | //DramcHWGatingOnOff(p, 0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9566 | if(u1IsJmtrK != TRUE) |
| 9567 | { |
| 9568 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) |
| 9569 | | P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN)); |
| 9570 | } |
| 9571 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9572 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9573 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 0, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); |
| 9574 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 0, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); |
| 9575 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 0, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); |
| 9576 | mcDELAY_US(1); |
| 9577 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0), 1, B0_DLL_ARPI0_RG_ARPI_RESETB_B0); |
| 9578 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0), 1, B1_DLL_ARPI0_RG_ARPI_RESETB_B1); |
| 9579 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0), 1, CA_DLL_ARPI0_RG_ARPI_RESETB_CA); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9580 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9581 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6), 0, SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0); |
| 9582 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6), 0, SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1); |
| 9583 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6), 0, SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA); |
| 9584 | #endif |
| 9585 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9586 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9587 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11), 0, SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0); |
| 9588 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), 0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1); |
| 9589 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11), 0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA); |
| 9590 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9591 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9592 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1), P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA) |
| 9593 | | P_Fld(0x0, SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA)); |
| 9594 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0) |
| 9595 | | P_Fld(0x0, SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0)); |
| 9596 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1) |
| 9597 | | P_Fld(0x0, SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1)); |
| 9598 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9599 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9600 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMDQSIENCG_EN); |
| 9601 | |
| 9602 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2), 0, SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0); |
| 9603 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2), 0, SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1); |
| 9604 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN); |
| 9605 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), 0, MISC_CTRL4_R_OPT2_CG_DQSIEN); |
| 9606 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_DQSIENCG_NORMAL_EN); |
| 9607 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9608 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6), 1, B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0); |
| 9609 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6), 1, B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1); |
| 9610 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9611 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9612 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); |
| 9613 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN) |
| 9614 | | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN) |
| 9615 | | P_Fld(0x1, MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN)); |
| 9616 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0); |
| 9617 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1); |
| 9618 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5), 1, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0); |
| 9619 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5), 1, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1); |
| 9620 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3), 1, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0); |
| 9621 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3), 1, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9622 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9623 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_EN_B0); |
| 9624 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_EN_B1); |
| 9625 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER), 1, MISC_JMETER_JMTR_EN); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9626 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9627 | |
| 9628 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9629 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), 1, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0); |
| 9630 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), 1, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9631 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9632 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9633 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN); |
| 9634 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9635 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9636 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); |
| 9637 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_DQSERRCNT_DIS); |
| 9638 | |
| 9639 | #if MIOCK_JMETER_CNT_WA |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9640 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9641 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_EYESCAN_DQS_OPT); |
| 9642 | #endif |
| 9643 | |
| 9644 | } |
| 9645 | |
| 9646 | static void DramcJmeterCalib(DRAMC_CTX_T *p, JMETER_T *pJmtrInfo, U16 u2JmDlyStep, U8 u1IsJmtrK) |
| 9647 | { |
| 9648 | U16 u2Jm_dly_start = 0, u2Jm_dly_end = 512, u2Jm_dly_step = u2JmDlyStep; |
| 9649 | U16 ucdqs_dly, fgcurrent_value, fginitial_value; |
| 9650 | U16 ucsearch_state = 0xffff; |
| 9651 | U32 u4sample_cnt, u4ones_cnt[DQS_BYTE_NUMBER]; |
| 9652 | U8 check; |
| 9653 | |
| 9654 | check = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), MISC_DUTYSCAN1_EYESCAN_DQS_OPT); |
Arthur Heymans | e9d9c1e | 2023-04-19 10:08:36 +0200 | [diff] [blame] | 9655 | (void)check; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9656 | |
| 9657 | for (ucdqs_dly = u2Jm_dly_start; ucdqs_dly < u2Jm_dly_end; ucdqs_dly += u2Jm_dly_step) |
| 9658 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9659 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9660 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2), ucdqs_dly, B0_PHY2_RG_RX_ARDQS_JM_DLY_B0); |
| 9661 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2), ucdqs_dly, B1_PHY2_RG_RX_ARDQS_JM_DLY_B1); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9662 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9663 | |
| 9664 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9665 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_REG_SW_RST); |
| 9666 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_REG_SW_RST); |
| 9667 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9668 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9669 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); |
| 9670 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9671 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9672 | mcDELAY_US(10); |
| 9673 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9674 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9675 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1), 0, MISC_DUTYSCAN1_RX_EYE_SCAN_EN); |
| 9676 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9677 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9678 | u4sample_cnt = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_TOGGLE_CNT), MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT); |
| 9679 | u4ones_cnt[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT), MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT); |
| 9680 | //u4ones_cnt[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT), MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT); |
| 9681 | //u4ones_cnt[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT), MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT); |
| 9682 | //u4ones_cnt[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT), MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT); |
| 9683 | #ifndef DDR_INIT_TIME_PROFILING |
| 9684 | if (u1IsJmtrK == TRUE){ |
| 9685 | mcSHOW_DBG_MSG2(("%d : %d, %d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0])); |
| 9686 | } |
| 9687 | #endif |
| 9688 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9689 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9690 | if (u4ones_cnt[0] < (u4sample_cnt / 2)) |
| 9691 | { |
| 9692 | fgcurrent_value = 0; |
| 9693 | } |
| 9694 | else |
| 9695 | { |
| 9696 | fgcurrent_value = 1; |
| 9697 | } |
| 9698 | |
| 9699 | |
| 9700 | if (ucsearch_state == 0xffff) |
| 9701 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9702 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9703 | fginitial_value = fgcurrent_value; |
| 9704 | ucsearch_state = 0; |
| 9705 | } |
| 9706 | else |
| 9707 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9708 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9709 | if (fgcurrent_value != fginitial_value) |
| 9710 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9711 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9712 | fginitial_value = fgcurrent_value; |
| 9713 | pJmtrInfo->JmtrInfo[ucsearch_state].u1JmDelay = ucdqs_dly; |
| 9714 | pJmtrInfo->JmtrInfo[ucsearch_state].u1TransLevel = fgcurrent_value; |
| 9715 | |
| 9716 | ucsearch_state++; |
| 9717 | pJmtrInfo->u1TransCnt = ucsearch_state; |
| 9718 | if (ucsearch_state == CYCLE_1T) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9719 | break; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9720 | } |
| 9721 | } |
| 9722 | } |
| 9723 | } |
| 9724 | #endif |
| 9725 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9726 | |
| 9727 | #ifdef ENABLE_MIOCK_JMETER |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9728 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9729 | U16 GetVcoreDelayCellTime(DRAMC_CTX_T *p) |
| 9730 | { |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9731 | |
| 9732 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 9733 | if(p->femmc_Ready==1) |
| 9734 | { |
| 9735 | mcSHOW_DBG_MSG(("[FAST_K] Freq=%d, DelayCellTimex100=%d\n", p->frequency, p->pSavetimeData->u2DelayCellTimex100)); |
| 9736 | return p->pSavetimeData->u2DelayCellTimex100; |
| 9737 | } |
| 9738 | #endif |
| 9739 | |
Ryan Chuang | e895b2a | 2021-08-31 11:05:14 +0800 | [diff] [blame] | 9740 | return 0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9741 | } |
| 9742 | |
| 9743 | void Get_RX_DelayCell(DRAMC_CTX_T *p) |
| 9744 | { |
| 9745 | #if defined(FOR_HQA_REPORT_USED) && (FOR_DV_SIMULATION_USED==0) && (SW_CHANGE_FOR_SIMULATION==0) |
| 9746 | |
| 9747 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 9748 | if(p->femmc_Ready == 1) |
| 9749 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9750 | return; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9751 | } |
| 9752 | #endif |
| 9753 | |
| 9754 | if (gHQALOG_RX_delay_cell_ps_075V == 0) |
| 9755 | { |
| 9756 | #if __ETT__ |
| 9757 | mcSHOW_DBG_MSG(("RX delay cell calibration (%d):\n", hqa_vmddr_class)); |
| 9758 | switch (hqa_vmddr_class) |
| 9759 | { |
| 9760 | case 1: |
| 9761 | dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, HV, LP4)); |
| 9762 | break; |
| 9763 | case 2: |
| 9764 | dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, NV, LP4)); |
| 9765 | break; |
| 9766 | case 3: |
| 9767 | dramc_set_vcore_voltage(_SEL_PREFIX(VMDDR, LV, LP4)); |
| 9768 | break; |
| 9769 | } |
| 9770 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9771 | |
| 9772 | dramc_set_vcore_voltage(SEL_PREFIX_VMDDR); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9773 | #endif |
| 9774 | |
| 9775 | gHQALOG_RX_delay_cell_ps_075V = GetVcoreDelayCellTime(p); |
| 9776 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9777 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9778 | vSetVcoreByFreq(p); |
| 9779 | } |
| 9780 | #endif |
| 9781 | } |
| 9782 | #endif |
| 9783 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9784 | |
| 9785 | DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p) |
| 9786 | { |
| 9787 | #if ENABLE_8PHASE_CALIBRATION |
| 9788 | U8 u18Ph_dly_loop_break = 0; |
| 9789 | U8 u1DqsienPI = 0; |
| 9790 | U8 u18Phase_SM = DQS_8PH_DEGREE_0, u18Ph_dly_final = 0xff; |
| 9791 | U8 u18Ph_dly = 0, u18Ph_start = 0, u18Ph_end = 0; |
| 9792 | |
| 9793 | U16 u2R0 = 0xffff, u2R180 = 0xffff, u2R = 0xffff; |
| 9794 | U16 u2P = 0xffff, ucdqs_dly = 0; |
| 9795 | S16 s2Err_code = 0x7fff, s2Err_code_min = 0x7fff; |
| 9796 | |
| 9797 | U8 backup_rank, u1RankIdx, u18PhDlyBackup = 0; |
| 9798 | U8 u1loop_cnt = 0, u1early_break_cnt = 5; |
| 9799 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9800 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9801 | JMETER_T JmtrInfo; |
| 9802 | U8 u1JmtrPrintCnt = 0; |
| 9803 | |
| 9804 | U32 u4backup_broadcast= GetDramcBroadcast(); |
| 9805 | DRAM_STATUS_T eDRAMStatus = DRAM_OK; |
| 9806 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9807 | #ifdef DUMP_INIT_RG_LOG_TO_DE |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9808 | return DRAM_OK; |
| 9809 | #endif |
| 9810 | |
| 9811 | u1DqsienPI = 0x0; |
| 9812 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9813 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9814 | if (!p) |
| 9815 | { |
| 9816 | mcSHOW_ERR_MSG(("context NULL\n")); |
| 9817 | return DRAM_FAIL; |
| 9818 | } |
| 9819 | |
| 9820 | if (p->frequency < 1866) |
| 9821 | { |
| 9822 | //mcSHOW_ERR_MSG(("skip 8-Phase Calib Freq is %d < 1866 !!!\n", p->frequency)); |
| 9823 | return DRAM_OK; |
| 9824 | } |
| 9825 | |
| 9826 | //mcDUMP_REG_MSG(("\n[dumpRG] Dramc8PhaseCal\n")); |
| 9827 | #if VENDER_JV_LOG |
| 9828 | vPrintCalibrationBasicInfo_ForJV(p); |
| 9829 | #else |
| 9830 | vPrintCalibrationBasicInfo(p); |
| 9831 | #endif |
| 9832 | |
| 9833 | mcSHOW_DBG_MSG(("[Dramc8PhaseCal]\n")); |
| 9834 | |
| 9835 | U32 u4RegBackupAddress[] = |
| 9836 | { |
| 9837 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1)), |
| 9838 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6)), |
| 9839 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)), |
| 9840 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5)), |
| 9841 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5)), |
| 9842 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ3)), |
| 9843 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ3)), |
| 9844 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)), |
| 9845 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)), |
| 9846 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2)), |
| 9847 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2)), |
| 9848 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL_ARPI2)), |
| 9849 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL_ARPI2)), |
| 9850 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11)), |
| 9851 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11)), |
| 9852 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD11)), |
| 9853 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL)), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9854 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY)), |
| 9855 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY + DDRPHY_AO_RANK_OFFSET)), |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9856 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_JMETER)), |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9857 | //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2)), |
| 9858 | //(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2)), |
| 9859 | (DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL)), |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9860 | #if 0 |
| 9861 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DLL_ARPI0)), |
| 9862 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DLL_ARPI0)), |
| 9863 | (DRAMC_REG_ADDR(DDRPHY_REG_CA_DLL_ARPI0)), |
| 9864 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ6)), |
| 9865 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ6)), |
| 9866 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6)), |
| 9867 | #endif |
| 9868 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1)), |
| 9869 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)), |
| 9870 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)), |
| 9871 | (DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)), |
| 9872 | (DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)), |
| 9873 | (DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2)), |
| 9874 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)), |
| 9875 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)), |
| 9876 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)), |
| 9877 | |
| 9878 | }; |
| 9879 | |
| 9880 | backup_rank = u1GetRank(p); |
| 9881 | memset(&JmtrInfo, 0, sizeof(JmtrInfo)); |
| 9882 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 9883 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9884 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9885 | DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 9886 | |
| 9887 | DramcJmeterInit(p, FALSE); |
| 9888 | |
| 9889 | u18PhDlyBackup = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1), SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); |
| 9890 | |
| 9891 | for (u18Phase_SM = DQS_8PH_DEGREE_0; u18Phase_SM < DQS_8PH_DEGREE_MAX; u18Phase_SM++) |
| 9892 | { |
| 9893 | switch (u18Phase_SM) |
| 9894 | { |
| 9895 | case DQS_8PH_DEGREE_0: |
| 9896 | u1DqsienPI = 16; |
| 9897 | u18Ph_start = 0; |
| 9898 | u18Ph_end = 1; |
| 9899 | break; |
| 9900 | case DQS_8PH_DEGREE_180: |
| 9901 | u1DqsienPI = 48; |
| 9902 | u18Ph_start = 0; |
| 9903 | u18Ph_end = 1; |
| 9904 | break; |
| 9905 | case DQS_8PH_DEGREE_45: |
| 9906 | u1DqsienPI = 24; |
| 9907 | u18Ph_start = 0; |
| 9908 | u18Ph_end = 32; |
| 9909 | break; |
| 9910 | default: |
| 9911 | mcSHOW_ERR_MSG(("u18Phase_SM err!\n")); |
| 9912 | #if __ETT__ |
| 9913 | while (1); |
| 9914 | #endif |
| 9915 | } |
| 9916 | |
| 9917 | mcSHOW_DBG_MSG2(("\n[Dramc8PhaseCal] 8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", u18Phase_SM, u18Ph_start, u18Ph_end, u1DqsienPI, u18PhDlyBackup)); |
| 9918 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9919 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9920 | for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++) |
| 9921 | { |
| 9922 | vSetRank(p, u1RankIdx); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9923 | |
| 9924 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY), u1DqsienPI, SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9925 | } |
| 9926 | vSetRank(p, backup_rank); |
| 9927 | |
| 9928 | for (u18Ph_dly = u18Ph_start; u18Ph_dly < u18Ph_end; u18Ph_dly++) |
| 9929 | { |
| 9930 | mcSHOW_DBG_MSG2(("8PH dly = %d\n", u18Ph_dly)); |
| 9931 | |
| 9932 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1), u18Ph_dly, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); |
| 9933 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1), u18Ph_dly, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1); |
| 9934 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1), u18Ph_dly, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA); |
| 9935 | |
| 9936 | DramcJmeterCalib(p, &JmtrInfo, 1, FALSE); |
| 9937 | |
| 9938 | for (u1JmtrPrintCnt = 0; u1JmtrPrintCnt < JmtrInfo.u1TransCnt; u1JmtrPrintCnt++) |
| 9939 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9940 | if (JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1TransLevel == 1) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9941 | { |
| 9942 | ucdqs_dly = JmtrInfo.JmtrInfo[u1JmtrPrintCnt].u1JmDelay; |
| 9943 | |
| 9944 | if (u18Phase_SM == DQS_8PH_DEGREE_0) |
| 9945 | { |
| 9946 | u2R0 = ucdqs_dly; |
| 9947 | mcSHOW_DBG_MSG2(("R0 (H) = %d\n", u2R0)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9948 | break; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9949 | } |
| 9950 | else if (u18Phase_SM == DQS_8PH_DEGREE_180) |
| 9951 | { |
| 9952 | u2R180 = ucdqs_dly; |
| 9953 | if (u2R180 > u2R0) |
| 9954 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9955 | u2R = u2R0 + ((u2R180 - u2R0) >> 2); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9956 | mcSHOW_DBG_MSG2(("R = %d, R180 (H) = %d\n", u2R, u2R180)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9957 | break; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9958 | } |
| 9959 | } |
| 9960 | else if (u18Phase_SM == DQS_8PH_DEGREE_45) |
| 9961 | { |
| 9962 | u2P = ucdqs_dly; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9963 | if (u2P > u2R0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9964 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9965 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9966 | if (u2R > u2P) |
| 9967 | s2Err_code = u2R - u2P; |
| 9968 | else |
| 9969 | s2Err_code = u2P - u2R; |
| 9970 | |
| 9971 | if (s2Err_code == 0) |
| 9972 | { |
| 9973 | s2Err_code_min = s2Err_code; |
| 9974 | u18Ph_dly_final = u18Ph_dly; |
| 9975 | u18Ph_dly_loop_break = 1; |
| 9976 | } |
| 9977 | else if (s2Err_code < s2Err_code_min) |
| 9978 | { |
| 9979 | s2Err_code_min = s2Err_code; |
| 9980 | u18Ph_dly_final = u18Ph_dly; |
| 9981 | u1loop_cnt = 0; |
| 9982 | } |
| 9983 | else if (s2Err_code >= s2Err_code_min) |
| 9984 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9985 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9986 | u1loop_cnt++; |
| 9987 | if (u1loop_cnt > u1early_break_cnt) |
| 9988 | u18Ph_dly_loop_break = 1; |
| 9989 | } |
| 9990 | |
| 9991 | mcSHOW_DBG_MSG2(("diff (P-R) = %d, min = %d, early break count = %d, R45 (H) = %d\n", s2Err_code, s2Err_code_min, u1loop_cnt, u2P)); |
| 9992 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 9993 | break; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 9994 | } |
| 9995 | } |
| 9996 | else |
| 9997 | { |
| 9998 | mcSHOW_ERR_MSG(("u18Phase_SM err!\n")); |
| 9999 | #if __ETT__ |
| 10000 | while (1); |
| 10001 | #endif |
| 10002 | } |
| 10003 | } |
| 10004 | } |
| 10005 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10006 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10007 | if (JmtrInfo.u1TransCnt == u1JmtrPrintCnt) |
| 10008 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10009 | u18Ph_dly_final = u18PhDlyBackup; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10010 | eDRAMStatus = DRAM_FAIL; |
| 10011 | mcSHOW_ERR_MSG(("\n[Dramc8PhaseCal] 8-Phase SM_%d is fail (to Default) !!!\n", u18Phase_SM)); |
| 10012 | goto exit; |
| 10013 | } else if (u18Ph_dly_loop_break == 1) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10014 | break; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10015 | } |
| 10016 | } |
| 10017 | |
| 10018 | exit: |
| 10019 | mcSHOW_DBG_MSG(("\n[Dramc8PhaseCal] u18Ph_dly_final = %d\n\n", u18Ph_dly_final)); |
| 10020 | //mcDUMP_REG_MSG(("\n[Dramc8PhaseCal] u18Ph_dly_final = %d\n\n", u18Ph_dly_final)); |
| 10021 | |
| 10022 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ1, u18Ph_dly_final, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); |
| 10023 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ1, u18Ph_dly_final, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1); |
| 10024 | vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD1, u18Ph_dly_final, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA); |
| 10025 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10026 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10027 | OECKCKE_Control(p, ENABLE); |
| 10028 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 10029 | |
| 10030 | DramcBroadcastOnOff(u4backup_broadcast); |
| 10031 | |
| 10032 | return eDRAMStatus; |
| 10033 | #endif |
| 10034 | } |
| 10035 | |
| 10036 | #if SIMULATION_SW_IMPED |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10037 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10038 | #if 0 |
| 10039 | static U32 SwImpedanceAdjust(U32 u4ImpVal, S8 s1StepCnt) |
| 10040 | { |
| 10041 | S32 S4ImpedanceTemp = (S32)u4ImpVal; |
| 10042 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10043 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10044 | S4ImpedanceTemp += s1StepCnt; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10045 | |
| 10046 | if ((S4ImpedanceTemp > 15) && (S4ImpedanceTemp < 29)) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10047 | { |
| 10048 | S4ImpedanceTemp = S4ImpedanceTemp - 16 + 29; |
| 10049 | } |
| 10050 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10051 | if (S4ImpedanceTemp > 31) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10052 | { |
| 10053 | S4ImpedanceTemp = 31; |
| 10054 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10055 | else if (S4ImpedanceTemp < 0) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10056 | { |
| 10057 | S4ImpedanceTemp = 0; |
| 10058 | } |
| 10059 | |
| 10060 | return (U32)S4ImpedanceTemp; |
| 10061 | } |
| 10062 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10063 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10064 | #define IMPCAL_STAGE_DRVP 0 |
| 10065 | #define IMPCAL_STAGE_DRVN 1 |
| 10066 | #define IMPCAL_STAGE_ODTP 2 |
| 10067 | #define IMPCAL_STAGE_ODTN 3 |
| 10068 | #define IMPCAL_STAGE_TRACKING 4 |
| 10069 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10070 | |
| 10071 | #define IMP_TRACK_LP4X_LOWFREQ_VREF_SEL 0x37 |
| 10072 | #define IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL 0x3a |
| 10073 | |
| 10074 | #define IMP_TRACK_LP5_LOWFREQ_VREF_SEL 0x38 |
| 10075 | #define IMP_TRACK_LP5_HIGHFREQ_VREF_SEL 0x3a |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10076 | |
| 10077 | static const U8 ImpLP4VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10078 | |
| 10079 | {0x37, 0x33, 0x00, 0x37}, |
| 10080 | {0x3a, 0x33, 0x00, 0x3a}, |
| 10081 | {0x2a, 0x2a, 0x00, 0x3a} |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10082 | }; |
| 10083 | |
| 10084 | static const U8 ImpLP5VrefSel[IMP_VREF_MAX][IMP_DRV_MAX] = { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10085 | |
| 10086 | {0x38, 0x33, 0x00, 0x38}, |
| 10087 | {0x3a, 0x33, 0x00, 0x3a}, |
| 10088 | {0x2a, 0x2a, 0x00, 0x3a} |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10089 | }; |
| 10090 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10091 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10092 | static void vImpCalVrefSel(DRAMC_CTX_T *p, DRAMC_IMP_T efreq_region, U8 u1ImpCalStage) |
| 10093 | { |
| 10094 | U8 u1RegTmpValue = 0; |
| 10095 | U32 u4DrvFld = 0; |
| 10096 | |
| 10097 | if (p->dram_type == TYPE_LPDDR4X) |
| 10098 | { |
| 10099 | if (u1ImpCalStage == IMPCAL_STAGE_TRACKING) |
| 10100 | u1RegTmpValue = (efreq_region == IMP_LOW_FREQ) ? IMP_TRACK_LP4X_LOWFREQ_VREF_SEL : IMP_TRACK_LP4X_HIGHFREQ_VREF_SEL; |
| 10101 | else |
| 10102 | u1RegTmpValue = ImpLP4VrefSel[efreq_region][u1ImpCalStage]; |
| 10103 | } |
| 10104 | else if (p->dram_type == TYPE_LPDDR5) |
| 10105 | { |
| 10106 | if (u1ImpCalStage == IMPCAL_STAGE_TRACKING) |
| 10107 | u1RegTmpValue = (efreq_region == IMP_LOW_FREQ) ? IMP_TRACK_LP5_LOWFREQ_VREF_SEL : IMP_TRACK_LP5_HIGHFREQ_VREF_SEL; |
| 10108 | else |
| 10109 | u1RegTmpValue = ImpLP5VrefSel[efreq_region][u1ImpCalStage]; |
| 10110 | } |
| 10111 | else |
| 10112 | { |
| 10113 | mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm DRAM type for IMP_VREF_SEL !!!\n")); |
| 10114 | #if __ETT__ |
| 10115 | while(1); |
| 10116 | #endif |
| 10117 | } |
| 10118 | |
| 10119 | switch (u1ImpCalStage) |
| 10120 | { |
| 10121 | case IMPCAL_STAGE_DRVP: |
| 10122 | u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP; |
| 10123 | break; |
| 10124 | case IMPCAL_STAGE_DRVN: |
| 10125 | u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN; |
| 10126 | break; |
| 10127 | case IMPCAL_STAGE_ODTN: |
| 10128 | u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN; |
| 10129 | break; |
| 10130 | case IMPCAL_STAGE_TRACKING: |
| 10131 | break; |
| 10132 | default: |
| 10133 | mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm u1ImpCalStage for SW IMP Calibration !!!\n")); |
| 10134 | break; |
| 10135 | } |
| 10136 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10137 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10138 | mcSHOW_DBG_MSG3(("[vImpCalVrefSel] IMP_VREF_SEL 0x%x, IMPCAL stage:%u, freq_region:%u\n", |
| 10139 | u1RegTmpValue, u1ImpCalStage, efreq_region)); |
| 10140 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10141 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10142 | if (u1ImpCalStage == IMPCAL_STAGE_TRACKING) { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10143 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10144 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP); |
| 10145 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN); |
| 10146 | } else { |
| 10147 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, u4DrvFld); |
| 10148 | } |
| 10149 | |
| 10150 | return; |
| 10151 | } |
| 10152 | |
| 10153 | void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where) |
| 10154 | { |
| 10155 | U32 backup_broadcast; |
| 10156 | //U8 u1Hysteresis; |
| 10157 | |
| 10158 | backup_broadcast = GetDramcBroadcast(); |
| 10159 | |
| 10160 | DramcBroadcastOnOff(DRAMC_BROADCAST_ON); |
| 10161 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10162 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10163 | vImpCalVrefSel(p, dq_freq_option, IMPCAL_STAGE_TRACKING); |
| 10164 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10165 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10166 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQDRVP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQDRVN2)); |
| 10167 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING2_DQDRVP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING2_DQDRVN1)); |
| 10168 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQODTP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQODTN2)); |
| 10169 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING4_DQODTP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING4_DQODTN1)); |
| 10170 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10171 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10172 | #if SUPPORT_HYNIX_RX_DQS_WEAK_PULL |
| 10173 | if (p->vendor_id == VENDOR_HYNIX) |
| 10174 | { U32 temp_value[4]; |
| 10175 | int i; |
| 10176 | for(i=0; i<4; i++) |
| 10177 | { |
| 10178 | temp_value[i] = SwImpedanceAdjust(gDramcImpedanceResult[dq_freq_option][i], 2); |
| 10179 | } |
| 10180 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[0], SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(temp_value[1], SHU_MISC_DRVING1_DQSDRVN2)); |
| 10181 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[0], SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(temp_value[1], SHU_MISC_DRVING1_DQSDRVN1)); |
| 10182 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[2], SHU_MISC_DRVING3_DQSODTP2) | P_Fld(temp_value[3], SHU_MISC_DRVING3_DQSODTN2)); |
| 10183 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(temp_value[2], SHU_MISC_DRVING3_DQSODTP) | P_Fld(temp_value[3], SHU_MISC_DRVING3_DQSODTN)); |
| 10184 | } |
| 10185 | else |
| 10186 | #endif |
| 10187 | { |
| 10188 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQSDRVP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQSDRVN2)); |
| 10189 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING1 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][DRVP], SHU_MISC_DRVING1_DQSDRVP1) | P_Fld(gDramcImpedanceResult[dq_freq_option][DRVN], SHU_MISC_DRVING1_DQSDRVN1)); |
| 10190 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQSODTP2) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQSODTN2)); |
| 10191 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING3 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[dq_freq_option][ODTP], SHU_MISC_DRVING3_DQSODTP) | P_Fld(gDramcImpedanceResult[dq_freq_option][ODTN], SHU_MISC_DRVING3_DQSODTN)); |
| 10192 | } |
| 10193 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10194 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10195 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP2) | P_Fld(gDramcImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN2)); |
| 10196 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING2 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][DRVP], SHU_MISC_DRVING2_CMDDRVP1) | P_Fld(gDramcImpedanceResult[ca_freq_option][DRVN], SHU_MISC_DRVING2_CMDDRVN1)); |
| 10197 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP2) | P_Fld(gDramcImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN2)); |
| 10198 | vIO32WriteFldMulti((DDRPHY_REG_SHU_MISC_DRVING4 + save_to_where * SHU_GRP_DDRPHY_OFFSET), P_Fld(gDramcImpedanceResult[ca_freq_option][ODTP], SHU_MISC_DRVING4_CMDODTP1) | P_Fld(gDramcImpedanceResult[ca_freq_option][ODTN], SHU_MISC_DRVING4_CMDODTN1)); |
| 10199 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10200 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10201 | #if (fcFOR_CHIP_ID == fcA60868) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10202 | vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVP); |
| 10203 | vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xA, MISC_SHU_DRVING8_CS_DRVN); |
| 10204 | #elif (fcFOR_CHIP_ID == fc8195) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10205 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10206 | vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0xF, MISC_SHU_DRVING8_CS_DRVP); |
| 10207 | vIO32WriteFldAlign((DDRPHY_REG_MISC_SHU_DRVING8 + save_to_where * SHU_GRP_DDRPHY_OFFSET), 0x14, MISC_SHU_DRVING8_CS_DRVN); |
| 10208 | #endif |
| 10209 | |
| 10210 | DramcBroadcastOnOff(backup_broadcast); |
| 10211 | } |
| 10212 | |
| 10213 | #if IMPEDANCE_HW_CALIBRATION |
| 10214 | static void Dramc_Hw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region) |
| 10215 | { |
| 10216 | U8 u1DrvType = 0; |
| 10217 | U32 u4DRVP_Result = 0xff, u4ODTN_Result = 0xff, u4DRVN_Result = 0xff; |
| 10218 | |
| 10219 | vAutoRefreshSwitch(p, ENABLE); |
| 10220 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0), 0, SHU_CONF0_PBREFEN); |
| 10221 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10222 | for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10223 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10224 | if (u1DrvType == ODTP) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10225 | continue; |
| 10226 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10227 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10228 | vImpCalVrefSel(p, freq_region, u1DrvType); |
| 10229 | } |
| 10230 | |
| 10231 | ImpedanceTracking_DisImpHw_Setting(p, DISABLE); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10232 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10233 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), P_Fld(4, SHU_MISC_IMPCAL1_IMPCALCNT) | P_Fld(1, SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE)); |
| 10234 | DramcImpedanceTrackingEnable(p); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10235 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 0, MISC_IMPCAL_IMPCAL_ECO_OPT); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10236 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10237 | mcDELAY_US(16); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10238 | |
| 10239 | u4DRVN_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1); |
| 10240 | u4DRVP_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1); |
| 10241 | u4ODTN_Result = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1); |
| 10242 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10243 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10244 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP); |
| 10245 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVN_Result, SHU_MISC_IMPCAL1_IMPDRVN); |
| 10246 | |
| 10247 | mcSHOW_DBG_MSG(("[HwImpedanceCal] DRVP=%d, DRVN=%d, ODTN=%d\n", u4DRVP_Result, u4DRVN_Result, u4ODTN_Result)); |
| 10248 | |
| 10249 | gDramcImpedanceResult[freq_region][DRVP] = u4DRVP_Result; |
| 10250 | gDramcImpedanceResult[freq_region][DRVN] = u4DRVN_Result; |
| 10251 | gDramcImpedanceResult[freq_region][ODTP] = 0; |
| 10252 | gDramcImpedanceResult[freq_region][ODTN] = u4ODTN_Result; |
| 10253 | |
| 10254 | //vAutoRefreshSwitch(p, DISABLE); |
| 10255 | |
| 10256 | } |
| 10257 | |
| 10258 | #else |
| 10259 | static U32 DramcSwImpCalResult(DRAMC_CTX_T *p, const char *drvType, U32 u4Fld) |
| 10260 | { |
| 10261 | U32 u4ImpxDrv = 0, u4ImpCalResult = 0; |
| 10262 | U32 u4CheckImpChange = (u4Fld == SHU_MISC_IMPCAL1_IMPDRVP)? 1: 0; |
| 10263 | |
| 10264 | for (u4ImpxDrv = 0; u4ImpxDrv < 32; u4ImpxDrv++) |
| 10265 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10266 | #if 0 |
| 10267 | if (u4ImpxDrv == 16) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10268 | u4ImpxDrv = 29; |
| 10269 | #endif |
| 10270 | |
| 10271 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4ImpxDrv, u4Fld); |
| 10272 | mcDELAY_US(1); |
| 10273 | u4ImpCalResult = u4IO32ReadFldAlign((DDRPHY_REG_MISC_PHY_RGS_CMD), MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); |
| 10274 | mcSHOW_DBG_MSG2(("OCD %s=%d ,CALOUT=%d\n", drvType, u4ImpxDrv, u4ImpCalResult)); |
| 10275 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10276 | if (u4ImpCalResult == u4CheckImpChange) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10277 | { |
| 10278 | mcSHOW_DBG_MSG2(("\nOCD %s calibration OK! %s=%d\n\n", drvType, drvType, u4ImpxDrv)); |
| 10279 | break; |
| 10280 | } |
| 10281 | } |
| 10282 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10283 | if (u4ImpxDrv == 32) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10284 | { |
| 10285 | u4ImpxDrv = 31; |
| 10286 | mcSHOW_DBG_MSG2(("\nOCD %s calibration FAIL! %s=%d\n\n", drvType, drvType, u4ImpxDrv)); |
| 10287 | } |
| 10288 | |
| 10289 | return u4ImpxDrv; |
| 10290 | } |
| 10291 | |
| 10292 | static void Dramc_Sw_ImpedanceCal(DRAMC_CTX_T *p, DRAMC_IMP_T freq_region) |
| 10293 | { |
| 10294 | U8 u1DrvType = 0, u1CALI_ENP = 0, u1CALI_ENN = 0; |
| 10295 | U32 u4DRVP_Result = 0xff, u4ODTN_Result = 0xff, u4DRVN_Result = 0xff; |
| 10296 | U32 u4SwImpCalResult = 0, u4DrvFld = 0; |
| 10297 | const char *drvStr = "NULL"; |
| 10298 | |
| 10299 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), 1, MISC_IMPCAL_IMPCAL_CALI_EN); |
| 10300 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVN) | P_Fld(0, SHU_MISC_IMPCAL1_IMPDRVP)); |
| 10301 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10302 | |
| 10303 | for (u1DrvType = DRVP; u1DrvType < IMP_DRV_MAX; u1DrvType++) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10304 | { |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10305 | if (u1DrvType == ODTP) |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10306 | continue; |
| 10307 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10308 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10309 | vImpCalVrefSel(p, freq_region, u1DrvType); |
| 10310 | |
| 10311 | switch (u1DrvType) |
| 10312 | { |
| 10313 | case DRVP: |
| 10314 | drvStr = "DRVP"; |
| 10315 | u1CALI_ENP = 0x1; |
| 10316 | u1CALI_ENN = 0x0; |
| 10317 | u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVP; |
| 10318 | u4DRVP_Result = 0; |
| 10319 | break; |
| 10320 | case DRVN: |
| 10321 | case ODTN: |
| 10322 | drvStr = (u1DrvType == DRVN)? "DRVN" : "ODTN"; |
| 10323 | u1CALI_ENP = 0x0; |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10324 | u1CALI_ENN = (u1DrvType == DRVN)? 0x0: 0x1; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10325 | u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVN; |
| 10326 | break; |
| 10327 | default: |
| 10328 | mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u1DrvType for SW IMP Calibration !!!\n")); |
| 10329 | break; |
| 10330 | } |
| 10331 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10332 | |
| 10333 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENP, MISC_IMPCAL_IMPCAL_CALI_ENP); |
| 10334 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENN, MISC_IMPCAL_IMPCAL_CALI_ENN); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10335 | |
| 10336 | mcSHOW_DBG_MSG2(("\n\n\tK %s\n", drvStr)); |
| 10337 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10338 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10339 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP); |
| 10340 | |
| 10341 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10342 | u4SwImpCalResult = DramcSwImpCalResult(p, drvStr, u4DrvFld); |
| 10343 | |
| 10344 | switch (u1DrvType) |
| 10345 | { |
| 10346 | case DRVP: |
| 10347 | u4DRVP_Result = u4SwImpCalResult; |
| 10348 | break; |
| 10349 | case DRVN: |
| 10350 | u4DRVN_Result = u4SwImpCalResult; |
| 10351 | break; |
| 10352 | case ODTN: |
| 10353 | u4ODTN_Result = u4SwImpCalResult; |
| 10354 | break; |
| 10355 | default: |
| 10356 | mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u4SwImpCalResult for SW IMP Calibration !!!\n")); |
| 10357 | break; |
| 10358 | } |
| 10359 | } |
| 10360 | |
| 10361 | mcSHOW_DBG_MSG(("[SwImpedanceCal] DRVP=%d, DRVN=%d, ODTN=%d\n", u4DRVP_Result, u4DRVN_Result, u4ODTN_Result)); |
| 10362 | |
| 10363 | gDramcImpedanceResult[freq_region][DRVP] = u4DRVP_Result; |
| 10364 | gDramcImpedanceResult[freq_region][DRVN] = u4DRVN_Result; |
| 10365 | gDramcImpedanceResult[freq_region][ODTP] = 0; |
| 10366 | gDramcImpedanceResult[freq_region][ODTN] = u4ODTN_Result; |
| 10367 | |
| 10368 | } |
| 10369 | #endif |
| 10370 | |
| 10371 | DRAM_STATUS_T DramcImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region) |
| 10372 | { |
| 10373 | //U32 u4BaklReg_DDRPHY_MISC_IMP_CTRL0, u4BaklReg_DDRPHY_MISC_IMP_CTRL1; |
| 10374 | //U32 u4BaklReg_DRAMC_REG_IMPCAL; |
| 10375 | U8 backup_channel; |
| 10376 | U32 backup_broadcast; |
| 10377 | U8 u1Drv05 = 0, u1DDR4 = 0; |
| 10378 | |
| 10379 | U32 u4RegBackupAddress[] = |
| 10380 | { |
| 10381 | (DDRPHY_REG_MISC_IMPCAL), |
| 10382 | #if IMPEDANCE_HW_CALIBRATION |
| 10383 | (DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR), |
| 10384 | (DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0)), |
| 10385 | (DRAMC_REG_DRAMC_PD_CTRL), |
| 10386 | (DRAMC_REG_DRAMC_PD_CTRL+ SHIFT_TO_CHB_ADDR), |
| 10387 | #if (CHANNEL_NUM > 2) |
| 10388 | (DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR), |
| 10389 | (DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR), |
| 10390 | #endif |
| 10391 | (DDRPHY_REG_MISC_CTRL0), |
| 10392 | (DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR), |
| 10393 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING1)), |
| 10394 | (DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING2)), |
| 10395 | (DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0)), |
| 10396 | #endif |
| 10397 | }; |
| 10398 | |
| 10399 | backup_broadcast = GetDramcBroadcast(); |
| 10400 | DramcBroadcastOnOff(DRAMC_BROADCAST_OFF); |
| 10401 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10402 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10403 | vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_FAIL); |
| 10404 | |
| 10405 | #if VENDER_JV_LOG |
| 10406 | vPrintCalibrationBasicInfo_ForJV(p); |
| 10407 | #else |
| 10408 | vPrintCalibrationBasicInfo(p); |
| 10409 | #endif |
| 10410 | |
| 10411 | mcSHOW_DBG_MSG(("[DramcImpedenceCal]\n")); |
| 10412 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10413 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10414 | vIO32WriteFldMulti_All(DDRPHY_REG_MISC_LP_CTRL, P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10) | \ |
| 10415 | P_Fld(0x0, MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL) | \ |
| 10416 | P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10) | \ |
| 10417 | P_Fld(0x0, MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL)); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10418 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10419 | vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 0, MISC_IMPCAL_IMPCAL_HW); |
| 10420 | backup_channel = p->channel; |
| 10421 | vSetPHY2ChannelMapping(p, CHANNEL_A); |
| 10422 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10423 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10424 | //u4BaklReg_DDRPHY_MISC_IMP_CTRL0 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL0)); |
| 10425 | //u4BaklReg_DDRPHY_MISC_IMP_CTRL1 = u4IO32Read4B((DDRPHY_MISC_IMP_CTRL1)); |
| 10426 | //u4BaklReg_DRAMC_REG_IMPCAL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL)); |
| 10427 | DramcBackupRegisters(p, u4RegBackupAddress, ARRAY_SIZE(u4RegBackupAddress)); |
| 10428 | |
| 10429 | #if IMPEDANCE_HW_CALIBRATION |
| 10430 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0), 1, DDRCOMMON0_LPDDR4EN); |
| 10431 | vIO32WriteFldMulti_All(DRAMC_REG_DRAMC_PD_CTRL, P_Fld(1, DRAMC_PD_CTRL_PHYCLKDYNGEN)\ |
| 10432 | | P_Fld(1, DRAMC_PD_CTRL_DCMEN)); |
| 10433 | #endif |
| 10434 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10435 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10436 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), 0, MISC_IMP_CTRL1_RG_RIMP_PRE_EN); |
| 10437 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), P_Fld(0, MISC_IMPCAL_IMPCAL_CALI_ENN) | P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDP) | \ |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10438 | P_Fld(1, MISC_IMPCAL_IMPCAL_IMPPDN)); |
Ryan Chuang | 98affb6 | 2021-09-23 20:35:22 +0800 | [diff] [blame] | 10439 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10440 | u1DDR4 = 1; |
| 10441 | |
| 10442 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMP_CTRL1), P_Fld(1, MISC_IMP_CTRL1_RG_IMP_EN) | \ |
| 10443 | P_Fld(0, MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL) | \ |
| 10444 | P_Fld(1, MISC_IMP_CTRL1_RG_RIMP_VREF_EN) | \ |
| 10445 | P_Fld(u1DDR4, MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL)); |
| 10446 | mcDELAY_US(1); |
| 10447 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10448 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10449 | vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1Drv05, SHU_CA_CMD12_RG_RIMP_DRV05); |
| 10450 | |
| 10451 | #if IMPEDANCE_HW_CALIBRATION |
| 10452 | Dramc_Hw_ImpedanceCal(p, freq_region); |
| 10453 | #else |
| 10454 | Dramc_Sw_ImpedanceCal(p, freq_region); |
| 10455 | #endif |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10456 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10457 | DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32)); |
| 10458 | //vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u4BaklReg_DRAMC_REG_IMPCAL); |
| 10459 | //vIO32Write4B((DDRPHY_MISC_IMP_CTRL0), u4BaklReg_DDRPHY_MISC_IMP_CTRL0); |
| 10460 | //vIO32Write4B((DDRPHY_MISC_IMP_CTRL1), u4BaklReg_DDRPHY_MISC_IMP_CTRL1); |
| 10461 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10462 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10463 | |
| 10464 | #if 0 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10465 | if (u1Para) |
| 10466 | { |
| 10467 | u4ODTN_Result = ImpedanceAdjustment_Hynix(u4ODTN_Result, u1Para); |
| 10468 | } |
| 10469 | #endif |
| 10470 | |
| 10471 | #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 10472 | { |
| 10473 | U8 u1drv; |
| 10474 | { |
| 10475 | for (u1drv = 0; u1drv < 4; u1drv++) |
| 10476 | { |
| 10477 | { |
| 10478 | gDramcImpedanceResult[freq_region][u1drv] = p->pSavetimeData->u1SwImpedanceResule[freq_region][u1drv]; |
| 10479 | vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_FAST_K); |
| 10480 | } |
| 10481 | } |
| 10482 | } |
| 10483 | } |
| 10484 | #endif |
| 10485 | |
| 10486 | mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", freq_region, gDramcImpedanceResult[freq_region][DRVP], |
| 10487 | gDramcImpedanceResult[freq_region][DRVN], gDramcImpedanceResult[freq_region][ODTN])); |
| 10488 | |
| 10489 | #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST |
| 10490 | if ((p->dram_type == TYPE_LPDDR4) && (freq_region == 0)) |
| 10491 | { |
| 10492 | gDramcImpedanceResult[freq_region][DRVP] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][DRVP], gDramcSwImpedanceAdjust[freq_region][DRVP]); |
| 10493 | gDramcImpedanceResult[freq_region][DRVN] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][DRVN], gDramcSwImpedanceAdjust[freq_region][ODTN]); |
| 10494 | } |
| 10495 | else |
| 10496 | { |
| 10497 | gDramcImpedanceResult[freq_region][DRVP] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][DRVP], gDramcSwImpedanceAdjust[freq_region][DRVP]); |
| 10498 | gDramcImpedanceResult[freq_region][ODTN] = SwImpedanceAdjust(gDramcImpedanceResult[freq_region][ODTN], gDramcSwImpedanceAdjust[freq_region][ODTN]); |
| 10499 | } |
| 10500 | |
| 10501 | mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d (After Adjust)\n", freq_region, gDramcImpedanceResult[freq_region][DRVP], |
| 10502 | gDramcImpedanceResult[freq_region][DRVN], gDramcImpedanceResult[freq_region][ODTN])); |
| 10503 | #endif |
| 10504 | |
| 10505 | #if 0 |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10506 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10507 | if (gDramcSwImpedanceResult[freq_region][DRVP] >= 31 && (freq_region == 0) ) { |
| 10508 | mcSHOW_DBG_MSG(("SLT_BIN2\n")); |
| 10509 | while (1); |
| 10510 | } |
| 10511 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10512 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10513 | if (freq_region==0) |
| 10514 | { |
| 10515 | if (!(gDramcImpedanceResult[freq_region][DRVP] >= 1 && gDramcImpedanceResult[freq_region][DRVP] <= 0x16) || |
| 10516 | !(gDramcImpedanceResult[freq_region][DRVN] >= 10 && gDramcImpedanceResult[freq_region][DRVN] <= 23) || |
| 10517 | !(gDramcImpedanceResult[freq_region][ODTN] >= 3 && gDramcImpedanceResult[freq_region][ODTN] <= 0x13)) { |
| 10518 | #if defined(SLT) |
| 10519 | mcSHOW_ERR_MSG(("[DramcInit] SLT_BIN2\n")); |
| 10520 | while (1); |
| 10521 | #else |
| 10522 | mcSHOW_ERR_MSG(("[Warning] freq_region = %d, Unexpected value for impedance calibration\n", freq_region)); |
| 10523 | #if __ETT__ |
| 10524 | while (1); |
| 10525 | #endif |
| 10526 | #endif |
| 10527 | }else{ |
| 10528 | vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_OK); |
| 10529 | } |
| 10530 | } |
| 10531 | else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10532 | { |
| 10533 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10534 | if (!(gDramcImpedanceResult[freq_region][DRVP] >= 1 && gDramcImpedanceResult[freq_region][DRVP] <= 24) || |
| 10535 | !(gDramcImpedanceResult[freq_region][DRVN] >= 10 && gDramcImpedanceResult[freq_region][DRVN] <= 30) || |
| 10536 | !(gDramcImpedanceResult[freq_region][ODTN] >= 3 && gDramcImpedanceResult[freq_region][ODTN] <= 12)) { |
| 10537 | #if defined(SLT) |
| 10538 | mcSHOW_ERR_MSG(("[DramcInit] SLT_BIN2\n")); |
| 10539 | while (1); |
| 10540 | #else |
| 10541 | mcSHOW_ERR_MSG(("[Warning] freq_region = %d, Unexpected value for impedance calibration\n", freq_region)); |
| 10542 | #if __ETT__ |
| 10543 | while (1); |
| 10544 | #endif |
| 10545 | #endif |
| 10546 | }else{ |
| 10547 | vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_OK); |
| 10548 | } |
| 10549 | } |
| 10550 | #endif |
| 10551 | |
| 10552 | #if PIN_CHECK_TOOL |
| 10553 | if((gDramcImpedanceResult[freq_region][ODTN] ==0)||(gDramcImpedanceResult[freq_region][ODTN] >=31)) |
| 10554 | { |
| 10555 | mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, ODTN = %d ==> unexpect value\n", freq_region, gDramcImpedanceResult[freq_region][ODTN])); |
| 10556 | PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+ODTN)); |
| 10557 | } |
| 10558 | else if((gDramcImpedanceResult[freq_region][DRVP] ==0)||(gDramcImpedanceResult[freq_region][DRVP] >=31)) |
| 10559 | { |
| 10560 | mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVP = %d ==> unexpect value\n", freq_region, gDramcImpedanceResult[freq_region][DRVP])); |
| 10561 | PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVP)); |
| 10562 | } |
| 10563 | else if((gDramcImpedanceResult[freq_region][DRVN] ==0)||(gDramcImpedanceResult[freq_region][DRVN] >=31)) |
| 10564 | { |
| 10565 | mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVN = %d ==> unexpect value\n", freq_region, gDramcImpedanceResult[freq_region][DRVN])); |
| 10566 | PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVN)); |
| 10567 | } |
| 10568 | #endif |
| 10569 | |
| 10570 | mcSHOW_DBG_MSG4(("[DramcImpedanceCal] Done\n\n")); |
| 10571 | |
| 10572 | vSetPHY2ChannelMapping(p, backup_channel); |
| 10573 | DramcBroadcastOnOff(backup_broadcast); |
| 10574 | |
| 10575 | return DRAM_OK; |
| 10576 | } |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10577 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10578 | |
| 10579 | #if ENABLE_WRITE_DBI || TX_K_DQM_WITH_WDBI |
| 10580 | void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK) |
| 10581 | { |
| 10582 | U8 ucDataRateDivShift = 0; |
| 10583 | S8 s1UIMove = 0; |
| 10584 | |
| 10585 | ucDataRateDivShift = u1MCK2UI_DivShift(p); |
| 10586 | s1UIMove = iShiftMCK * (S8)(1 << ucDataRateDivShift); |
| 10587 | ShiftDQUI(p, s1UIMove, ALL_BYTES); |
| 10588 | } |
| 10589 | #endif |
| 10590 | |
| 10591 | #if ENABLE_DUTY_SCAN_V2 |
| 10592 | |
| 10593 | #define DutyPrintAllLog 0 |
| 10594 | |
| 10595 | #define DUTY_OFFSET_START -28 |
| 10596 | #define DUTY_OFFSET_END 28 |
| 10597 | #define DUTY_OFFSET_STEP 4 |
| 10598 | |
| 10599 | #define CLOCK_PI_START 0 |
| 10600 | #define CLOCK_PI_END 63 |
| 10601 | |
| 10602 | #if FOR_DV_SIMULATION_USED |
| 10603 | #define CLOCK_PI_STEP 8 |
| 10604 | #else |
| 10605 | #define CLOCK_PI_STEP 2 |
| 10606 | #endif |
| 10607 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10608 | #define ClockDutyFailLowerBound 4500 |
| 10609 | #define ClockDutyFailUpperBound 5500 |
| 10610 | #define ClockDutyMiddleBound 5000 |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10611 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10612 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10613 | static U8 DramcDutyDelayRGSettingConvert(DRAMC_CTX_T *p, S8 scDutyDelay, |
| 10614 | U8 *tDly) |
| 10615 | { |
| 10616 | U8 tDelay; |
| 10617 | |
| 10618 | if (scDutyDelay < 0) |
| 10619 | { |
| 10620 | tDelay = -scDutyDelay; |
| 10621 | } |
| 10622 | else if (scDutyDelay > 0) |
| 10623 | { |
| 10624 | tDelay = scDutyDelay + (1 << 5); |
| 10625 | } |
| 10626 | else |
| 10627 | { |
| 10628 | tDelay = 0; |
| 10629 | } |
| 10630 | |
| 10631 | *tDly = tDelay; |
| 10632 | return tDelay; |
| 10633 | } |
| 10634 | |
| 10635 | static void DramcClockDutySetClkDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay) |
| 10636 | { |
| 10637 | U8 u1ShuffleIdx = 0; |
| 10638 | U32 save_offset; |
| 10639 | U8 tDelay; |
| 10640 | |
| 10641 | DramcDutyDelayRGSettingConvert(p, scDutyDelay[0], &tDelay); |
| 10642 | |
| 10643 | #if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ |
| 10644 | for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) |
| 10645 | #endif |
| 10646 | { |
| 10647 | save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET; |
| 10648 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_TXDUTY + save_offset), |
| 10649 | P_Fld(tDelay, SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY)); |
| 10650 | } |
| 10651 | } |
| 10652 | |
| 10653 | static void DQSDutyScan_SetDqsDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay) |
| 10654 | { |
| 10655 | U8 u1ShuffleIdx = 0, u1DQSIdx; |
| 10656 | U32 save_offset; |
| 10657 | U8 tDelay[2]; |
| 10658 | |
| 10659 | // mcSHOW_DBG_MSG(("CH%d, Final DQS0 duty delay cell = %d\n", p->channel, scDutyDelay[0])); |
| 10660 | // mcSHOW_DBG_MSG(("CH%d, Final DQS1 duty delay cell = %d\n", p->channel, scDutyDelay[1])); |
| 10661 | |
| 10662 | for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++) |
| 10663 | { |
| 10664 | DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx])); |
| 10665 | } |
| 10666 | |
| 10667 | #if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ |
| 10668 | for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) |
| 10669 | #endif |
| 10670 | { |
| 10671 | { |
| 10672 | for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++) |
| 10673 | { |
| 10674 | save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET; |
| 10675 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset, |
| 10676 | P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0)); |
| 10677 | } |
| 10678 | } |
| 10679 | } |
| 10680 | } |
| 10681 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10682 | #if APPLY_DQDQM_DUTY_CALIBRATION |
| 10683 | static void DQDQMDutyScan_SetDQDQMDelayCell(DRAMC_CTX_T *p, U8 u1ChannelIdx, S8 *scDutyDelay, U8 k_type) |
| 10684 | { |
| 10685 | U8 u1ShuffleIdx = 0, u1DQSIdx; |
| 10686 | U32 save_offset; |
| 10687 | U8 tDelay[2]; |
| 10688 | |
| 10689 | for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++) |
| 10690 | { |
| 10691 | DramcDutyDelayRGSettingConvert(p, scDutyDelay[u1DQSIdx], &(tDelay[u1DQSIdx])); |
| 10692 | } |
| 10693 | |
| 10694 | #if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ |
| 10695 | for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) |
| 10696 | #endif |
| 10697 | { |
| 10698 | for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++) |
| 10699 | { |
| 10700 | save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET; |
| 10701 | |
| 10702 | if (k_type == DutyScan_Calibration_K_DQ) |
| 10703 | { |
| 10704 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset, |
| 10705 | P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0)); |
| 10706 | } |
| 10707 | |
| 10708 | if (k_type == DutyScan_Calibration_K_DQM) |
| 10709 | { |
| 10710 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY) + save_offset, |
| 10711 | P_Fld(tDelay[u1DQSIdx], SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0)); |
| 10712 | } |
| 10713 | } |
| 10714 | } |
| 10715 | } |
| 10716 | |
| 10717 | #if 0 |
| 10718 | void DQDQMDutyScan_CopyDQRG2DQMRG(DRAMC_CTX_T *p) |
| 10719 | { |
| 10720 | U8 u1ShuffleIdx = 0, u1DQSIdx, u1RankIdx = 0; |
| 10721 | U32 save_offset; |
| 10722 | U8 ucDQDQMDelay; |
| 10723 | U8 ucRev_DQDQM_Bit0, ucRev_DQDQM_Bit1; |
| 10724 | |
| 10725 | #if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ |
| 10726 | for(u1ShuffleIdx = 0; u1ShuffleIdx<DRAM_DFS_SRAM_MAX; u1ShuffleIdx++) |
| 10727 | #endif |
| 10728 | { |
| 10729 | for(u1DQSIdx = 0; u1DQSIdx<2; u1DQSIdx++) |
| 10730 | { |
| 10731 | save_offset = u1ShuffleIdx * SHU_GRP_DDRPHY_OFFSET + u1DQSIdx*DDRPHY_AO_B0_B1_OFFSET_0X80; |
| 10732 | |
| 10733 | ucDQDQMDelay = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0_DQ_DLY); |
| 10734 | ucRev_DQDQM_Bit0 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0_BIT0); |
| 10735 | ucRev_DQDQM_Bit1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0_BIT0); |
| 10736 | |
| 10737 | vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_SHU_B0_DQ3) + save_offset, P_Fld(ucDQDQMDelay, SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0_DQM_DLY) |
| 10738 | | P_Fld(ucRev_DQDQM_Bit0, SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0_BIT0) |
| 10739 | | P_Fld(ucRev_DQDQM_Bit1, SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0_BIT1)); |
| 10740 | } |
| 10741 | } |
| 10742 | } |
| 10743 | #endif |
| 10744 | #endif |
| 10745 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10746 | S8 gcFinal_K_CLK_delay_cell[DQS_BYTE_NUMBER]; |
| 10747 | S8 gcFinal_K_DQS_delay_cell[DQS_BYTE_NUMBER]; |
| 10748 | S8 gcFinal_K_WCK_delay_cell[DQS_BYTE_NUMBER]; |
| 10749 | #if APPLY_DQDQM_DUTY_CALIBRATION |
| 10750 | S8 gcFinal_K_DQ_delay_cell[DQS_BYTE_NUMBER]; |
| 10751 | S8 gcFinal_K_DQM_delay_cell[DQS_BYTE_NUMBER]; |
| 10752 | #endif |
| 10753 | typedef struct _TEST_DUTY_AVG_LOG_PARAMETER_T |
| 10754 | { |
| 10755 | U32 ucmost_approach_50_percent; |
| 10756 | S8 scFinal_clk_delay_cell; |
| 10757 | U32 ucFinal_period_duty_averige; |
| 10758 | U32 ucFinal_period_duty_max; |
| 10759 | U32 ucFinal_period_duty_min; |
| 10760 | U32 ucFinal_duty_max_clk_dly; |
| 10761 | U32 ucFinal_duty_min_clk_dly; |
| 10762 | } TEST_DUTY_AVG_LOG_PARAMETER_T; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10763 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10764 | void DramcNewDutyCalibration(DRAMC_CTX_T *p) |
| 10765 | { |
| 10766 | U8 u1backup_rank; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10767 | BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10768 | U32 backup_DDRPHY_REG_B0_DQ2=0, backup_DDRPHY_REG_B1_DQ2=0, backup_DDRPHY_REG_CA_CMD2=0; |
| 10769 | U32 backup_DDRPHY_REG_SHU_B0_DQ13=0, backup_DDRPHY_REG_SHU_B1_DQ13=0, backup_DDRPHY_REG_SHU_CA_CMD13=0; |
| 10770 | |
| 10771 | #if(DQS_DUTY_SLT_CONDITION_TEST) |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10772 | U16 u2TestCnt, u2FailCnt=0, u2TestCntTotal =20; |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10773 | U8 u1ByteIdx, u1PI_FB; |
| 10774 | U32 u4Variance; |
| 10775 | #endif |
| 10776 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10777 | |
| 10778 | u1backup_rank = u1GetRank(p); |
| 10779 | vSetRank(p, RANK_0); |
| 10780 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10781 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10782 | backup_DDRPHY_REG_B0_DQ2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2)); |
| 10783 | if (!isLP4_DSC) |
| 10784 | backup_DDRPHY_REG_B1_DQ2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2)); |
| 10785 | else |
| 10786 | backup_DDRPHY_REG_CA_CMD2 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2)); |
| 10787 | backup_DDRPHY_REG_SHU_B0_DQ13 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13)); |
| 10788 | if (!isLP4_DSC) |
| 10789 | backup_DDRPHY_REG_SHU_B1_DQ13 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13)); |
| 10790 | else |
| 10791 | backup_DDRPHY_REG_SHU_CA_CMD13 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13)); |
| 10792 | |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10793 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10794 | vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAIL); |
| 10795 | |
| 10796 | #if !FT_DSIM_USED |
| 10797 | #if DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ |
| 10798 | if (p->frequency == u2DFSGetHighestFreq(p)) |
| 10799 | #else |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10800 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10801 | #endif |
| 10802 | #endif |
| 10803 | { |
Ryan Chuang | c6ed254 | 2021-07-06 17:12:27 +0800 | [diff] [blame] | 10804 | U8 u1ChannelIdx; |
| 10805 | U8 u1backup_channel = vGetPHY2ChannelMapping(p); |
| 10806 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10807 | #if SUPPORT_SAVE_TIME_FOR_CALIBRATION |
| 10808 | if(p->femmc_Ready==1) |
| 10809 | { |
Ryan Chuang | c6ed254 | 2021-07-06 17:12:27 +0800 | [diff] [blame] | 10810 | for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){ |
| 10811 | vSetPHY2ChannelMapping(p, u1ChannelIdx); |
| 10812 | |
| 10813 | DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); |
| 10814 | DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); |
Ryan Chuang | c6ed254 | 2021-07-06 17:12:27 +0800 | [diff] [blame] | 10815 | #if APPLY_DQDQM_DUTY_CALIBRATION |
| 10816 | DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); |
| 10817 | DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); |
| 10818 | #endif |
| 10819 | } |
| 10820 | vSetPHY2ChannelMapping(p, u1backup_channel); |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10821 | |
| 10822 | vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K); |
| 10823 | return; |
| 10824 | } |
| 10825 | #endif |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10826 | } |
| 10827 | |
| 10828 | OECKCKE_Control(p, ENABLE); |
Ryan Chuang | 3927755 | 2021-10-26 20:01:01 +0800 | [diff] [blame] | 10829 | |
Ryan Chuang | b0b8dc3 | 2021-05-06 23:48:18 +0800 | [diff] [blame] | 10830 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2), backup_DDRPHY_REG_B0_DQ2); |
| 10831 | if (!isLP4_DSC) |
| 10832 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2), backup_DDRPHY_REG_B1_DQ2); |
| 10833 | else |
| 10834 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), backup_DDRPHY_REG_CA_CMD2); |
| 10835 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13), backup_DDRPHY_REG_SHU_B0_DQ13); |
| 10836 | if (!isLP4_DSC) |
| 10837 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13), backup_DDRPHY_REG_SHU_B1_DQ13); |
| 10838 | else |
| 10839 | vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), backup_DDRPHY_REG_SHU_CA_CMD13); |
| 10840 | |
| 10841 | |
| 10842 | vSetRank(p, u1backup_rank); |
| 10843 | } |
| 10844 | #endif |