blob: 5629e6bfdc7cef28cf071d61e56fa18dc7ed3a0c [file] [log] [blame]
Angel Ponsbbc99cf2020-04-04 18:51:23 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Shunqian Zheng015ae112016-04-20 20:35:09 +08002
Kyösti Mälkki13f66502019-03-03 08:01:05 +02003#include <device/mmio.h>
Lin Huang589474f2017-08-02 16:59:06 +08004#include <assert.h>
Shunqian Zheng015ae112016-04-20 20:35:09 +08005#include <gpio.h>
Shunqian Zheng015ae112016-04-20 20:35:09 +08006#include <soc/grf.h>
7#include <soc/soc.h>
Elyes HAOUAS27d02d82019-05-15 21:11:39 +02008#include <types.h>
Shunqian Zheng015ae112016-04-20 20:35:09 +08009
Julius Werner2768a112016-09-01 22:55:58 -070010static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir)
11{
Julius Werner55009af2019-12-02 22:03:27 -080012 clrsetbits32(&gpio_port[gpio.port]->swporta_ddr,
13 1 << gpio.num, dir << gpio.num);
Julius Werner2768a112016-09-01 22:55:58 -070014}
15
16static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull)
Shunqian Zheng015ae112016-04-20 20:35:09 +080017{
Shunqian Zheng74bb4122016-05-17 14:00:04 +080018 u32 pull_val = gpio_get_pull_val(gpio, pull);
Julius Wernercd49cce2019-03-05 16:53:33 -080019 if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288))
Julius Werner55009af2019-12-02 22:03:27 -080020 clrsetbits32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2),
21 pull_val << (gpio.idx * 2));
Shunqian Zheng015ae112016-04-20 20:35:09 +080022 else
23 write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2),
Shunqian Zheng74bb4122016-05-17 14:00:04 +080024 pull_val << (gpio.idx * 2)));
Shunqian Zheng015ae112016-04-20 20:35:09 +080025}
26
27void gpio_input(gpio_t gpio)
28{
Julius Werner2768a112016-09-01 22:55:58 -070029 gpio_set_pull(gpio, GPIO_PULLNONE);
30 gpio_set_dir(gpio, GPIO_INPUT);
Shunqian Zheng015ae112016-04-20 20:35:09 +080031}
32
33void gpio_input_pulldown(gpio_t gpio)
34{
Julius Werner2768a112016-09-01 22:55:58 -070035 gpio_set_pull(gpio, GPIO_PULLDOWN);
36 gpio_set_dir(gpio, GPIO_INPUT);
Shunqian Zheng015ae112016-04-20 20:35:09 +080037}
38
39void gpio_input_pullup(gpio_t gpio)
40{
Julius Werner2768a112016-09-01 22:55:58 -070041 gpio_set_pull(gpio, GPIO_PULLUP);
42 gpio_set_dir(gpio, GPIO_INPUT);
Shunqian Zheng015ae112016-04-20 20:35:09 +080043}
44
Lin Huang589474f2017-08-02 16:59:06 +080045void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull)
Jeffy Chenb0b59872017-03-03 18:24:02 +080046{
47 uint32_t int_polarity, inttype_level;
48 uint32_t mask = BIT(gpio.num);
49
Lin Huang589474f2017-08-02 16:59:06 +080050 /* gpio pull only PULLNONE, PULLUP, PULLDOWN status */
51 assert(pull <= GPIO_PULLDOWN);
52
53 gpio_set_dir(gpio, GPIO_INPUT);
54 gpio_set_pull(gpio, pull);
Jeffy Chenb0b59872017-03-03 18:24:02 +080055
56 int_polarity = inttype_level = 0;
57 switch (type) {
58 case IRQ_TYPE_EDGE_RISING:
59 int_polarity = mask;
60 inttype_level = mask;
61 break;
62 case IRQ_TYPE_EDGE_FALLING:
63 inttype_level = mask;
64 break;
65 case IRQ_TYPE_LEVEL_HIGH:
66 int_polarity = mask;
67 break;
68 case IRQ_TYPE_LEVEL_LOW:
69 break;
70 }
Julius Werner55009af2019-12-02 22:03:27 -080071 clrsetbits32(&gpio_port[gpio.port]->int_polarity,
72 mask, int_polarity);
73 clrsetbits32(&gpio_port[gpio.port]->inttype_level,
74 mask, inttype_level);
Jeffy Chenb0b59872017-03-03 18:24:02 +080075
Julius Werner55009af2019-12-02 22:03:27 -080076 setbits32(&gpio_port[gpio.port]->inten, mask);
77 clrbits32(&gpio_port[gpio.port]->intmask, mask);
Jeffy Chenb0b59872017-03-03 18:24:02 +080078}
79
80int gpio_irq_status(gpio_t gpio)
81{
82 uint32_t mask = BIT(gpio.num);
83 uint32_t int_status = read32(&gpio_port[gpio.port]->int_status);
84
85 if (!(int_status & mask))
86 return 0;
87
Julius Werner55009af2019-12-02 22:03:27 -080088 setbits32(&gpio_port[gpio.port]->porta_eoi, mask);
Jeffy Chenb0b59872017-03-03 18:24:02 +080089 return 1;
90}
91
Shunqian Zheng015ae112016-04-20 20:35:09 +080092int gpio_get(gpio_t gpio)
93{
94 return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;
95}
96
Julius Wernerffeee422018-03-27 16:22:00 -070097void gpio_set(gpio_t gpio, int value)
Shunqian Zheng015ae112016-04-20 20:35:09 +080098{
Julius Werner55009af2019-12-02 22:03:27 -080099 clrsetbits32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,
100 !!value << gpio.num);
Julius Wernerffeee422018-03-27 16:22:00 -0700101}
102
103void gpio_output(gpio_t gpio, int value)
104{
105 gpio_set(gpio, value);
Julius Werner2768a112016-09-01 22:55:58 -0700106 gpio_set_dir(gpio, GPIO_OUTPUT);
107 gpio_set_pull(gpio, GPIO_PULLNONE);
Shunqian Zheng015ae112016-04-20 20:35:09 +0800108}