Prasad Malisetty | 78298f5 | 2022-07-25 13:35:05 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <device/pci.h> |
Prasad Malisetty | 78298f5 | 2022-07-25 13:35:05 +0530 | [diff] [blame] | 7 | #include <gpio.h> |
| 8 | #include <soc/addressmap.h> |
| 9 | #include <soc/clock.h> |
Prasad Malisetty | 78298f5 | 2022-07-25 13:35:05 +0530 | [diff] [blame] | 10 | #include <soc/qcom_qmp_phy.h> |
| 11 | #include <soc/pcie.h> |
| 12 | |
| 13 | #if CONFIG(BOARD_GOOGLE_SENOR) |
| 14 | #define NVME_REG_EN GPIO(19) |
| 15 | #else |
| 16 | /* For Herobrine board and all variants */ |
| 17 | #define NVME_REG_EN GPIO(51) |
| 18 | #endif |
| 19 | |
| 20 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_serdes_tbl[] = { |
| 21 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), |
| 22 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), |
| 23 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), |
| 24 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), |
| 25 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), |
| 26 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), |
| 27 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), |
| 28 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), |
| 29 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), |
| 30 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
| 31 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), |
| 32 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), |
| 33 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), |
| 34 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), |
| 35 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), |
| 36 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), |
| 37 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), |
| 38 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), |
| 39 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), |
| 40 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), |
| 41 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), |
| 42 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), |
| 43 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), |
| 44 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), |
| 45 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), |
| 46 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), |
| 47 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), |
| 48 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), |
| 49 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), |
| 50 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
| 51 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
| 52 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
| 53 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), |
| 54 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), |
| 55 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), |
| 56 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), |
| 57 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
| 58 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
| 59 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
| 60 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
| 61 | QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), |
| 62 | }; |
| 63 | |
| 64 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_tx_tbl[] = { |
| 65 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
| 66 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), |
| 67 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), |
| 68 | }; |
| 69 | |
| 70 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_rx_tbl[] = { |
| 71 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
| 72 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), |
| 73 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), |
| 74 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
| 75 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
| 76 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), |
| 77 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), |
| 78 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), |
| 79 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
| 80 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
| 81 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), |
| 82 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), |
| 83 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), |
| 84 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
| 85 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
| 86 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), |
| 87 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), |
| 88 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), |
| 89 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), |
| 90 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), |
| 91 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), |
| 92 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), |
| 93 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), |
| 94 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), |
| 95 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), |
| 96 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), |
| 97 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), |
| 98 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), |
| 99 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), |
| 100 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), |
| 101 | }; |
| 102 | |
| 103 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_pcs_tbl[] = { |
| 104 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| 105 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), |
| 106 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), |
| 107 | }; |
| 108 | |
| 109 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_pcie_pcs_misc_tbl[] = { |
| 110 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
| 111 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| 112 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| 113 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), |
| 114 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), |
| 115 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), |
| 116 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
| 117 | }; |
| 118 | |
| 119 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_tx_tbl[] = { |
| 120 | QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), |
| 121 | }; |
| 122 | |
| 123 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_rx_tbl[] = { |
| 124 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), |
| 125 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), |
| 126 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), |
| 127 | QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
| 128 | }; |
| 129 | |
| 130 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_pcs_tbl[] = { |
| 131 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), |
| 132 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), |
| 133 | }; |
| 134 | |
| 135 | static const struct qcom_qmp_phy_init_tbl sc7280_qmp_gen3x2_pcie_misc_tbl[] = { |
| 136 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), |
| 137 | QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
| 138 | }; |
| 139 | |
| 140 | static pcie_cntlr_cfg_t pcie_host = { |
Elyes Haouas | 9776738 | 2022-11-18 15:08:13 +0100 | [diff] [blame] | 141 | .parf = (void *)PCIE1_PCIE_PARF, |
| 142 | .dbi_base = (void *)PCIE1_GEN3X2_PCIE_DBI, |
| 143 | .elbi = (void *)PCIE1_GEN3X2_PCIE_ELBI, |
| 144 | .atu_base = (void *)PCIE1_GEN3X2_DWC_PCIE_DM_IATU, |
| 145 | .cfg_base = (void *)PCIE1_GEN3X2_PCIE_DBI + PCIE_EP_CONF_OFFSET, |
| 146 | .pcie_bcr = (void *)PCIE1_BCR, |
| 147 | .qmp_phy_bcr = (void *)GCC_PCIE_1_PHY_BCR, |
Prasad Malisetty | 78298f5 | 2022-07-25 13:35:05 +0530 | [diff] [blame] | 148 | .lanes = PCIE_3x2_NUM_LANES, |
| 149 | .cfg_size = PCIE_EP_CONF_SIZE, |
| 150 | .perst = GPIO(2), |
| 151 | |
| 152 | /* Store the IO and MEM space settings for future use by the ATU */ |
| 153 | .io.phys_start = PCIE1_GEN3X2_PCIE_DBI + PCIE_IO_SPACE_OFFSET, |
| 154 | .io.size = PCIE_IO_SPACE_SIZE, |
| 155 | |
| 156 | .mem.phys_start = PCIE1_GEN3X2_PCIE_DBI + PCIE_MMIO_SPACE_OFFSET, |
| 157 | .mem.size = PCIE1_SPACE_END_ADDR, |
| 158 | }; |
| 159 | |
| 160 | static pcie_qmp_phy_cfg_t pcie1_qmp_phy_3x2 = { |
Elyes Haouas | 9776738 | 2022-11-18 15:08:13 +0100 | [diff] [blame] | 161 | .qmp_phy_base = (void *)PCIE_1_QMP_PHY, |
| 162 | .serdes = (void *)PCE1_QPHY_SERDES, |
| 163 | .tx0 = (void *)PCE1_QPHY_TX0, |
| 164 | .rx0 = (void *)PCE1_QPHY_RX0, |
| 165 | .pcs = (void *)PCIE1_QMP_PHY_PCS_COM, |
| 166 | .tx1 = (void *)PCE1_QPHY_TX1, |
| 167 | .rx1 = (void *)PCE1_QPHY_RX1, |
| 168 | .pcs_misc = (void *)PCE1_QPHY_PCS_MISC, |
Prasad Malisetty | 78298f5 | 2022-07-25 13:35:05 +0530 | [diff] [blame] | 169 | .serdes_tbl = sc7280_qmp_pcie_serdes_tbl, |
| 170 | .serdes_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_serdes_tbl), |
| 171 | .tx_tbl = sc7280_qmp_pcie_tx_tbl, |
| 172 | .tx_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_tx_tbl), |
| 173 | .tx_tbl_sec = sc7280_qmp_gen3x2_pcie_tx_tbl, |
| 174 | .tx_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_tx_tbl), |
| 175 | .rx_tbl = sc7280_qmp_pcie_rx_tbl, |
| 176 | .rx_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_rx_tbl), |
| 177 | .rx_tbl_sec = sc7280_qmp_gen3x2_pcie_rx_tbl, |
| 178 | .rx_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_rx_tbl), |
| 179 | .pcs_tbl = sc7280_qmp_pcie_pcs_tbl, |
| 180 | .pcs_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_pcs_tbl), |
| 181 | .pcs_tbl_sec = sc7280_qmp_gen3x2_pcie_pcs_tbl, |
| 182 | .pcs_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_pcs_tbl), |
| 183 | .pcs_misc_tbl = sc7280_qmp_pcie_pcs_misc_tbl, |
| 184 | .pcs_misc_tbl_num = ARRAY_SIZE(sc7280_qmp_pcie_pcs_misc_tbl), |
| 185 | .pcs_misc_tbl_sec = sc7280_qmp_gen3x2_pcie_misc_tbl, |
| 186 | .pcs_misc_tbl_num_sec = ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_misc_tbl), |
| 187 | }; |
| 188 | |
| 189 | /* Enable PIPE clock */ |
| 190 | int qcom_dw_pcie_enable_pipe_clock(void) |
| 191 | { |
| 192 | int ret; |
| 193 | |
| 194 | /* Set pipe clock source */ |
| 195 | ret = clock_configure_mux(GCC_PCIE_1_PIPE_MUXR, PCIE_1_PIPE_SRC_SEL); |
| 196 | if (ret) { |
| 197 | printk(BIOS_ERR, " %s(): Pipe clock enable failed\n", __func__); |
| 198 | return -1; |
| 199 | } |
| 200 | |
| 201 | /* Enable pipe clock */ |
| 202 | ret = clock_enable_pcie(PCIE_1_PIPE_CLK); |
| 203 | if (ret) { |
| 204 | printk(BIOS_ERR, "Failed to enable pipe clock\n"); |
| 205 | return -1; |
| 206 | } |
| 207 | |
| 208 | return ret; |
| 209 | } |
| 210 | |
| 211 | /* Enable controller specific clocks */ |
| 212 | int32_t qcom_dw_pcie_enable_clock(void) |
| 213 | { |
| 214 | int32_t ret, clk; |
| 215 | |
| 216 | /* Enable gdsc before enable pcie clocks */ |
| 217 | ret = clock_enable_gdsc(PCIE_1_GDSC); |
| 218 | if (ret) { |
| 219 | printk(BIOS_ERR, "Failed to enable gdsc\n"); |
| 220 | return ret; |
| 221 | } |
| 222 | |
| 223 | /* Enable pcie and PHY clocks */ |
| 224 | for (clk = PCIE_1_SLV_Q2A_AXI_CLK; clk < PCIE_CLK_COUNT - 3; clk++) { |
| 225 | ret = clock_enable_pcie(clk); |
| 226 | if (ret) { |
| 227 | printk(BIOS_ERR, "Failed to enable %d clock\n", clk); |
| 228 | return ret; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | return ret; |
| 233 | } |
| 234 | |
| 235 | /* Turn on NVMe */ |
| 236 | void gcom_pcie_power_on_ep(void) |
| 237 | { |
| 238 | gpio_output(NVME_REG_EN, 1); |
| 239 | } |
| 240 | |
| 241 | void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg) |
| 242 | { |
| 243 | host_cfg->cntlr_cfg = &pcie_host; |
| 244 | host_cfg->qmp_phy_cfg = &pcie1_qmp_phy_3x2; |
| 245 | } |