Michał Żygowski | e622587 | 2022-10-15 16:35:31 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <bootstate.h> |
Michał Żygowski | e622587 | 2022-10-15 16:35:31 +0200 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <cpu/cpu.h> |
| 6 | #include <device/mmio.h> |
| 7 | #include <device/pci_ops.h> |
| 8 | #include <fsp/util.h> |
| 9 | #include <intelblocks/systemagent.h> |
| 10 | #include <intelblocks/vtd.h> |
| 11 | #include <lib.h> |
| 12 | #include <soc/iomap.h> |
| 13 | #include <soc/pci_devs.h> |
| 14 | |
| 15 | /* VT-d specification: https://cdrdv2.intel.com/v1/dl/getContent/671081 */ |
| 16 | #define VER_REG 0x0 |
| 17 | #define CAP_REG 0x8 |
| 18 | #define CAP_PMR_LO BIT(5) |
| 19 | #define CAP_PMR_HI BIT(6) |
| 20 | #define PMEN_REG 0x64 |
| 21 | #define PMEN_EPM BIT(31) |
| 22 | #define PMEN_PRS BIT(0) |
| 23 | #define PLMBASE_REG 0x68 |
| 24 | #define PLMLIMIT_REG 0x6C |
| 25 | #define PHMBASE_REG 0x70 |
| 26 | #define PHMLIMIT_REG 0x78 |
| 27 | |
| 28 | /* FSP 2.x VT-d HOB from edk2-platforms */ |
| 29 | static const uint8_t vtd_pmr_info_data_hob_guid[16] = { |
| 30 | 0x45, 0x16, 0xb6, 0x6f, 0x68, 0xf1, 0xbe, 0x46, |
| 31 | 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 |
| 32 | }; |
| 33 | |
| 34 | struct vtd_pmr_info_hob { |
| 35 | uint32_t protected_low_base; |
| 36 | uint32_t protected_low_limit; |
| 37 | uint64_t protected_high_base; |
| 38 | uint64_t protected_high_limit; |
| 39 | } __packed; |
| 40 | |
| 41 | static struct vtd_pmr_info_hob *pmr_hob; |
| 42 | |
| 43 | static __always_inline uint32_t vtd_read32(uintptr_t vtd_base, uint32_t reg) |
| 44 | { |
| 45 | return read32p(vtd_base + reg); |
| 46 | } |
| 47 | |
| 48 | static __always_inline void vtd_write32(uintptr_t vtd_base, uint32_t reg, uint32_t value) |
| 49 | { |
| 50 | return write32p(vtd_base + reg, value); |
| 51 | } |
| 52 | |
| 53 | static __always_inline uint64_t vtd_read64(uintptr_t vtd_base, uint32_t reg) |
| 54 | { |
| 55 | return read64p(vtd_base + reg); |
| 56 | } |
| 57 | |
| 58 | static __always_inline void vtd_write64(uintptr_t vtd_base, uint32_t reg, uint64_t value) |
| 59 | { |
| 60 | return write64p(vtd_base + reg, value); |
| 61 | } |
| 62 | |
| 63 | static bool is_vtd_enabled(uintptr_t vtd_base) |
| 64 | { |
| 65 | uint32_t version = vtd_read32(vtd_base, VER_REG); |
| 66 | |
| 67 | if (version == 0 || version == UINT32_MAX) { |
| 68 | printk(BIOS_WARNING, "No VT-d @ 0x%08lx\n", vtd_base); |
| 69 | return false; |
| 70 | } |
| 71 | |
| 72 | printk(BIOS_DEBUG, "VT-d @ 0x%08lx, version %x.%x\n", |
| 73 | vtd_base, (version & 0xf0) >> 4, version & 0xf); |
| 74 | |
| 75 | return true; |
| 76 | } |
| 77 | |
| 78 | static uint32_t vtd_get_pmr_alignment_lo(uintptr_t vtd_base) |
| 79 | { |
| 80 | uint32_t value; |
| 81 | |
| 82 | vtd_write32(vtd_base, PLMLIMIT_REG, 0xffffffff); |
| 83 | value = vtd_read32(vtd_base, PLMLIMIT_REG); |
| 84 | value = ~value + 1; |
| 85 | |
| 86 | return value; |
| 87 | } |
| 88 | |
| 89 | static uint64_t vtd_get_pmr_alignment_hi(uintptr_t vtd_base) |
| 90 | { |
| 91 | uint64_t value; |
| 92 | |
| 93 | vtd_write64(vtd_base, PHMLIMIT_REG, 0xffffffffffffffffULL); |
| 94 | value = vtd_read64(vtd_base, PHMLIMIT_REG); |
| 95 | value = ~value + 1ULL; |
| 96 | value = value & ((1ULL << (uint32_t)cpu_phys_address_size()) - 1ULL); |
| 97 | |
| 98 | /* The host address width can be different than the sizing of the register. |
| 99 | * Simply find the least significant bit set and use it as alignment; |
| 100 | */ |
| 101 | return __ffs64(value); |
| 102 | } |
| 103 | |
| 104 | static void vtd_set_pmr_low(uintptr_t vtd_base) |
| 105 | { |
| 106 | uint32_t pmr_lo_align; |
| 107 | uint32_t pmr_lo_limit; |
| 108 | /* |
| 109 | * Typical PMR alignment is 1MB so we should be good but check just in |
| 110 | * case. |
| 111 | */ |
| 112 | pmr_lo_align = vtd_get_pmr_alignment_lo(vtd_base); |
| 113 | pmr_lo_limit = pmr_hob->protected_low_limit; |
| 114 | |
| 115 | if (!IS_ALIGNED(pmr_lo_limit, pmr_lo_align)) { |
| 116 | pmr_lo_limit = ALIGN_DOWN(pmr_lo_limit, pmr_lo_align); |
| 117 | printk(BIOS_WARNING, "PMR limit low not properly aligned, aligning down to %08x\n", |
| 118 | pmr_lo_limit); |
| 119 | } |
| 120 | |
| 121 | printk(BIOS_INFO, "Setting DMA protection [0x0 - 0x%08x]\n", pmr_lo_limit); |
| 122 | vtd_write32(vtd_base, PLMBASE_REG, 0); |
| 123 | vtd_write32(vtd_base, PLMLIMIT_REG, pmr_lo_limit - 1); |
| 124 | } |
| 125 | |
| 126 | static void vtd_set_pmr_high(uintptr_t vtd_base) |
| 127 | { |
| 128 | uint64_t pmr_hi_align; |
| 129 | uint64_t pmr_hi_limit; |
| 130 | /* |
| 131 | * Typical PMR alignment is 1MB so we should be good with above 4G |
| 132 | * memory but check just in case. |
| 133 | */ |
| 134 | pmr_hi_align = vtd_get_pmr_alignment_hi(vtd_base); |
| 135 | pmr_hi_limit = pmr_hob->protected_high_limit; |
| 136 | |
| 137 | /* No memory above 4G? Skip PMR high programming */ |
| 138 | if (pmr_hi_limit == 0 || pmr_hi_limit < 4ULL * GiB) |
| 139 | return; |
| 140 | |
| 141 | if (!IS_ALIGNED(pmr_hi_limit, pmr_hi_align)) { |
| 142 | pmr_hi_limit = ALIGN_DOWN(pmr_hi_limit, pmr_hi_align); |
| 143 | printk(BIOS_WARNING, "PMR High limit not properly aligned, " |
| 144 | "aligning down to %016llx\n", |
| 145 | pmr_hi_limit); |
| 146 | } |
| 147 | |
| 148 | printk(BIOS_INFO, "Setting DMA protection [0x100000000 - 0x%016llx]\n", pmr_hi_limit); |
| 149 | vtd_write64(vtd_base, PHMBASE_REG, 4ULL * GiB); |
| 150 | vtd_write64(vtd_base, PHMLIMIT_REG, pmr_hi_limit - 1ULL); |
| 151 | } |
| 152 | |
| 153 | static bool disable_pmr_protection(uintptr_t vtd_base) |
| 154 | { |
| 155 | if (vtd_read32(vtd_base, PMEN_REG) & PMEN_PRS) { |
| 156 | vtd_write32(vtd_base, PMEN_REG, vtd_read32(vtd_base, PMEN_REG) & ~PMEN_EPM); |
| 157 | if (vtd_read32(vtd_base, PMEN_REG) & PMEN_PRS) { |
| 158 | printk(BIOS_ERR, "Failed to disable existing DMA protection\n"); |
| 159 | return false; |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | return true; |
| 164 | } |
| 165 | |
| 166 | static bool enable_pmr_protection(uintptr_t vtd_base) |
| 167 | { |
| 168 | vtd_write32(vtd_base, PMEN_REG, vtd_read32(vtd_base, PMEN_REG) | PMEN_EPM); |
| 169 | if (vtd_read32(vtd_base, PMEN_REG) & PMEN_PRS) |
| 170 | return true; |
| 171 | |
| 172 | return false; |
| 173 | } |
| 174 | |
| 175 | static const void *locate_pmr_info_hob(void) |
| 176 | { |
| 177 | size_t size; |
| 178 | const void *hob; |
| 179 | |
| 180 | if (pmr_hob) |
| 181 | return (void *)pmr_hob; |
| 182 | |
| 183 | hob = fsp_find_extension_hob_by_guid(vtd_pmr_info_data_hob_guid, &size); |
| 184 | |
| 185 | if (hob) { |
| 186 | pmr_hob = (struct vtd_pmr_info_hob *)hob; |
| 187 | printk(BIOS_SPEW, "PMR info HOB:\n" |
| 188 | " protected_low_base: %08x\n" |
| 189 | " protected_low_limit: %08x\n" |
| 190 | " protected_high_base: %016llx\n" |
| 191 | " protected_high_limit: %016llx\n", |
| 192 | pmr_hob->protected_low_base, pmr_hob->protected_low_limit, |
| 193 | pmr_hob->protected_high_base, pmr_hob->protected_high_limit); |
| 194 | } |
| 195 | |
| 196 | return hob; |
| 197 | } |
| 198 | |
| 199 | static void vtd_engine_enable_dma_protection(uintptr_t vtd_base) |
| 200 | { |
| 201 | if (!is_vtd_enabled(vtd_base)) { |
| 202 | printk(BIOS_ERR, "Not enabling DMA protection, VT-d not found\n"); |
| 203 | return; |
| 204 | } |
| 205 | |
| 206 | /* At minimum PMR Low must be supported, coreboot executes in 32bit space (for now) */ |
| 207 | if (!(vtd_read32(vtd_base, CAP_REG) & CAP_PMR_LO)) { |
| 208 | printk(BIOS_ERR, "Not enabling DMA protection, PMR registers not supported\n"); |
| 209 | return; |
| 210 | } |
| 211 | |
| 212 | if (!locate_pmr_info_hob()) { |
| 213 | printk(BIOS_ERR, "VT-d PMR HOB not found, not enabling DMA protection\n"); |
| 214 | return; |
| 215 | } |
| 216 | |
| 217 | /* If protection is enabled, disable it first */ |
| 218 | if (!disable_pmr_protection(vtd_base)) { |
| 219 | printk(BIOS_ERR, "Not setting DMA protection\n"); |
| 220 | return; |
| 221 | } |
| 222 | |
| 223 | vtd_set_pmr_low(vtd_base); |
| 224 | |
| 225 | if (vtd_read32(vtd_base, CAP_REG) & CAP_PMR_HI) |
| 226 | vtd_set_pmr_high(vtd_base); |
| 227 | |
| 228 | if (enable_pmr_protection(vtd_base)) |
| 229 | printk(BIOS_INFO, "Successfully enabled VT-d PMR DMA protection\n"); |
| 230 | else |
| 231 | printk(BIOS_ERR, "Enabling VT-d PMR DMA protection failed\n"); |
| 232 | } |
| 233 | |
| 234 | static const struct hob_resource *find_resource_hob_by_addr(const uint64_t addr) |
| 235 | { |
| 236 | const struct hob_header *hob_iterator; |
| 237 | const struct hob_resource *res; |
| 238 | |
| 239 | if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) { |
| 240 | printk(BIOS_ERR, "Failed to find HOB list\n"); |
| 241 | return NULL; |
| 242 | } |
| 243 | |
| 244 | while (fsp_hob_iterator_get_next_resource(&hob_iterator, &res) == CB_SUCCESS) { |
| 245 | if ((res->type == EFI_RESOURCE_MEMORY_RESERVED) && (res->addr == addr)) |
| 246 | return res; |
| 247 | } |
| 248 | |
| 249 | return NULL; |
| 250 | } |
| 251 | |
| 252 | void *vtd_get_dma_buffer(size_t *size) |
| 253 | { |
| 254 | const struct hob_resource *res; |
| 255 | |
| 256 | if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) |
| 257 | goto no_dma_buffer; |
| 258 | |
| 259 | if (!locate_pmr_info_hob()) { |
| 260 | printk(BIOS_ERR, "FSP PMR info HOB not found\n"); |
| 261 | goto no_dma_buffer; |
| 262 | } |
| 263 | |
| 264 | /* PMR low limit will be the DMA buffer base reserved by FSP */ |
| 265 | res = find_resource_hob_by_addr((uint64_t)pmr_hob->protected_low_limit); |
| 266 | if (!res) { |
| 267 | printk(BIOS_ERR, "FSP PMR resource HOB not found\n"); |
| 268 | goto no_dma_buffer; |
| 269 | } |
| 270 | |
| 271 | if (size) |
| 272 | *size = res->length; |
| 273 | |
| 274 | return (void *)(uintptr_t)res->addr; |
| 275 | |
| 276 | no_dma_buffer: |
| 277 | if (size) |
| 278 | *size = 0; |
| 279 | return NULL; |
| 280 | } |
| 281 | |
| 282 | void vtd_enable_dma_protection(void) |
| 283 | { |
| 284 | if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) |
| 285 | return; |
| 286 | |
| 287 | vtd_engine_enable_dma_protection(VTVC0_BASE_ADDRESS); |
| 288 | /* |
| 289 | * FIXME: GFX VT-d will fail to set PMR (tested on ADL-S). |
| 290 | * Should we program PMRs on all VT-d engines? |
| 291 | * vtd_engine_enable_dma_protection(GFXVT_BASE_ADDRESS); |
| 292 | * vtd_engine_enable_dma_protection(IPUVT_BASE_ADDRESS); |
| 293 | */ |
| 294 | } |
| 295 | |
| 296 | static void vtd_disable_pmr_on_resume(void *unused) |
| 297 | { |
| 298 | /* At minimum PMR Low must be supported */ |
| 299 | if (!(vtd_read32(VTVC0_BASE_ADDRESS, CAP_REG) & CAP_PMR_LO)) |
| 300 | return; |
| 301 | |
| 302 | if (disable_pmr_protection(VTVC0_BASE_ADDRESS)) { |
| 303 | vtd_write32(VTVC0_BASE_ADDRESS, PLMBASE_REG, 0); |
| 304 | vtd_write32(VTVC0_BASE_ADDRESS, PLMLIMIT_REG, 0); |
| 305 | if (vtd_read32(VTVC0_BASE_ADDRESS, CAP_REG) & CAP_PMR_HI) { |
| 306 | vtd_write64(VTVC0_BASE_ADDRESS, PHMBASE_REG, 0); |
| 307 | vtd_write64(VTVC0_BASE_ADDRESS, PHMLIMIT_REG, 0); |
| 308 | } |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, vtd_disable_pmr_on_resume, NULL); |