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Yidi Lin3d7b6062015-07-31 17:10:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2015 MediaTek Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Yidi Lin3d7b6062015-07-31 17:10:40 +080014 */
15
16#include <arch/cache.h>
17#include <arch/io.h>
18#include <boardid.h>
19#include <boot/coreboot_tables.h>
Koro Chen9733ba52015-07-31 17:11:04 +080020#include <delay.h>
Yidi Lin3d7b6062015-07-31 17:10:40 +080021#include <device/device.h>
22
Koro Chen9733ba52015-07-31 17:11:04 +080023#include <gpio.h>
24#include <soc/mt6391.h>
25#include <soc/mtcmos.h>
26#include <soc/pinmux.h>
27#include <soc/pll.h>
28
29static void configure_audio(void)
30{
31 mtcmos_audio_power_on();
32
33 /* regulator for codecs */
34 switch (board_id()) {
35 case 0:
36 /* vgp1 set to 1.22V */
37 mt6391_configure_ldo(LDO_VCAMD, LDO_1P22);
38 /* vgp4 set to 1.8V */
39 mt6391_configure_ldo(LDO_VGP4, LDO_1P8);
40 break;
41 default:
42 /* board from Rev1 */
43 /* vgp1 set to 1.8V */
44 mt6391_configure_ldo(LDO_VCAMD, LDO_1P8);
45 /* delay 1ms for realtek's power sequence request */
46 mdelay(1);
47 /* vcama set to 1.8V */
48 mt6391_configure_ldo(LDO_VCAMA, LDO_1P8);
49 break;
50 }
51
52 /* reset ALC5676 */
53 gpio_output(PAD_LCM_RST, 1);
54
55 /* SoC I2S */
56 gpio_set_mode(PAD_I2S0_LRCK, PAD_I2S0_LRCK_FUNC_I2S1_WS);
57 gpio_set_mode(PAD_I2S0_BCK, PAD_I2S0_BCK_FUNC_I2S1_BCK);
58 gpio_set_mode(PAD_I2S0_MCK, PAD_I2S0_MCK_FUNC_I2S1_MCK);
59 gpio_set_mode(PAD_I2S0_DATA0, PAD_I2S0_DATA0_FUNC_I2S1_DO_1);
60 gpio_set_mode(PAD_I2S0_DATA1, PAD_I2S0_DATA1_FUNC_I2S2_DI_2);
61
62 /* codec ext MCLK ON */
63 mt6391_gpio_output(MT6391_KP_COL4, 1);
64 mt6391_gpio_output(MT6391_KP_COL5, 1);
65
66 /* set I2S clock to 48KHz */
67 mt_pll_set_aud_div(48 * KHz);
68}
69
Yidi Lin3d7b6062015-07-31 17:10:40 +080070static void mainboard_init(device_t dev)
71{
Koro Chen9733ba52015-07-31 17:11:04 +080072 configure_audio();
Yidi Lin3d7b6062015-07-31 17:10:40 +080073}
74
75static void mainboard_enable(device_t dev)
76{
77 dev->ops->init = &mainboard_init;
78}
79
80struct chip_operations mainboard_ops = {
81 .name = "oak",
82 .enable_dev = mainboard_enable,
83};