Angel Pons | 2e8a4b0 | 2020-04-05 13:22:54 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 5 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 6 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 7 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 8 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 9 | #include <southbridge/intel/common/gpio.h> |
Kyösti Mälkki | 926a8d1 | 2014-04-27 22:17:22 +0300 | [diff] [blame] | 10 | #include <bootmode.h> |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 11 | #include <ec/quanta/it8518/ec.h> |
| 12 | #include "ec.h" |
| 13 | #include "onboard.h" |
| 14 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 15 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 16 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 17 | /* |
| 18 | * GFX INTA -> PIRQA (MSI) |
| 19 | * D20IP_XHCI XHCI INTA -> PIRQD (MSI) |
| 20 | * D26IP_E2P EHCI #2 INTA -> PIRQF |
| 21 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 22 | * D28IP_P2IP WLAN INTA -> PIRQD |
| 23 | * D28IP_P3IP Card Reader INTB -> PIRQE |
| 24 | * D28IP_P6IP LAN INTC -> PIRQB |
| 25 | * D29IP_E1P EHCI #1 INTA -> PIRQD |
| 26 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 27 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 28 | */ |
| 29 | |
| 30 | /* Device interrupt pin register (board specific) */ |
| 31 | RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 32 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 33 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 34 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 35 | RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | |
| 36 | (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | |
| 37 | (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | |
| 38 | (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); |
| 39 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 40 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 41 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 42 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 43 | RCBA32(D20IP) = (INTA << D20IP_XHCIIP); |
| 44 | |
| 45 | /* Device interrupt route registers */ |
| 46 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 47 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 48 | DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); |
| 49 | DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 50 | DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); |
| 51 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 52 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 53 | DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 54 | } |
| 55 | |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 56 | /* |
| 57 | * The Stout EC needs to be reset to RW mode. It is important that |
| 58 | * the RTC_PWR_STS is not set until ramstage EC init. |
| 59 | */ |
| 60 | static void early_ec_init(void) |
| 61 | { |
| 62 | u8 ec_status = ec_read(EC_STATUS_REG); |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 63 | int rec_mode = get_recovery_mode_switch(); |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 64 | |
| 65 | if (((ec_status & 0x3) == EC_IN_RO_MODE) || |
| 66 | ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) { |
| 67 | |
| 68 | printk(BIOS_DEBUG, "EC Cold Boot Detected\n"); |
| 69 | if (!rec_mode) { |
| 70 | /* |
| 71 | * Tell EC to exit RO mode |
| 72 | */ |
| 73 | printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); |
| 74 | ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); |
| 75 | die("wait for ec to reset"); |
| 76 | } |
| 77 | } else { |
| 78 | printk(BIOS_DEBUG, "EC Warm Boot Detected\n"); |
| 79 | ec_write_cmd(EC_CMD_WARM_RESET); |
| 80 | } |
| 81 | } |
| 82 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 83 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 84 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 85 | read_spd(&spd[0], 0x50, id_only); |
| 86 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 87 | } |
| 88 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 89 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 90 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 91 | struct pei_data pei_data_template = { |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 92 | .pei_version = PEI_VERSION, |
Angel Pons | d9e58dc | 2021-01-20 01:22:20 +0100 | [diff] [blame] | 93 | .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, |
| 94 | .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, |
| 95 | .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 96 | .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 97 | .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 98 | .wdbbar = 0x4000000, |
| 99 | .wdbsize = 0x1000, |
| 100 | .hpet_address = CONFIG_HPET_ADDRESS, |
Angel Pons | 92717ff | 2020-09-14 16:22:22 +0200 | [diff] [blame] | 101 | .rcba = (uintptr_t)DEFAULT_RCBA, |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 102 | .pmbase = DEFAULT_PMBASE, |
| 103 | .gpiobase = DEFAULT_GPIOBASE, |
| 104 | .thermalbase = 0xfed08000, |
| 105 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 106 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 107 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 108 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 109 | .ec_present = 1, |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 110 | .max_ddr3_freq = 1600, |
| 111 | .usb_port_config = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 112 | /* enabled USB oc pin length */ |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 113 | { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ |
| 114 | { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ |
| 115 | { 0, 1, 0x0000 }, /* P2: Empty */ |
| 116 | { 1, 1, 0x0040 }, /* P3: Camera (no OC) */ |
| 117 | { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */ |
| 118 | { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */ |
| 119 | { 0, 1, 0x0000 }, /* P6: Empty */ |
| 120 | { 0, 1, 0x0000 }, /* P7: Empty */ |
| 121 | { 0, 5, 0x0000 }, /* P8: Empty */ |
| 122 | { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */ |
| 123 | { 0, 5, 0x0000 }, /* P10: Empty */ |
| 124 | { 0, 5, 0x0000 }, /* P11: Empty */ |
| 125 | { 0, 5, 0x0000 }, /* P12: Empty */ |
| 126 | { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ |
| 127 | }, |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 128 | .usb3 = { |
| 129 | .mode = XHCI_MODE, |
| 130 | .hs_port_switch_mask = XHCI_PORTS, |
| 131 | .preboot_support = XHCI_PREBOOT, |
| 132 | .xhci_streams = XHCI_STREAMS, |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 133 | }, |
| 134 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 135 | *pei_data = pei_data_template; |
| 136 | } |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 137 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 138 | void mainboard_early_init(int s3resume) |
| 139 | { |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 140 | /* Do ec reset as early as possible, but skip it on S3 resume */ |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 141 | if (!s3resume) { |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 142 | early_ec_init(); |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 143 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 144 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 145 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 146 | int mainboard_should_reset_usb(int s3resume) |
| 147 | { |
| 148 | return !s3resume; |
| 149 | } |
| 150 | |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 151 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 152 | /* enabled USB oc pin length */ |
Elyes HAOUAS | 48a0129 | 2016-09-29 18:57:56 +0200 | [diff] [blame] | 153 | {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ |
| 154 | {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ |
| 155 | {0, 0, 0}, /* P2: Empty */ |
| 156 | {1, 0, -1}, /* P3: Camera (no OC) */ |
| 157 | {1, 0, -1}, /* P4: WLAN (no OC) */ |
| 158 | {1, 0, -1}, /* P5: WWAN (no OC) */ |
| 159 | {0, 0, 0}, /* P6: Empty */ |
| 160 | {0, 0, 0}, /* P7: Empty */ |
| 161 | {0, 0, 0}, /* P8: Empty */ |
| 162 | {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ |
| 163 | {0, 0, 0}, /* P10: Empty */ |
| 164 | {0, 0, 0}, /* P11: Empty */ |
| 165 | {0, 0, 0}, /* P12: Empty */ |
| 166 | {1, 0, -1}, /* P13: Bluetooth (no OC) */ |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 167 | }; |