arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## Compute the location and size of where this firmware image |
| 3 | ## (linuxBIOS plus bootloader) will live in the boot rom chip. |
| 4 | ## |
| 5 | if USE_FALLBACK_IMAGE |
| 6 | default ROM_SECTION_SIZE = FALLBACK_SIZE |
| 7 | default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) |
| 8 | else |
| 9 | default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) |
| 10 | default ROM_SECTION_OFFSET = 0 |
| 11 | end |
| 12 | |
| 13 | ## |
| 14 | ## Compute the start location and size size of |
| 15 | ## The linuxBIOS bootloader. |
| 16 | ## |
| 17 | default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) |
| 18 | default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) |
| 19 | default CONFIG_ROM_STREAM = 1 |
| 20 | |
| 21 | ## |
| 22 | ## Compute where this copy of linuxBIOS will start in the boot rom |
| 23 | ## |
| 24 | default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) |
| 25 | |
| 26 | ## |
| 27 | ## Compute a range of ROM that can cached to speed up linuxBIOS, |
| 28 | ## execution speed. |
| 29 | ## |
| 30 | ## XIP_ROM_SIZE must be a power of 2. |
| 31 | ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE |
| 32 | ## |
| 33 | default XIP_ROM_SIZE=65536 |
| 34 | default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) |
| 35 | |
| 36 | arch i386 end |
| 37 | |
| 38 | |
| 39 | ## |
| 40 | ## Build the objects we have code for in this directory. |
| 41 | ## |
| 42 | |
| 43 | driver mainboard.o |
| 44 | |
| 45 | #dir /drivers/ati/ragexl |
Yinghai Lu | 968bbe8 | 2005-12-06 23:34:09 +0000 | [diff] [blame^] | 46 | #needed by irq_tables and mptable and acpi_tables |
| 47 | object get_bus_conf.o |
| 48 | |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 49 | |
| 50 | if HAVE_MP_TABLE object mptable.o end |
| 51 | if HAVE_PIRQ_TABLE object irq_tables.o end |
| 52 | #object reset.o |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 53 | |
| 54 | if USE_DCACHE_RAM |
| 55 | |
| 56 | if CONFIG_USE_INIT |
| 57 | |
| 58 | makerule ./auto.o |
| 59 | depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 60 | action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" |
| 61 | end |
| 62 | |
| 63 | else |
| 64 | |
| 65 | makerule ./auto.inc |
| 66 | depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| 67 | action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" |
| 68 | action "perl -e 's/.rodata/.rom.data/g' -pi $@" |
| 69 | action "perl -e 's/.text/.section .rom.text/g' -pi $@" |
| 70 | end |
| 71 | |
| 72 | end |
| 73 | else |
| 74 | |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 75 | ## |
| 76 | ## Romcc output |
| 77 | ## |
| 78 | makerule ./failover.E |
| 79 | depends "$(MAINBOARD)/failover.c ./romcc" |
| 80 | action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" |
| 81 | end |
| 82 | |
| 83 | makerule ./failover.inc |
| 84 | depends "$(MAINBOARD)/failover.c ./romcc" |
| 85 | action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" |
| 86 | end |
| 87 | |
| 88 | makerule ./auto.E |
| 89 | depends "$(MAINBOARD)/auto.c option_table.h ./romcc" |
| 90 | action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" |
| 91 | end |
| 92 | makerule ./auto.inc |
| 93 | depends "$(MAINBOARD)/auto.c option_table.h ./romcc" |
| 94 | action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" |
| 95 | end |
| 96 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 97 | |
| 98 | end |
| 99 | |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 100 | ## |
| 101 | ## Build our 16 bit and 32 bit linuxBIOS entry code |
| 102 | ## |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 103 | if USE_FALLBACK_IMAGE |
| 104 | mainboardinit cpu/x86/16bit/entry16.inc |
| 105 | ldscript /cpu/x86/16bit/entry16.lds |
| 106 | end |
| 107 | |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 108 | mainboardinit cpu/x86/32bit/entry32.inc |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 109 | |
| 110 | if USE_DCACHE_RAM |
| 111 | if CONFIG_USE_INIT |
| 112 | ldscript /cpu/x86/32bit/entry32.lds |
| 113 | end |
| 114 | |
| 115 | if CONFIG_USE_INIT |
| 116 | ldscript /cpu/amd/car/cache_as_ram.lds |
| 117 | end |
| 118 | end |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 119 | |
| 120 | ## |
| 121 | ## Build our reset vector (This is where linuxBIOS is entered) |
| 122 | ## |
| 123 | if USE_FALLBACK_IMAGE |
| 124 | mainboardinit cpu/x86/16bit/reset16.inc |
| 125 | ldscript /cpu/x86/16bit/reset16.lds |
| 126 | else |
| 127 | mainboardinit cpu/x86/32bit/reset32.inc |
| 128 | ldscript /cpu/x86/32bit/reset32.lds |
| 129 | end |
| 130 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 131 | if USE_DCACHE_RAM |
| 132 | else |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 133 | ### Should this be in the northbridge code? |
| 134 | mainboardinit arch/i386/lib/cpu_reset.inc |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 135 | end |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 136 | |
| 137 | ## |
| 138 | ## Include an id string (For safe flashing) |
| 139 | ## |
| 140 | mainboardinit southbridge/nvidia/ck804/id.inc |
| 141 | ldscript /southbridge/nvidia/ck804/id.lds |
| 142 | |
| 143 | ## |
| 144 | ## ROMSTRAP table for CK804 |
| 145 | ## |
| 146 | if USE_FALLBACK_IMAGE |
| 147 | mainboardinit southbridge/nvidia/ck804/romstrap.inc |
| 148 | ldscript /southbridge/nvidia/ck804/romstrap.lds |
| 149 | end |
| 150 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 151 | if USE_DCACHE_RAM |
| 152 | ## |
| 153 | ## Setup Cache-As-Ram |
| 154 | ## |
| 155 | mainboardinit cpu/amd/car/cache_as_ram.inc |
| 156 | end |
| 157 | |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 158 | ### |
| 159 | ### This is the early phase of linuxBIOS startup |
| 160 | ### Things are delicate and we test to see if we should |
| 161 | ### failover to another image. |
| 162 | ### |
| 163 | if USE_FALLBACK_IMAGE |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 164 | if USE_DCACHE_RAM |
| 165 | ldscript /arch/i386/lib/failover.lds |
| 166 | else |
| 167 | ldscript /arch/i386/lib/failover.lds |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 168 | mainboardinit ./failover.inc |
| 169 | end |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 170 | end |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 171 | |
| 172 | ### |
| 173 | ### O.k. We aren't just an intermediary anymore! |
| 174 | ### |
| 175 | |
| 176 | ## |
| 177 | ## Setup RAM |
| 178 | ## |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 179 | if USE_DCACHE_RAM |
| 180 | |
| 181 | if CONFIG_USE_INIT |
| 182 | initobject auto.o |
| 183 | else |
| 184 | mainboardinit ./auto.inc |
| 185 | end |
| 186 | |
| 187 | else |
| 188 | # ROMCC |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 189 | mainboardinit cpu/x86/fpu/enable_fpu.inc |
| 190 | mainboardinit cpu/x86/mmx/enable_mmx.inc |
| 191 | mainboardinit cpu/x86/sse/enable_sse.inc |
| 192 | mainboardinit ./auto.inc |
| 193 | mainboardinit cpu/x86/sse/disable_sse.inc |
| 194 | mainboardinit cpu/x86/mmx/disable_mmx.inc |
| 195 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 196 | end |
| 197 | |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 198 | ## |
| 199 | ## Include the secondary Configuration files |
| 200 | ## |
| 201 | if CONFIG_CHIP_NAME |
| 202 | config chip.h |
| 203 | end |
| 204 | |
| 205 | |
| 206 | # sample config for tyan/s2892 |
| 207 | chip northbridge/amd/amdk8/root_complex |
| 208 | device apic_cluster 0 on |
| 209 | chip cpu/amd/socket_940 |
| 210 | device apic 0 on end |
| 211 | end |
| 212 | end |
| 213 | |
| 214 | device pci_domain 0 on |
| 215 | chip northbridge/amd/amdk8 #mc0 |
| 216 | device pci 18.0 on # northbridge |
| 217 | # devices on link 0, link 0 == LDT 0 |
| 218 | chip southbridge/nvidia/ck804 |
| 219 | device pci 0.0 on end # HT |
| 220 | device pci 1.0 on # LPC |
| 221 | chip superio/winbond/w83627hf |
| 222 | device pnp 2e.0 on # Floppy |
| 223 | io 0x60 = 0x3f0 |
| 224 | irq 0x70 = 6 |
| 225 | drq 0x74 = 2 |
| 226 | end |
| 227 | device pnp 2e.1 off # Parallel Port |
| 228 | io 0x60 = 0x378 |
| 229 | irq 0x70 = 7 |
| 230 | end |
| 231 | device pnp 2e.2 on # Com1 |
| 232 | io 0x60 = 0x3f8 |
| 233 | irq 0x70 = 4 |
| 234 | end |
| 235 | device pnp 2e.3 off # Com2 |
| 236 | io 0x60 = 0x2f8 |
| 237 | irq 0x70 = 3 |
| 238 | end |
| 239 | device pnp 2e.5 on # Keyboard |
| 240 | io 0x60 = 0x60 |
| 241 | io 0x62 = 0x64 |
| 242 | irq 0x70 = 1 |
| 243 | irq 0x72 = 12 |
| 244 | end |
| 245 | device pnp 2e.6 off # CIR |
| 246 | io 0x60 = 0x100 |
| 247 | end |
| 248 | device pnp 2e.7 off # GAME_MIDI_GIPO1 |
| 249 | io 0x60 = 0x220 |
| 250 | io 0x62 = 0x300 |
| 251 | irq 0x70 = 9 |
| 252 | end |
| 253 | device pnp 2e.8 off end # GPIO2 |
| 254 | device pnp 2e.9 off end # GPIO3 |
| 255 | device pnp 2e.a off end # ACPI |
| 256 | device pnp 2e.b on # HW Monitor |
| 257 | io 0x60 = 0x290 |
| 258 | irq 0x70 = 5 |
| 259 | end |
| 260 | end |
| 261 | end |
| 262 | device pci 1.1 on # SM 0 |
| 263 | chip drivers/generic/generic #dimm 0-0-0 |
| 264 | device i2c 50 on end |
| 265 | end |
| 266 | chip drivers/generic/generic #dimm 0-0-1 |
| 267 | device i2c 51 on end |
| 268 | end |
| 269 | chip drivers/generic/generic #dimm 0-1-0 |
| 270 | device i2c 52 on end |
| 271 | end |
| 272 | chip drivers/generic/generic #dimm 0-1-1 |
| 273 | device i2c 53 on end |
| 274 | end |
| 275 | chip drivers/generic/generic #dimm 1-0-0 |
| 276 | device i2c 54 on end |
| 277 | end |
| 278 | chip drivers/generic/generic #dimm 1-0-1 |
| 279 | device i2c 55 on end |
| 280 | end |
| 281 | chip drivers/generic/generic #dimm 1-1-0 |
| 282 | device i2c 56 on end |
| 283 | end |
| 284 | chip drivers/generic/generic #dimm 1-1-1 |
| 285 | device i2c 57 on end |
| 286 | end |
| 287 | end # SM |
| 288 | device pci 1.1 on # SM 1 |
| 289 | chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 |
| 290 | device i2c 2d on end |
| 291 | end |
| 292 | chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 |
| 293 | device i2c 2e on end |
| 294 | end |
| 295 | chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN |
| 296 | device i2c 2a on end |
| 297 | end |
| 298 | chip drivers/generic/generic # Winbond HWM 0x92 |
| 299 | device i2c 49 on end |
| 300 | end |
| 301 | chip drivers/generic/generic # Winbond HWM 0x94 |
| 302 | device i2c 4a on end |
| 303 | end |
| 304 | end #SM |
| 305 | device pci 2.0 on end # USB 1.1 |
| 306 | device pci 2.1 on end # USB 2 |
| 307 | device pci 4.0 off end # ACI |
| 308 | device pci 4.1 off end # MCI |
| 309 | device pci 6.0 on end # IDE |
| 310 | device pci 7.0 on end # SATA 1 |
| 311 | device pci 8.0 on end # SATA 0 |
| 312 | device pci 9.0 on # PCI |
| 313 | # chip drivers/ati/ragexl |
| 314 | chip drivers/pci/onboard |
| 315 | device pci 6.0 on end |
| 316 | register "rom_address" = "0xfff80000" |
| 317 | end |
| 318 | chip drivers/pci/onboard |
| 319 | device pci 8.0 on end |
| 320 | end |
| 321 | end |
| 322 | device pci a.0 off end # NIC |
| 323 | device pci b.0 off end # PCI E 3 |
| 324 | device pci c.0 off end # PCI E 2 |
| 325 | device pci d.0 on end # PCI E 1 |
| 326 | device pci e.0 on end # PCI E 0 |
| 327 | register "ide0_enable" = "1" |
| 328 | register "ide1_enable" = "1" |
| 329 | register "sata0_enable" = "1" |
| 330 | register "sata1_enable" = "1" |
| 331 | end |
| 332 | end # device pci 18.0 |
| 333 | device pci 18.0 on end # Link 1 |
| 334 | device pci 18.0 on |
| 335 | # devices on link 2, link 2 == LDT 2 |
| 336 | chip southbridge/amd/amd8131 |
| 337 | # the on/off keyword is mandatory |
| 338 | device pci 0.0 on end |
| 339 | device pci 0.1 on end |
| 340 | device pci 1.0 on |
| 341 | chip drivers/pci/onboard |
| 342 | device pci 9.0 on end # broadcom 5704 |
| 343 | device pci 9.1 on end |
| 344 | end |
| 345 | end |
| 346 | device pci 1.1 on end |
| 347 | end |
| 348 | end # device pci 18.0 |
| 349 | device pci 18.1 on end |
| 350 | device pci 18.2 on end |
| 351 | device pci 18.3 on end |
| 352 | end #mc0 |
| 353 | |
| 354 | end # pci_domain |
| 355 | |
| 356 | # chip drivers/generic/debug |
| 357 | # device pnp 0.0 off end |
| 358 | # device pnp 0.1 off end |
| 359 | # device pnp 0.2 off end |
| 360 | # device pnp 0.3 off end |
| 361 | # device pnp 0.4 off end |
| 362 | # device pnp 0.5 on end |
| 363 | # end |
| 364 | end # root_complex |