Aaron Durbin | 2c29d34 | 2016-07-21 17:58:16 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <soc/pci_devs.h> |
| 22 | #include <soc/pci_ids.h> |
| 23 | #include <timer.h> |
| 24 | |
| 25 | #define DUAL_ROLE_CFG0 0x80d8 |
| 26 | # define DRD_CONFIG_MASK (0x3 << 0) |
| 27 | # define DRD_CONFIG_DYNAMIC (0x0 << 0) |
| 28 | # define DRD_CONFIG_HOST (0x1 << 0) |
| 29 | # define DRD_CONFIG_DEVICE (0x2 << 0) |
| 30 | # define SW_VBUS_VALID_MASK (1 << 24) |
| 31 | # define SW_VBUS_DEASSERT_VALID (0 << 24) |
| 32 | # define SW_VBUS_ASSERT_VALID (1 << 24) |
| 33 | # define SW_IDPIN_EN_MASK (1 << 21) |
| 34 | # define SW_IDPIN_DIS (0 << 21) |
| 35 | # define SW_IDPIN_EN (1 << 21) |
| 36 | # define SW_IDPIN_MASK (1 << 20) |
| 37 | # define SW_IDPIN_HOST (0 << 20) |
| 38 | # define SW_IDPIN_DEVICE (1 << 20) |
| 39 | #define DUAL_ROLE_CFG1 0x80dc |
| 40 | # define DRD_MODE_MASK (1 << 29) |
| 41 | # define DRD_MODE_DEVICE (0 << 29) |
| 42 | # define DRD_MODE_HOST (1 << 29) |
| 43 | |
| 44 | static void configure_host_mode_port0(struct device *dev) |
| 45 | { |
| 46 | uint32_t *cfg0; |
| 47 | uint32_t *cfg1; |
| 48 | const struct resource *res; |
| 49 | uint32_t reg; |
| 50 | struct device *xdci_dev = XDCI_DEV; |
| 51 | struct stopwatch sw; |
| 52 | |
| 53 | /* |
| 54 | * Only default to host mode if the xdci device is present and |
| 55 | * enabled. If it's disabled assume the switch was already done |
| 56 | * in FSP. |
| 57 | */ |
| 58 | if (xdci_dev == NULL || !xdci_dev->enabled) |
| 59 | return; |
| 60 | |
| 61 | printk(BIOS_INFO, "Putting port 0 into host mode.\n"); |
| 62 | |
| 63 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 64 | |
| 65 | cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); |
| 66 | cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); |
| 67 | |
| 68 | reg = read32(cfg0); |
| 69 | reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); |
| 70 | reg &= ~(SW_VBUS_VALID_MASK); |
| 71 | reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; |
| 72 | reg |= SW_VBUS_DEASSERT_VALID; |
| 73 | write32(cfg0, reg); |
| 74 | |
| 75 | stopwatch_init_msecs_expire(&sw, 10); |
| 76 | |
| 77 | /* Wait for the host mode status bit. */ |
| 78 | while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { |
| 79 | if (stopwatch_expired(&sw)) { |
| 80 | printk(BIOS_INFO, "Timed out waiting for host mode.\n"); |
| 81 | break; |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", |
| 86 | stopwatch_duration_msecs(&sw)); |
| 87 | } |
| 88 | |
| 89 | static void xhci_init(struct device *dev) |
| 90 | { |
| 91 | configure_host_mode_port0(dev); |
| 92 | } |
| 93 | |
| 94 | static const struct device_operations device_ops = { |
| 95 | .read_resources = pci_dev_read_resources, |
| 96 | .set_resources = pci_dev_set_resources, |
| 97 | .enable_resources = pci_dev_enable_resources, |
| 98 | .init = xhci_init, |
| 99 | }; |
| 100 | |
| 101 | static const struct pci_driver pmc __pci_driver = { |
| 102 | .ops = &device_ops, |
| 103 | .vendor = PCI_VENDOR_ID_INTEL, |
| 104 | .device = PCI_DEVICE_ID_APOLLOLAKE_XHCI, |
| 105 | }; |