Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/uart.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <soc/gpio.h> |
| 21 | #include <soc/uart.h> |
| 22 | #include <soc/pci_devs.h> |
| 23 | |
| 24 | static void lpss_uart_write(uint16_t reg, uint32_t val) |
| 25 | { |
| 26 | uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg; |
| 27 | write32((void *)base, val); |
| 28 | } |
| 29 | |
Aaron Durbin | a513519 | 2016-02-24 19:00:03 -0600 | [diff] [blame] | 30 | static inline int invalid_uart_for_console(void) |
| 31 | { |
| 32 | /* There are actually only 2 UARTS, and they are named UART1 and |
| 33 | * UART2. They live at pci functions 1 and 2 respectively. */ |
| 34 | if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1) |
| 35 | return 1; |
| 36 | return 0; |
| 37 | } |
| 38 | |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 39 | void lpss_console_uart_init(void) |
| 40 | { |
| 41 | uint32_t clk_sel; |
| 42 | device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); |
| 43 | |
Aaron Durbin | a513519 | 2016-02-24 19:00:03 -0600 | [diff] [blame] | 44 | if (invalid_uart_for_console()) |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 45 | return; |
| 46 | |
| 47 | /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ |
| 48 | pci_write_config32(uart, PCI_BASE_ADDRESS_0, |
| 49 | CONFIG_CONSOLE_UART_BASE_ADDRESS); |
| 50 | |
| 51 | /* Enable memory access and bus master */ |
| 52 | pci_write_config32(uart, PCI_COMMAND, |
| 53 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 54 | |
Martin Roth | 433e8d2 | 2016-04-14 16:41:11 -0600 | [diff] [blame] | 55 | /* Take UART out of reset */ |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 56 | lpss_uart_write(UART_RESET, UART_RESET_UART_EN); |
| 57 | |
| 58 | /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */ |
| 59 | clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a); |
| 60 | /* Set M and N divisor inputs and enable clock */ |
| 61 | lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE); |
| 62 | lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN); |
| 63 | |
| 64 | } |
| 65 | |
| 66 | uintptr_t uart_platform_base(int idx) |
| 67 | { |
| 68 | return (CONFIG_CONSOLE_UART_BASE_ADDRESS); |
| 69 | } |
| 70 | |
Aaron Durbin | a513519 | 2016-02-24 19:00:03 -0600 | [diff] [blame] | 71 | static const struct pad_config uart_gpios[] = { |
| 72 | PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ |
| 73 | PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ |
| 74 | PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ |
| 75 | PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ |
| 76 | }; |
| 77 | |
| 78 | void soc_console_uart_init(void) |
| 79 | { |
| 80 | /* Get a 0-based pad index. See invalid_uart_for_console() above. */ |
| 81 | const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; |
| 82 | |
| 83 | if (invalid_uart_for_console()) |
| 84 | return; |
| 85 | |
| 86 | /* Configure the 2 pads per UART. */ |
| 87 | gpio_configure_pads(&uart_gpios[pad_index * 2], 2); |
| 88 | |
| 89 | lpss_console_uart_init(); |
| 90 | } |