blob: 9d1be5c709e8c7d529f5369e27ad3ae04b2e7780 [file] [log] [blame]
Hannah Williams733b39a2016-02-11 13:46:28 -08001/*
2 * This file is part of the coreboot project.
3 *
Alexandru Gagniuc717dccc2016-04-06 10:49:55 -07004 * Copyright (C) 2016 Intel Corp.
5 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
Hannah Williams733b39a2016-02-11 13:46:28 -08006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
Hannah Williams733b39a2016-02-11 13:46:28 -080018#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_ids.h>
Shaunak Saha5b6c5a52016-06-07 02:06:28 -070021#include <console/console.h>
Hannah Williams733b39a2016-02-11 13:46:28 -080022#include <soc/iomap.h>
23#include <soc/pci_ids.h>
Shaunak Saha5b6c5a52016-06-07 02:06:28 -070024#include <soc/gpio.h>
25#include <soc/pci_devs.h>
26#include <soc/pm.h>
27#include "chip.h"
Hannah Williams733b39a2016-02-11 13:46:28 -080028
Alexandru Gagniuc717dccc2016-04-06 10:49:55 -070029/*
30 * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases
31 * where the BAR reads back as 0, but the IO window is open. This also means
32 * that it will not respond to PCI probing. In the event that probing the BAR
33 * fails, we still need to create a resource for it.
34 */
35static void read_resources(device_t dev)
Hannah Williams733b39a2016-02-11 13:46:28 -080036{
37 struct resource *res;
Alexandru Gagniuc717dccc2016-04-06 10:49:55 -070038 pci_dev_read_resources(dev);
Hannah Williams733b39a2016-02-11 13:46:28 -080039
40 res = new_resource(dev, PCI_BASE_ADDRESS_4);
41 res->base = ACPI_PMIO_BASE;
Alexandru Gagniuc717dccc2016-04-06 10:49:55 -070042 res->size = ACPI_PMIO_SIZE;
Hannah Williams733b39a2016-02-11 13:46:28 -080043 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
44}
45
Alexandru Gagniuca942bd42016-05-18 14:41:48 -070046/*
47 * Part 2:
48 * Resources are assigned, and no other device was given an IO resource to
49 * overlap with our ACPI BAR. But because the resource is FIXED,
50 * pci_dev_set_resources() will not store it for us. We need to do that
51 * explicitly.
52 */
53static void set_resources(device_t dev)
54{
55 struct resource *res;
56
57 pci_dev_set_resources(dev);
58
59 res = find_resource(dev, PCI_BASE_ADDRESS_4);
60 pci_write_config32(dev, res->index, res->base);
61 dev->command |= PCI_COMMAND_IO;
62 res->flags |= IORESOURCE_STORED;
63 report_resource_stored(dev, res, " ACPI BAR");
64}
65
Shaunak Saha5b6c5a52016-06-07 02:06:28 -070066static void pmc_gpe_init(void)
67{
68 uint32_t gpio_cfg = 0;
69 uint32_t gpio_cfg_reg;
70 uint8_t dw1, dw2, dw3;
71 const struct soc_intel_apollolake_config *config;
72
73 struct device *dev = NB_DEV_ROOT;
74 if (!dev || !dev->chip_info) {
75 printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
76 return;
77 }
78 config = dev->chip_info;
79
80 uintptr_t pmc_bar = get_pmc_mmio_bar();
81
82 const uint32_t gpio_cfg_mask =
83 (GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
84 (GPE0_DWX_MASK << GPE0_DW2_SHIFT) |
85 (GPE0_DWX_MASK << GPE0_DW3_SHIFT);
86
87 /* Assign to local variable */
88 dw1 = config->gpe0_dw1;
89 dw2 = config->gpe0_dw2;
90 dw3 = config->gpe0_dw3;
91
92 /* Making sure that bad values don't bleed into the other fields */
93 dw1 &= GPE0_DWX_MASK;
94 dw2 &= GPE0_DWX_MASK;
95 dw3 &= GPE0_DWX_MASK;
96
97 /* Route the GPIOs to the GPE0 block. Determine that all values
98 * are different, and if they aren't use the reset values.
99 * DW0 is reserved/unused */
100 if (dw1 == dw2 || dw2 == dw3) {
101 printk(BIOS_INFO, "PMC: Using default GPE route.\n");
102 gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
103
104 dw1 = (gpio_cfg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK;
105 dw2 = (gpio_cfg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK;
106 dw3 = (gpio_cfg >> GPE0_DW3_SHIFT) & GPE0_DWX_MASK;
107 } else {
108 gpio_cfg |= (uint32_t)dw1 << GPE0_DW1_SHIFT;
109 gpio_cfg |= (uint32_t)dw2 << GPE0_DW2_SHIFT;
110 gpio_cfg |= (uint32_t)dw3 << GPE0_DW3_SHIFT;
111 }
112
113 gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
114 gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
115
116 write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
117
118 /* Set the routes in the GPIO communities as well. */
119 gpio_route_gpe(dw1, dw2, dw3);
120}
121
122static void pmc_init(struct device *dev)
123{
124 /* Set up GPE configuration */
125 pmc_gpe_init();
126}
127
Hannah Williams733b39a2016-02-11 13:46:28 -0800128static const struct device_operations device_ops = {
Alexandru Gagniuc717dccc2016-04-06 10:49:55 -0700129 .read_resources = read_resources,
Alexandru Gagniuca942bd42016-05-18 14:41:48 -0700130 .set_resources = set_resources,
Alexandru Gagniuc717dccc2016-04-06 10:49:55 -0700131 .enable_resources = pci_dev_enable_resources,
Shaunak Saha5b6c5a52016-06-07 02:06:28 -0700132 .init = &pmc_init,
Hannah Williams733b39a2016-02-11 13:46:28 -0800133};
134
135static const struct pci_driver pmc __pci_driver = {
136 .ops = &device_ops,
137 .vendor = PCI_VENDOR_ID_INTEL,
138 .device = PCI_DEVICE_ID_APOLLOLAKE_PMC,
139};