| Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <cpu/x86/mtrr.h> |
| 18 | #include <cpu/x86/cr.h> |
| 19 | #include <soc/cpu.h> |
| 20 | |
| 21 | .text |
| 22 | .global chipset_teardown_car |
| 23 | chipset_teardown_car: |
| 24 | /* |
| 25 | * Retrieve return address from stack as it will get trashed below if |
| 26 | * execution is utilizing the cache-as-ram stack. |
| 27 | */ |
| 28 | pop %ebx |
| 29 | |
| 30 | /* invalidate cache contents. */ |
| 31 | invd |
| 32 | /* Disable MTRRs. */ |
| 33 | mov $(MTRR_DEF_TYPE_MSR), %ecx |
| 34 | rdmsr |
| 35 | and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax |
| 36 | wrmsr |
| 37 | |
| 38 | /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ |
| 39 | mov $(MSR_EVICT_CTL), %ecx |
| 40 | rdmsr |
| 41 | and $(~(1 << 1)), %eax |
| 42 | wrmsr |
| 43 | and $(~(1 << 0)), %eax |
| 44 | wrmsr |
| 45 | |
| 46 | /* Return to caller. */ |
| 47 | jmp *%ebx |