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Ravi Sarawadi9d903a12016-03-04 21:33:04 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015-2016 Intel Corp.
5 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
6 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
Martin Rothebabfad2016-04-10 11:09:16 -060012 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Ravi Sarawadi9d903a12016-03-04 21:33:04 -080017 */
18
19#include <console/console.h>
20#include <cpu/cpu.h>
21#include <cpu/x86/cache.h>
22#include <cpu/x86/mp.h>
23#include <cpu/x86/msr.h>
24#include <cpu/x86/mtrr.h>
25#include <device/device.h>
26#include <device/pci.h>
27#include <soc/cpu.h>
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070028#include <soc/smm.h>
Ravi Sarawadi9d903a12016-03-04 21:33:04 -080029
30static struct device_operations cpu_dev_ops = {
31 .init = DEVICE_NOOP,
32};
33
34static struct cpu_device_id cpu_table[] = {
35 { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
36 { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
37 { 0, 0 },
38};
39
40static const struct cpu_driver driver __cpu_driver = {
41 .ops = &cpu_dev_ops,
42 .id_table = cpu_table,
43};
44
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070045
46/*
47 * MP and SMM loading initialization.
48 */
49struct smm_relocation_attrs {
50 uint32_t smbase;
51 uint32_t smrr_base;
52 uint32_t smrr_mask;
53};
54
55static struct smm_relocation_attrs relo_attrs;
56
Ravi Sarawadi9d903a12016-03-04 21:33:04 -080057static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
58{
59 msr_t msr;
60 msr = rdmsr(MSR_CORE_THREAD_COUNT);
61 *num_virt = (msr.lo >> 0) & 0xffff;
62 *num_phys = (msr.lo >> 16) & 0xffff;
63}
64
65/*
66 * Do essential initialization tasks before APs can be fired up
67 *
68 * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
69 * creates the MTRR solution that the APs will use. Otherwise APs will try to
70 * apply the incomplete solution as the BSP is calculating it.
71 */
Aaron Durbine72b9d42016-05-03 15:56:24 -050072static void pre_mp_init(void)
Ravi Sarawadi9d903a12016-03-04 21:33:04 -080073{
74 x86_setup_mtrrs_with_detect();
75 x86_mtrr_check();
76}
77
Aaron Durbine72b9d42016-05-03 15:56:24 -050078/* Find CPU topology */
79static int get_cpu_count(void)
80{
81 unsigned int num_virt_cores, num_phys_cores;
82
83 read_cpu_topology(&num_phys_cores, &num_virt_cores);
84
85 printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
86 num_phys_cores, num_virt_cores);
87
88 return num_virt_cores;
89}
90
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070091static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
92 size_t *smm_save_state_size)
93{
94 void *smm_base;
95 size_t smm_size;
96
97 /* All range registers are aligned to 4KiB */
98 const uint32_t rmask = ~((1 << 12) - 1);
99
100 /* Initialize global tracking state. */
101 smm_region(&smm_base, &smm_size);
102 relo_attrs.smbase = (uint32_t)smm_base;
103 relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
104 relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
105 relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
106
107 *perm_smbase = relo_attrs.smbase;
108 *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE;
109 *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
110}
111
112static void relocation_handler(int cpu, uintptr_t curr_smbase,
113 uintptr_t staggered_smbase)
114{
115 msr_t smrr;
116 em64t100_smm_state_save_area_t *smm_state;
117 /* Set up SMRR. */
118 smrr.lo = relo_attrs.smrr_base;
119 smrr.hi = 0;
120 wrmsr(SMRR_PHYS_BASE, smrr);
121 smrr.lo = relo_attrs.smrr_mask;
122 smrr.hi = 0;
123 wrmsr(SMRR_PHYS_MASK, smrr);
124 smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
125 smm_state->smbase = staggered_smbase;
126}
Ravi Sarawadi9d903a12016-03-04 21:33:04 -0800127/*
128 * CPU initialization recipe
129 *
130 * Note that no microcode update is passed to the init function. CSE updates
131 * the microcode on all cores before releasing them from reset. That means that
132 * the BSP and all APs will come up with the same microcode revision.
133 */
Aaron Durbine72b9d42016-05-03 15:56:24 -0500134static const struct mp_ops mp_ops = {
135 .pre_mp_init = pre_mp_init,
136 .get_cpu_count = get_cpu_count,
Hannah Williamsd9c84ca2016-05-13 00:47:14 -0700137 .get_smm_info = get_smm_info,
138 .pre_mp_smm_init = southbridge_smm_clear_state,
139 .relocation_handler = relocation_handler,
140 .post_mp_init = southbridge_smm_enable_smi,
Ravi Sarawadi9d903a12016-03-04 21:33:04 -0800141};
142
143void apollolake_init_cpus(device_t dev)
144{
Ravi Sarawadi9d903a12016-03-04 21:33:04 -0800145 /* Clear for take-off */
Aaron Durbine72b9d42016-05-03 15:56:24 -0500146 if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
Ravi Sarawadi9d903a12016-03-04 21:33:04 -0800147 printk(BIOS_ERR, "MP initialization failure.\n");
148}