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Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -07001ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
2
3subdirs-y += ../../../cpu/intel/microcode
4subdirs-y += ../../../cpu/intel/turbo
5subdirs-y += ../../../cpu/x86/lapic
6subdirs-y += ../../../cpu/x86/mtrr
7subdirs-y += ../../../cpu/x86/smm
8subdirs-y += ../../../cpu/x86/tsc
Ravi Sarawadi9d903a12016-03-04 21:33:04 -08009subdirs-y += ../../../cpu/x86/cache
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070010
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -070011bootblock-y += bootblock/bootblock.c
12bootblock-y += bootblock/cache_as_ram.S
Andrey Petrov87fb1a62016-02-10 17:47:03 -080013bootblock-y += bootblock/bootblock.c
Aaron Durbin595688a2016-03-31 11:38:13 -050014bootblock-y += car.c
Andrey Petrov57799dc2016-02-09 17:02:57 -080015bootblock-y += gpio.c
Andrey Petrovfcd51ff2016-07-14 17:16:35 -070016bootblock-y += heci.c
Aaron Durbin1318e882016-07-12 23:39:51 -050017bootblock-y += itss.c
Alexandru Gagniuce237f8b2016-03-30 12:09:05 -070018bootblock-y += lpc_lib.c
Andrey Petrov5672dcd2016-02-12 15:12:43 -080019bootblock-y += mmap_boot.c
Andrey Petrov3dbea292016-06-14 22:20:28 -070020bootblock-y += pmutil.c
Furquan Shaikh6ac226d2016-06-15 17:13:20 -070021bootblock-y += spi.c
Andrey Petrov87fb1a62016-02-10 17:47:03 -080022bootblock-y += tsc_freq.c
Aaron Durbin61810302016-02-24 18:49:07 -060023bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -070024
Aaron Durbin595688a2016-03-31 11:38:13 -050025romstage-y += car.c
Andrey Petrovb4831462016-02-25 17:42:25 -080026romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
Andrey Petrov57799dc2016-02-09 17:02:57 -080027romstage-y += gpio.c
Andrey Petrovfcd51ff2016-07-14 17:16:35 -070028romstage-y += heci.c
Duncan Laurieff8bce02016-06-27 10:57:13 -070029romstage-y += i2c_early.c
Aaron Durbin1318e882016-07-12 23:39:51 -050030romstage-y += itss.c
Aaron Durbin61810302016-02-24 18:49:07 -060031romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
Alexandru Gagniuce237f8b2016-03-30 12:09:05 -070032romstage-y += lpc_lib.c
Andrey Petrov491c0162016-03-02 15:09:27 -080033romstage-y += memmap.c
Aaron Durbinfc2e7412016-05-12 12:43:37 -050034romstage-y += meminit.c
Andrey Petrov5672dcd2016-02-12 15:12:43 -080035romstage-y += mmap_boot.c
Andrey Petrovc6ee58c2016-04-12 17:00:52 -070036romstage-y += tsc_freq.c
Hannah Williams01bc8972016-02-04 20:13:34 -080037romstage-y += pmutil.c
Andrey Petrov0f593c22016-06-17 15:30:13 -070038romstage-y += reset.c
Furquan Shaikhbae63832016-06-17 15:50:24 -070039romstage-y += spi.c
Andrey Petrov87fb1a62016-02-10 17:47:03 -080040
Aaron Durbinb3f54182016-05-26 14:22:34 -050041smm-y += mmap_boot.c
Hannah Williams01bc8972016-02-04 20:13:34 -080042smm-y += pmutil.c
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070043smm-y += smihandler.c
Aaron Durbinb3f54182016-05-26 14:22:34 -050044smm-y += spi.c
45smm-y += tsc_freq.c
Aaron Durbinac57f082016-06-10 15:49:21 -050046smm-y += uart_early.c
Lance Zhaof51b1272015-11-09 17:06:34 -080047
48ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
Ravi Sarawadi9d903a12016-03-04 21:33:04 -080049ramstage-y += cpu.c
Andrey Petrov70efecd2016-03-04 21:41:13 -080050ramstage-y += chip.c
Harsha Priya29f351e2016-07-01 11:53:05 -070051ramstage-y += dsp.c
Andrey Petrov57799dc2016-02-09 17:02:57 -080052ramstage-y += gpio.c
Alexandru Gagniucc3640192015-12-15 16:06:15 -080053ramstage-y += graphics.c
Andrey Petrovfcd51ff2016-07-14 17:16:35 -070054ramstage-y += heci.c
Duncan Laurieff8bce02016-06-27 10:57:13 -070055ramstage-y += i2c.c
Aaron Durbin1318e882016-07-12 23:39:51 -050056ramstage-y += itss.c
Aaron Durbin61810302016-02-24 18:49:07 -060057ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
Lance Zhaoa7ff9c52015-11-12 18:19:41 -080058ramstage-y += lpc.c
Alexandru Gagniuce237f8b2016-03-30 12:09:05 -070059ramstage-y += lpc_lib.c
Andrey Petrov491c0162016-03-02 15:09:27 -080060ramstage-y += memmap.c
Andrey Petrov5672dcd2016-02-12 15:12:43 -080061ramstage-y += mmap_boot.c
Aaron Durbinfadfc2e2016-07-01 16:36:03 -050062ramstage-y += p2sb.c
Andrey Petrov1e70cda2016-03-08 16:12:06 -080063ramstage-y += uart.c
Saurabh Satija734aa872016-06-21 14:22:16 -070064ramstage-y += nhlt.c
Andrey Petrova2176d82016-01-15 18:05:12 -080065ramstage-y += northbridge.c
Alexandru Gagniuc0581a672016-02-24 15:08:23 -080066ramstage-y += spi.c
Andrey Petrovc6ee58c2016-04-12 17:00:52 -070067ramstage-y += tsc_freq.c
Hannah Williams01bc8972016-02-04 20:13:34 -080068ramstage-y += pmutil.c
Hannah Williams733b39a2016-02-11 13:46:28 -080069ramstage-y += pmc.c
Andrey Petrov0f593c22016-06-17 15:30:13 -070070ramstage-y += reset.c
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070071ramstage-y += smi.c
Furquan Shaikh0be3da52016-06-19 23:20:43 -070072ramstage-y += spi.c
Aaron Durbin2c29d342016-07-21 17:58:16 -050073ramstage-y += xhci.c
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070074
Aaron Durbineebe0e02016-03-18 11:19:38 -050075postcar-y += exit_car.S
76postcar-y += memmap.c
77postcar-y += mmap_boot.c
Furquan Shaikh0be3da52016-06-19 23:20:43 -070078postcar-y += spi.c
Aaron Durbineebe0e02016-03-18 11:19:38 -050079postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
Hannah Williamsb13d4542016-03-14 17:38:51 -070080postcar-y += tsc_freq.c
Aaron Durbineebe0e02016-03-18 11:19:38 -050081
Furquan Shaikhb54a2d12016-06-01 01:55:43 -070082verstage-y += car.c
Duncan Laurieff8bce02016-06-27 10:57:13 -070083verstage-y += i2c_early.c
Andrey Petrovfcd51ff2016-07-14 17:16:35 -070084verstage-y += heci.c
Aaron Durbinbef75e72016-05-26 11:00:44 -050085verstage-y += memmap.c
86verstage-y += mmap_boot.c
87verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
88verstage-y += tsc_freq.c
89verstage-y += pmutil.c
Andrey Petrov0f593c22016-06-17 15:30:13 -070090verstage-y += reset.c
Furquan Shaikh0be3da52016-06-19 23:20:43 -070091verstage-y += spi.c
Aaron Durbinbef75e72016-05-26 11:00:44 -050092
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -070093CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
94
Andrey Petrov79091db72016-05-17 00:03:27 -070095# Since FSP-M runs in CAR we need to relocate it to a specific address
96$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
97
Aaron Durbin9f444c32016-05-20 10:48:44 -050098ifeq ($(CONFIG_NEED_LBP2),y)
99files_added::
100 $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward
101endif
102
Furquan Shaikh7043bf32016-05-28 12:57:05 -0700103# Bootblock on Apollolake platform lies in the IFWI region. In order to place
104# the bootblock at the right location in IFWI image -
105# a. Using ifwitool:
106# 1. Create IFWI image (ifwi.bin.tmp) from input image
107# (CONFIG_IFWI_FILE_NAME).
108# 2. Delete OBBP sub-partition, if present.
109# 3. Replace IBBL directory entry in IBBP sub-partition with currently
110# generated bootblock.bin.
111# b. Using cbfstool:
112# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME.
113ifeq ($(CONFIG_NEED_IFWI),y)
114files_added:: $(IFWITOOL)
115 $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp
116 $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP
117 $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL
118 $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward
119endif
120
Saurabh Satija734aa872016-06-21 14:22:16 -0700121# DSP firmware settings files.
122NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs
123DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
124MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin
125DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin
126
127cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B)
128$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)
129$(DMIC_2CH_48KHZ_16B)-type := raw
130
131cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER)
132$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER)
133$(MAX98357_RENDER)-type := raw
134
135cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE)
136$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE)
137$(DA7219_RENDER_CAPTURE)-type := raw
138
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -0700139endif