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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / util / inteltool / spi.c
blob: bd584b6d53fe7c7e9a03595c12154887285788fd [file] [log] [blame]
Alexander Couzensaa3dd5d2015-01-03 02:52:10 +0100[diff] [blame]1
2#include <stdio.h>
3#include <stdlib.h>
4#include "inteltool.h"
5
6static const io_register_t pch_bios_cntl_registers[] = {
7 { 0x0, 1, "BIOSWE - write enable" },
8 { 0x1, 1, "BLE - lock enable" },
9 { 0x2, 2, "SPI Read configuration" },
10 { 0x4, 1, "TopSwapStatus" },
11 { 0x5, 1, "SMM Bios Write Protect Disable" },
12 { 0x6, 2, "reserved" },
13};
14
15#define SPIBAR 0x3800
16
17static const io_register_t spi_bar_registers[] = {
18 { SPIBAR + 0x00, 4, "BFPR - BIOS Flash primary region" },
19 { SPIBAR + 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
20 { SPIBAR + 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
21 { SPIBAR + 0x08, 4, "FADDR - Flash Address" },
22 { SPIBAR + 0x0c, 4, "Reserved" },
23 { SPIBAR + 0x10, 4, "FDATA0" },
24 /* 0x10 .. 0x4f are filled with data */
25 { SPIBAR + 0x50, 4, "FRACC - Flash Region Access Permissions" },
26 { SPIBAR + 0x54, 4, "Flash Region 0" },
27 { SPIBAR + 0x58, 4, "Flash Region 1" },
28 { SPIBAR + 0x5c, 4, "Flash Region 2" },
29 { SPIBAR + 0x60, 4, "Flash Region 3" },
30 { SPIBAR + 0x64, 4, "Flash Region 4" },
31 { SPIBAR + 0x74, 4, "FPR0 Flash Protected Range 0" },
32 { SPIBAR + 0x78, 4, "FPR0 Flash Protected Range 1" },
33 { SPIBAR + 0x7c, 4, "FPR0 Flash Protected Range 2" },
34 { SPIBAR + 0x80, 4, "FPR0 Flash Protected Range 3" },
35 { SPIBAR + 0x84, 4, "FPR0 Flash Protected Range 4" },
36 { SPIBAR + 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
37 { SPIBAR + 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
38 { SPIBAR + 0x94, 2, "PREOP - Prefix opcode Configuration" },
39 { SPIBAR + 0x96, 2, "OPTYPE - Opcode Type Configuration" },
40 { SPIBAR + 0x98, 8, "OPMENU - Opcode Menu Configuration" },
41 { SPIBAR + 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
42 { SPIBAR + 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
43 { SPIBAR + 0xb8, 4, "Reserved" },
44 { SPIBAR + 0xc0, 4, "AFC - Additional Flash Control" },
45 { SPIBAR + 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
46 { SPIBAR + 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
47 { SPIBAR + 0xd0, 4, "FPB - Flash Partition Boundary" },
48};
49
50int print_bioscntl(struct pci_dev *sb)
51{
52 int i, size = 0;
53 unsigned char bios_cntl = 0xff;
54 const io_register_t *bios_cntl_register = NULL;
55
56 printf("\n============= SPI / BIOS CNTL =============\n\n");
57
58 switch (sb->device_id) {
59 case PCI_DEVICE_ID_INTEL_3400:
60 case PCI_DEVICE_ID_INTEL_3420:
61 case PCI_DEVICE_ID_INTEL_3450:
62 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
63 case PCI_DEVICE_ID_INTEL_B55_A:
64 case PCI_DEVICE_ID_INTEL_B55_B:
65 case PCI_DEVICE_ID_INTEL_H55:
66 case PCI_DEVICE_ID_INTEL_H57:
67 case PCI_DEVICE_ID_INTEL_P55:
68 case PCI_DEVICE_ID_INTEL_Q57:
69 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
70 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
71 case PCI_DEVICE_ID_INTEL_HM55:
72 case PCI_DEVICE_ID_INTEL_HM57:
73 case PCI_DEVICE_ID_INTEL_PM55:
74 case PCI_DEVICE_ID_INTEL_QM57:
75 case PCI_DEVICE_ID_INTEL_QS57:
76 bios_cntl = pci_read_byte(sb, 0xdc);
77 bios_cntl_register = pch_bios_cntl_registers;
78 size = ARRAY_SIZE(pch_bios_cntl_registers);
79 break;
80 default:
81 printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
82 return 1;
83 }
84
85 printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl);
86
87 if (bios_cntl_register) {
88 for (i = 0; i < size; i++) {
89 unsigned int val = bios_cntl >> bios_cntl_register[i].addr;
90 val &= ((1 << bios_cntl_register[i].size) -1);
91 printf("0x%04x = %s\n", val, bios_cntl_register[i].name);
92 }
93 }
94
95 return 0;
96}
97
98int print_spibar(struct pci_dev *sb) {
99 int i, size = 0, rcba_size = 0x4000;
100 volatile uint8_t *rcba;
101 uint32_t rcba_phys;
102 const io_register_t *spi_register = NULL;
103
104 printf("\n============= SPI Bar ==============\n\n");
105
106 switch (sb->device_id) {
107 case PCI_DEVICE_ID_INTEL_ICH6:
108 case PCI_DEVICE_ID_INTEL_ICH7:
109 case PCI_DEVICE_ID_INTEL_ICH7M:
110 case PCI_DEVICE_ID_INTEL_ICH7DH:
111 case PCI_DEVICE_ID_INTEL_ICH7MDH:
112 case PCI_DEVICE_ID_INTEL_ICH8:
113 case PCI_DEVICE_ID_INTEL_ICH8M:
Lubomir Rintel2a13bad2015-03-01 10:14:15 +0100[diff] [blame]114 case PCI_DEVICE_ID_INTEL_ICH8ME:
Alexander Couzensaa3dd5d2015-01-03 02:52:10 +0100[diff] [blame]115 case PCI_DEVICE_ID_INTEL_ICH9DH:
116 case PCI_DEVICE_ID_INTEL_ICH9DO:
117 case PCI_DEVICE_ID_INTEL_ICH9R:
118 case PCI_DEVICE_ID_INTEL_ICH9:
119 case PCI_DEVICE_ID_INTEL_ICH9M:
120 case PCI_DEVICE_ID_INTEL_ICH9ME:
121 case PCI_DEVICE_ID_INTEL_ICH10R:
122 case PCI_DEVICE_ID_INTEL_NM10:
123 case PCI_DEVICE_ID_INTEL_I63XX:
124 case PCI_DEVICE_ID_INTEL_3400:
125 case PCI_DEVICE_ID_INTEL_3420:
126 case PCI_DEVICE_ID_INTEL_3450:
127 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
128 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
129 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
130 case PCI_DEVICE_ID_INTEL_B55_A:
131 case PCI_DEVICE_ID_INTEL_B55_B:
132 case PCI_DEVICE_ID_INTEL_H55:
133 case PCI_DEVICE_ID_INTEL_H57:
134 case PCI_DEVICE_ID_INTEL_HM55:
135 case PCI_DEVICE_ID_INTEL_HM57:
136 case PCI_DEVICE_ID_INTEL_P55:
137 case PCI_DEVICE_ID_INTEL_PM55:
138 case PCI_DEVICE_ID_INTEL_Q57:
139 case PCI_DEVICE_ID_INTEL_QM57:
140 case PCI_DEVICE_ID_INTEL_QS57:
141 case PCI_DEVICE_ID_INTEL_Z68:
142 case PCI_DEVICE_ID_INTEL_P67:
143 case PCI_DEVICE_ID_INTEL_UM67:
144 case PCI_DEVICE_ID_INTEL_HM65:
145 case PCI_DEVICE_ID_INTEL_H67:
146 case PCI_DEVICE_ID_INTEL_HM67:
147 case PCI_DEVICE_ID_INTEL_Q65:
148 case PCI_DEVICE_ID_INTEL_QS67:
149 case PCI_DEVICE_ID_INTEL_Q67:
150 case PCI_DEVICE_ID_INTEL_QM67:
151 case PCI_DEVICE_ID_INTEL_B65:
152 case PCI_DEVICE_ID_INTEL_C202:
153 case PCI_DEVICE_ID_INTEL_C204:
154 case PCI_DEVICE_ID_INTEL_C206:
155 case PCI_DEVICE_ID_INTEL_H61:
156 case PCI_DEVICE_ID_INTEL_Z77:
157 case PCI_DEVICE_ID_INTEL_Z75:
158 case PCI_DEVICE_ID_INTEL_Q77:
159 case PCI_DEVICE_ID_INTEL_Q75:
160 case PCI_DEVICE_ID_INTEL_B75:
161 case PCI_DEVICE_ID_INTEL_H77:
162 case PCI_DEVICE_ID_INTEL_C216:
163 case PCI_DEVICE_ID_INTEL_QM77:
164 case PCI_DEVICE_ID_INTEL_QS77:
165 case PCI_DEVICE_ID_INTEL_HM77:
166 case PCI_DEVICE_ID_INTEL_UM77:
167 case PCI_DEVICE_ID_INTEL_HM76:
168 case PCI_DEVICE_ID_INTEL_HM75:
169 case PCI_DEVICE_ID_INTEL_HM70:
170 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
171 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
172 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
Matt DeVillier5b667df2015-05-14 21:58:33 -0500[diff] [blame]173 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
Alexander Couzensaa3dd5d2015-01-03 02:52:10 +0100[diff] [blame]174 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
175 size = ARRAY_SIZE(spi_bar_registers);
176 spi_register = spi_bar_registers;
177 break;
178 case PCI_DEVICE_ID_INTEL_ICH:
179 case PCI_DEVICE_ID_INTEL_ICH0:
180 case PCI_DEVICE_ID_INTEL_ICH2:
181 case PCI_DEVICE_ID_INTEL_ICH4:
182 case PCI_DEVICE_ID_INTEL_ICH4M:
183 case PCI_DEVICE_ID_INTEL_ICH5:
184 printf("This southbridge does not have RCBA.\n");
185 return 1;
186 default:
187 printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
188 return 1;
189 }
190
191 rcba = map_physical(rcba_phys, rcba_size);
192 if (rcba == NULL) {
193 perror("Error mapping RCBA");
194 exit(1);
195 }
196
197 for (i = 0; i < size; i++) {
198 switch(spi_register[i].size) {
199 case 1:
200 printf("0x%08x = %s\n", *(uint8_t *)(rcba + spi_register[i].addr), spi_register[i].name);
201 break;
202 case 2:
203 printf("0x%08x = %s\n", *(uint16_t *)(rcba + spi_register[i].addr), spi_register[i].name);
204 break;
205 case 4:
206 printf("0x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), spi_register[i].name);
207 break;
208 case 8:
209 printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), *(uint32_t *)(rcba + spi_register[i].addr + 4), spi_register[i].name);
210 break;
211 }
212 }
213
214 unmap_physical((void *)rcba, rcba_size);
215 return 0;
216}
217
218int print_spi(struct pci_dev *sb) {
219 return (print_bioscntl(sb) || print_spibar(sb));
220}