blob: 2970a9fee33a497900e603372f7a6aeabeeb695a [file] [log] [blame]
Vladimir Serbinenko3129f792014-10-15 21:51:47 +02001package main
2
3import "fmt"
4
5func LenovoEC(ctx Context) {
6 ap := Create(ctx, "acpi/platform.asl")
7 defer ap.Close()
8
9 wakeGPE := 13
10
11 sbGPE := GuessECGPE(ctx)
12 var GPE int
13 var GPEUnsure bool
14 if sbGPE < 0 {
15 sbGPE = SouthBridge.EncodeGPE(1)
16 GPE = 1
17 GPEUnsure = true
18 SouthBridge.NeedRouteGPIOManually()
19 } else {
20 GPE = SouthBridge.DecodeGPE(sbGPE)
21 GPEUnsure = false
22 }
23
24 SouthBridge.EnableGPE(wakeGPE)
25 SouthBridge.EnableGPE(GPE)
26
27 GPEDefine := DSDTDefine{
28 Key: "THINKPAD_EC_GPE",
29 }
30
31 GPEDefine.Value = fmt.Sprintf("%d", sbGPE)
32 if GPEUnsure {
33 GPEDefine.Comment = "FIXME: Check this"
34 }
35
36 DSDTDefines = append(DSDTDefines,
37 DSDTDefine{
38 Key: "EC_LENOVO_H8_ME_WORKAROUND",
39 Value: "1",
40 }, GPEDefine)
41
42 ap.WriteString(
43 `Method(_WAK,1)
44{
45 /* ME may not be up yet. */
46 Store (0, \_TZ.MEB1)
47 Store (0, \_TZ.MEB2)
48 Return(Package(){0,0})
49}
50
51Method(_PTS,1)
52{
53 \_SB.PCI0.LPCB.EC.RADI(0)
54}
55`)
56
57 si := Create(ctx, "acpi/superio.asl")
58 defer si.Close()
59
60 si.WriteString("#include <drivers/pc80/ps2_controller.asl>\n")
61
62 dock := Create(ctx, "dock.c")
63 defer dock.Close()
64
65 AddRAMStageFile("dock.c", "")
66
67 dock.WriteString(
68 `#include <ec/lenovo/h8/h8.h>
69
70void h8_mainboard_init_dock (void)
71{
72/* FIXME: fill this if needed. */
73}
74`)
75
76 /* FIXME:XX Move this to ec/lenovo. */
77 smi := Create(ctx, "smihandler.c")
78 defer smi.Close()
79
80 AddSMMFile("smihandler.c", "")
81
82 smi.WriteString(
83 `/*
84 * This file is part of the coreboot project.
85 *
86 * Copyright (C) 2008-2009 coresystems GmbH
87 * Copyright (C) 2014 Vladimir Serbinenko
88 *
89 * This program is free software; you can redistribute it and/or
90 * modify it under the terms of the GNU General Public License as
91 * published by the Free Software Foundation; version 2 of
92 * the License.
93 *
94 * This program is distributed in the hope that it will be useful,
95 * but WITHOUT ANY WARRANTY; without even the implied warranty of
96 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
97 * GNU General Public License for more details.
Vladimir Serbinenko3129f792014-10-15 21:51:47 +020098 */
99
100#include <arch/io.h>
101#include <console/console.h>
102#include <cpu/x86/smm.h>
103#include <ec/acpi/ec.h>
104#include <ec/lenovo/h8/h8.h>
105#include <delay.h>
106#include <` + SouthBridge.GetGPIOHeader() + ">\n\n")
107
108 if GPEUnsure {
109 smi.WriteString("/* FIXME: check this */\n")
110 }
111 fmt.Fprintf(smi, "#define GPE_EC_SCI %d\n", GPE)
112
113 smi.WriteString("/* FIXME: check this */\n")
114 fmt.Fprintf(smi, "#define GPE_EC_WAKE %d\n", wakeGPE)
115
116 smi.WriteString(`
117static void mainboard_smm_init(void)
118{
119 printk(BIOS_DEBUG, "initializing SMI\n");
120 /* Enable 0x1600/0x1600 register pair */
121 ec_set_bit(0x00, 0x05);
122}
123
124int mainboard_io_trap_handler(int smif)
125{
126 static int smm_initialized;
127
128 if (!smm_initialized) {
129 mainboard_smm_init();
130 smm_initialized = 1;
131 }
132
133 return 0;
134}
135
136static void mainboard_smi_handle_ec_sci(void)
137{
138 u8 status = inb(EC_SC);
139 u8 event;
140
141 if (!(status & EC_SCI_EVT))
142 return;
143
144 event = ec_query();
145 printk(BIOS_DEBUG, "EC event %02x\n", event);
146}
147
148void mainboard_smi_gpi(u32 gpi_sts)
149{
150 if (gpi_sts & (1 << GPE_EC_SCI))
151 mainboard_smi_handle_ec_sci();
152}
153
154int mainboard_smi_apmc(u8 data)
155{
156 switch (data) {
157 case APM_CNT_ACPI_ENABLE:
158 /* use 0x1600/0x1604 to prevent races with userspace */
159 ec_set_ports(0x1604, 0x1600);
160 /* route EC_SCI to SCI */
161 gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
162 /* discard all events, and enable attention */
163 ec_write(0x80, 0x01);
164 break;
165 case APM_CNT_ACPI_DISABLE:
166 /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
167 provide a EC query function */
168 ec_set_ports(0x66, 0x62);
169 /* route EC_SCI to SMI */
170 gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
171 /* discard all events, and enable attention */
172 ec_write(0x80, 0x01);
173 break;
174 default:
175 break;
176 }
177 return 0;
178}
179
180void mainboard_smi_sleep(u8 slp_typ)
181{
182 if (slp_typ == 3) {
183 u8 ec_wake = ec_read(0x32);
184 /* If EC wake events are enabled, enable wake on EC WAKE GPE. */
185 if (ec_wake & 0x14) {
186 /* Redirect EC WAKE GPE to SCI. */
187 gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
188 }
189 }
190}
191`)
192
193 ec := Create(ctx, "acpi/ec.asl")
194 defer ec.Close()
195
196 ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n")
197
198 KconfigBool["EC_LENOVO_PMH7"] = true
199 KconfigBool["EC_LENOVO_H8"] = true
200
201 pmh := DevTreeNode{
202 Chip: "ec/lenovo/pmh7",
203 Registers: map[string]string{
204 "backlight_enable": "0x01",
205 "dock_event_enable": "0x01",
206 },
207 Children: []DevTreeNode{
208 DevTreeNode{
209 Chip: "pnp",
210 Comment: "dummy",
211 Dev: 0xff,
212 Func: 1,
213 },
214 },
215 }
216 PutChip("lpc", pmh)
217
218 ecs := ctx.InfoSource.GetEC()
219 h8 := DevTreeNode{
220 Chip: "ec/lenovo/h8",
221 Children: []DevTreeNode{
222 DevTreeNode{
223 Chip: "pnp",
224 Comment: "dummy",
225 Dev: 0xff,
226 Func: 2,
227 IOs: map[uint16]uint16{
228 0x60: 0x62,
229 0x62: 0x66,
230 0x64: 0x1600,
231 0x66: 0x1604,
232 },
233 },
234 },
235 Comment: "FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb",
236 Registers: map[string]string{
237 "config0": FormatHex8(ecs[0]),
238 "config1": FormatHex8(ecs[1]),
239 "config2": FormatHex8(ecs[2]),
240 "config3": FormatHex8(ecs[3]),
241 "beepmask0": FormatHex8(ecs[4]),
242 "beepmask1": FormatHex8(ecs[5]),
243 },
244 }
245 for i := 0; i < 0x10; i++ {
246 if ecs[0x10+i] != 0 {
247 h8.Registers[fmt.Sprintf("event%x_enable", i)] = FormatHex8(ecs[0x10+i])
248 }
249 }
250 PutChip("lpc", h8)
251
252 eeprom := DevTreeNode{
253 Chip: "drivers/i2c/at24rf08c",
254 Comment: "eeprom, 8 virtual devices, same chip",
255 Children: []DevTreeNode{
256 DevTreeNode{
257 Chip: "i2c",
258 Dev: 0x54,
259 },
260 DevTreeNode{
261 Chip: "i2c",
262 Dev: 0x55,
263 },
264 DevTreeNode{
265 Chip: "i2c",
266 Dev: 0x56,
267 },
268 DevTreeNode{
269 Chip: "i2c",
270 Dev: 0x57,
271 },
272 DevTreeNode{
273 Chip: "i2c",
274 Dev: 0x5c,
275 },
276 DevTreeNode{
277 Chip: "i2c",
278 Dev: 0x5d,
279 },
280 DevTreeNode{
281 Chip: "i2c",
282 Dev: 0x5e,
283 },
284 DevTreeNode{
285 Chip: "i2c",
286 Dev: 0x5f,
287 },
288 },
289 }
290 PutChip("smbus", eeprom)
291}