Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 17 | #ifndef SUPERIO_ITE_IT8772F_H |
| 18 | #define SUPERIO_ITE_IT8772F_H |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 19 | |
Ted Kuo | 4e8f23b | 2015-03-18 10:42:22 +0800 | [diff] [blame] | 20 | /* Supported thermal mode on TMPINx */ |
| 21 | enum thermal_mode { |
| 22 | THERMAL_MODE_DISABLED = 0, |
| 23 | THERMAL_DIODE, |
| 24 | THERMAL_RESISTOR, |
| 25 | }; |
| 26 | |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 27 | #define IT8772F_FDC 0x00 /* Floppy disk controller */ |
| 28 | #define IT8772F_SP1 0x01 /* Com1 */ |
| 29 | #define IT8772F_EC 0x04 /* Environment controller */ |
| 30 | #define IT8772F_KBCK 0x05 /* Keyboard */ |
| 31 | #define IT8772F_KBCM 0x06 /* Mouse */ |
| 32 | #define IT8772F_GPIO 0x07 /* GPIO */ |
| 33 | #define IT8772F_IR 0x0a /* Consumer IR */ |
| 34 | |
| 35 | /* Environmental Controller interface */ |
Ted Kuo | 4e8f23b | 2015-03-18 10:42:22 +0800 | [diff] [blame] | 36 | #define IT8772F_CONFIGURATION 0x00 |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 37 | #define IT8772F_INTERFACE_SELECT 0x0a |
| 38 | #define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) |
| 39 | #define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) |
| 40 | #define IT8772F_INTERFACE_SEL_DISABLE (0 << 4) |
| 41 | #define IT8772F_INTERFACE_SEL_SST_SLAVE (1 << 4) |
| 42 | #define IT8772F_INTERFACE_SEL_PECI (2 << 4) |
| 43 | #define IT8772F_INTERFACE_SEL_SST_HOST (3 << 4) |
| 44 | #define IT8772F_INTERFACE_CLOCK_32MHZ (0 << 3) |
| 45 | #define IT8772F_INTERFACE_CLOCK_24MHZ (1 << 3) |
| 46 | #define IT8772F_INTERFACE_SPEED_TOLERANCE (1 << 2) |
| 47 | #define IT8772F_INTERFACE_PECI_AWFCS (1 << 0) |
| 48 | #define IT8772F_FAN_TAC2_READ 0x0e |
| 49 | #define IT8772F_FAN_TAC3_READ 0x0f |
| 50 | #define IT8772F_FAN_MAIN_CTL 0x13 |
| 51 | #define IT8772F_FAN_MAIN_CTL_TAC_SMART(x) (1 << ((x)-1)) |
| 52 | #define IT8772F_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) |
| 53 | #define IT8772F_FAN_CTL_MODE 0x14 |
| 54 | #define IT8772F_FAN_CTL_ON(x) (1 << ((x)-1)) |
| 55 | #define IT8772F_FAN_PWM_MIN_DUTY (1 << 3) |
| 56 | #define IT8772F_FAN_PWM_CLOCK_48MHZ (0 << 4) |
| 57 | #define IT8772F_FAN_PWM_CLOCK_24MHZ (1 << 4) |
| 58 | #define IT8772F_FAN_PWM_CLOCK_8MHZ (3 << 4) |
| 59 | #define IT8772F_FAN_PWM_CLOCK_6MHZ (4 << 4) |
| 60 | #define IT8772F_FAN_PWM_CLOCK_3MHZ (5 << 4) |
| 61 | #define IT8772F_FAN_PWM_CLOCK_1_5MHZ (6 << 4) |
| 62 | #define IT8772F_FAN_PWM_CLOCK_51KHZ (7 << 4) |
| 63 | #define IT8772F_FAN_CTL_POLARITY_LOW (0 << 7) |
| 64 | #define IT8772F_FAN_CTL_POLARITY_HIGH (1 << 7) |
| 65 | #define IT8772F_FAN_CTL2_PWM_MODE 0x16 |
| 66 | #define IT8772F_FAN_CTL3_PWM_MODE 0x17 |
| 67 | #define IT8772F_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7) |
| 68 | #define IT8772F_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7) |
| 69 | #define IT8772F_ADC_TEMP_CHANNEL_ENABLE 0x51 |
| 70 | #define IT8772F_FAN_CTL2_PWM_START 0x6b |
| 71 | #define IT8772F_FAN_CTL2_AUTO_MODE 0x6c |
| 72 | #define IT8772F_FAN_CTL3_PWM_START 0x73 |
| 73 | #define IT8772F_FAN_CTL3_AUTO_MODE 0x74 |
| 74 | #define IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS (0 << 7) |
| 75 | #define IT8772F_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) |
| 76 | #define IT8772F_EXTEMP_STATUS 0x88 |
Ryan Lin | bd97885 | 2014-09-22 23:29:16 -0700 | [diff] [blame] | 77 | #define IT8772F_EXTEMP_STATUS_HOST_BUSY (1 << 0) |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 78 | #define IT8772F_EXTEMP_ADDRESS 0x89 |
| 79 | #define IT8772F_EXTEMP_WRITE_LENGTH 0x8a |
| 80 | #define IT8772F_EXTEMP_READ_LENGTH 0x8b |
| 81 | #define IT8772F_EXTEMP_COMMAND 0x8c |
| 82 | #define IT8772F_EXTEMP_WRITE_DATA_2 0x8d |
| 83 | #define IT8772F_EXTEMP_CONTROL 0x8e |
| 84 | #define IT8772F_EXTEMP_CONTROL_AUTO_32HZ (0 << 6) |
| 85 | #define IT8772F_EXTEMP_CONTROL_AUTO_16HZ (1 << 6) |
| 86 | #define IT8772F_EXTEMP_CONTROL_AUTO_8HZ (2 << 6) |
| 87 | #define IT8772F_EXTEMP_CONTROL_AUTO_4HZ (3 << 6) |
| 88 | #define IT8772F_EXTEMP_CONTROL_AUTO_START (1 << 5) |
| 89 | #define IT8772F_EXTEMP_CONTROL_AUTO_ABORT (1 << 4) |
| 90 | #define IT8772F_EXTEMP_CONTROL_AUTO_TWO_DOMAIN (1 << 3) |
| 91 | #define IT8772F_EXTEMP_CONTROL_CONTENTION (1 << 2) |
| 92 | #define IT8772F_EXTEMP_CONTROL_SST_IDLE_HIGH (1 << 1) |
| 93 | #define IT8772F_EXTEMP_CONTROL_START (1 << 0) |
| 94 | |
| 95 | /* Standard PECI GetTemp */ |
| 96 | #define PECI_CLIENT_ADDRESS 0x30 |
| 97 | #define PECI_GETTEMP_COMMAND 0x01 |
| 98 | #define PECI_GETTEMP_WRITE_LENGTH 0x01 |
| 99 | #define PECI_GETTEMP_READ_LENGTH 0x02 |
| 100 | |
| 101 | /* GPIO interface */ |
| 102 | #define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8 |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 103 | |
| 104 | #define SIO_GPIO_BLINK_GPIO10 0x08 |
| 105 | #define SIO_GPIO_BLINK_GPIO45 0x25 |
| 106 | |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 107 | #define IT8772F_GPIO_LED_BLINK1_CONTROL 0xf9 |
| 108 | |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 109 | #define IT8772F_GPIO_BLINK_FREQUENCY_4_HZ (0<<1) |
| 110 | #define IT8772F_GPIO_BLINK_FREQUENCY_1_HZ (1<<1) |
| 111 | #define IT8772F_GPIO_BLINK_FREQUENCY_1_4_HZ (2<<1) |
| 112 | #define IT8772F_GPIO_BLINK_FREQUENCY_1_8_HZ (3<<1) |
| 113 | |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 114 | #define GPIO_REG_SELECT(x) (0x25 + (x)) |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 115 | |
| 116 | /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 117 | #define GPIO_REG_POLARITY(x) (0xb0 + (x)) |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 118 | |
| 119 | /* GPIO Inernal Pull-up: 1: Enable, 0: Disable */ |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 120 | #define GPIO_REG_PULLUP(x) (0xb8 + (x)) |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 121 | |
| 122 | /* GPIO Fucntion Select: 1: Simple I/O, 0: Alternate function */ |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 123 | #define GPIO_REG_ENABLE(x) (0xc0 + (x)) |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 124 | |
| 125 | /* GPIO Mode: 0: input mode, 1: output mode */ |
Stefan Reinauer | b0dd1d9 | 2012-03-30 15:04:07 -0700 | [diff] [blame] | 126 | #define GPIO_REG_OUTPUT(x) (0xc8 + (x)) |
| 127 | |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 128 | #include <arch/io.h> |
| 129 | #include <stdint.h> |
| 130 | |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 131 | u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg); |
| 132 | void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value); |
| 133 | void it8772f_ac_resume_southbridge(pnp_devfn_t dev); |
| 134 | void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 135 | u8 pullup, u8 output, u8 enable); |
| 136 | |
| 137 | /* FIXME: should be static so will be removed later.. */ |
| 138 | /* Global configuration registers. */ |
| 139 | #define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ |
| 140 | #define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ |
| 141 | |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 142 | void it8772f_enter_conf(pnp_devfn_t dev); |
| 143 | void it8772f_exit_conf(pnp_devfn_t dev); |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 144 | void it8772f_gpio_led(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, |
| 145 | u8 output, u8 enable, u8 led_pin_map, u8 led_freq); |
| 146 | |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 147 | |
| 148 | #endif /* SUPERIO_ITE_IT8772F_H */ |