Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <device/pnp_def.h> |
| 19 | |
| 20 | #include "it8772f.h" |
| 21 | |
| 22 | /* NOTICE: This file is deprecated, use ite/common instead */ |
| 23 | |
| 24 | /* RAMstage equiv */ |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 25 | /* u8 pnp_read_config(pnp_devfn_t dev, u8 reg) */ |
| 26 | u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg) |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 27 | { |
| 28 | u16 port = dev >> 8; |
| 29 | |
| 30 | outb(reg, port); |
| 31 | return inb(port + 1); |
| 32 | } |
| 33 | |
| 34 | /* RAMstage equiv */ |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 35 | /* void pnp_write_config(pnp_devfn_t dev, u8 reg, u8 value) */ |
| 36 | void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value) |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 37 | { |
| 38 | u16 port = dev >> 8; |
| 39 | |
| 40 | outb(reg, port); |
| 41 | outb(value, port + 1); |
| 42 | } |
| 43 | |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 44 | void it8772f_enter_conf(pnp_devfn_t dev) |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 45 | { |
| 46 | u16 port = dev >> 8; |
| 47 | |
| 48 | outb(0x87, port); |
| 49 | outb(0x01, port); |
| 50 | outb(0x55, port); |
| 51 | outb((port == 0x4e) ? 0xaa : 0x55, port); |
| 52 | } |
| 53 | |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 54 | void it8772f_exit_conf(pnp_devfn_t dev) |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 55 | { |
| 56 | it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02); |
| 57 | } |
| 58 | |
| 59 | /* Set AC resume to be up to the Southbridge */ |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 60 | void it8772f_ac_resume_southbridge(pnp_devfn_t dev) |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 61 | { |
| 62 | it8772f_enter_conf(dev); |
| 63 | it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); |
| 64 | it8772f_sio_write(dev, 0xf4, 0x60); |
| 65 | it8772f_exit_conf(dev); |
| 66 | } |
| 67 | |
| 68 | /* Configure a set of GPIOs */ |
Edward O'Callaghan | 85836c2 | 2014-07-09 20:26:25 +1000 | [diff] [blame] | 69 | void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 70 | u8 pullup, u8 output, u8 enable) |
| 71 | { |
| 72 | set--; /* Set 1 is offset 0 */ |
| 73 | it8772f_enter_conf(dev); |
| 74 | it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); |
| 75 | if (set < 5) { |
| 76 | it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); |
| 77 | it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); |
| 78 | it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); |
| 79 | } |
| 80 | it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); |
| 81 | it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); |
| 82 | it8772f_exit_conf(dev); |
| 83 | } |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 84 | |
| 85 | /* Configure LED GPIOs */ |
| 86 | void it8772f_gpio_led(pnp_devfn_t dev,int set, u8 select, u8 polarity, u8 pullup, |
| 87 | u8 output, u8 enable, u8 led_pin_map, u8 led_freq) |
| 88 | { |
| 89 | set--; /* Set 1 is offset 0 */ |
| 90 | it8772f_enter_conf(dev); |
| 91 | it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); |
| 92 | if (set < 5) { |
| 93 | it8772f_sio_write(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); |
| 94 | it8772f_sio_write(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); |
| 95 | it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); |
| 96 | it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); |
| 97 | it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); |
| 98 | } |
| 99 | it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); |
| 100 | it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); |
| 101 | it8772f_exit_conf(dev); |
| 102 | } |