blob: 02700a61e2628a24390ca1bdafe058bf75337d7f [file] [log] [blame]
Edward O'Callaghanf2920022014-04-27 00:41:50 +10001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Edward O'Callaghanf2920022014-04-27 00:41:50 +100015 */
16
17#ifndef SUPERIO_ITE_COMMON_ROMSTAGE_H
18#define SUPERIO_ITE_COMMON_ROMSTAGE_H
19
20#include <arch/io.h>
21#include <stdint.h>
22
23#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */
24#define ITE_UART_CLK_PREDIVIDE_24 0x01
25
Edward O'Callaghan85836c22014-07-09 20:26:25 +100026void ite_conf_clkin(pnp_devfn_t dev, u8 predivide);
27void ite_enable_serial(pnp_devfn_t dev, u16 iobase);
Edward O'Callaghanf2920022014-04-27 00:41:50 +100028
29/* Some boards need to init wdt+gpio's very early */
Edward O'Callaghan85836c22014-07-09 20:26:25 +100030void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value);
31void ite_enable_3vsbsw(pnp_devfn_t dev);
32void ite_kill_watchdog(pnp_devfn_t dev);
Edward O'Callaghanf2920022014-04-27 00:41:50 +100033
34#endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */