Corey Osgood | 36b601c | 2007-03-17 14:00:23 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Corey Osgood | 36b601c | 2007-03-17 14:00:23 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006-2007 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Corey Osgood | 36b601c | 2007-03-17 14:00:23 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | /* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x |
| 19 | * by Corey Osgood. See vt82c686.h for more information. */ |
| 20 | |
Stefan Reinauer | 24d1d4b | 2013-03-21 11:51:41 -0700 | [diff] [blame] | 21 | #include <arch/io.h> |
Corey Osgood | 36b601c | 2007-03-17 14:00:23 +0000 | [diff] [blame] | 22 | #include <device/pci_ids.h> |
| 23 | #include "vt82c686.h" |
| 24 | |
| 25 | #define SIO_INDEX 0x3f0 |
| 26 | #define SIO_DATA 0x3f1 |
| 27 | |
| 28 | /** |
| 29 | * Configure the chip by writing the byte 'value' into the register |
| 30 | * specified by 'index'. |
| 31 | * |
| 32 | * @param index The index of the register to modify. |
| 33 | * @param value The value to write into the register. |
| 34 | */ |
| 35 | static void vt82c686_sio_write(uint8_t index, uint8_t value) |
| 36 | { |
| 37 | outb(index, SIO_INDEX); |
| 38 | outb(value, SIO_DATA); |
| 39 | } |
| 40 | |
| 41 | /** |
| 42 | * Enable the serial port(s) of the VT82C686(A/B) Super I/O chip. |
| 43 | * |
| 44 | * @param dev TODO |
| 45 | * @param iobase TODO |
| 46 | */ |
| 47 | static void vt82c686_enable_serial(device_t dev, unsigned iobase) |
| 48 | { |
| 49 | uint8_t reg; |
| 50 | device_t sbdev; |
| 51 | |
| 52 | /* TODO: Use info from 'dev' and 'iobase'. */ |
| 53 | /* TODO: Only enable one serial port (depending on config) or both? */ |
| 54 | |
| 55 | /* (1) Enter configuration mode (set Function 0 Rx85[1] = 1). */ |
| 56 | |
| 57 | /* Find the southbridge. Die upon error. */ |
| 58 | sbdev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 59 | PCI_DEVICE_ID_VIA_82C686), 0); |
| 60 | // sbdev = PCI_DEV(0, 7, 0); |
| 61 | if (sbdev == PCI_DEV_INVALID) { |
| 62 | /* Serial output is not yet working at this point, but |
| 63 | * die() emits the POST code 0xff and halts the CPU, too. */ |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 64 | die("Southbridge not found.\n"); |
Corey Osgood | 36b601c | 2007-03-17 14:00:23 +0000 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */ |
| 68 | reg = pci_read_config8(sbdev, 0x85); |
| 69 | pci_write_config8(sbdev, 0x85, reg | 0x3); /* Set bits 0 and 1. */ |
| 70 | |
| 71 | /* (2) Configure the chip. */ |
| 72 | |
| 73 | /* Enable serial port 1 (set bit 2) and 2 (set bit 3). */ |
| 74 | vt82c686_sio_write(VT82C686_FS, 0xf); |
| 75 | |
| 76 | // vt82c686_sio_write(VT82C686_POWER, 0x00); /* No powerdown */ |
| 77 | // vt82c686_sio_write(VT82C686_SP_CTRL, 0x00); /* Normal operation */ |
| 78 | vt82c686_sio_write(VT82C686_SP1, 0xfe); /* SP1: 0x3f8 */ |
| 79 | vt82c686_sio_write(VT82C686_SP2, 0xbe); /* SP2: 0x2f8 */ |
| 80 | |
| 81 | /* Enable high speed on serial port 1 (set bit 6) and 2 (set bit 7). */ |
| 82 | vt82c686_sio_write(VT82C686_SP_CFG, 0xc0); |
| 83 | |
| 84 | /* (3) Exit configuration mode (set Function 0 Rx85[1] = 0). */ |
| 85 | reg = pci_read_config8(sbdev, 0x85); |
| 86 | pci_write_config8(sbdev, 0x85, reg & 0xfd); /* Clear bit 1. */ |
| 87 | } |