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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / southbridge / nvidia / mcp55 / ide.c
blob: 4e618742e09ec69cc0a5ed4297d1a9cd8761ecff [file] [log] [blame]
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]1/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +0000[diff] [blame]2 * This file is part of the coreboot project.
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]3 *
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]18 */
19
20#include <console/console.h>
21#include <device/device.h>
22#include <device/pci.h>
23#include <device/pci_ids.h>
24#include <device/pci_ops.h>
25#include "mcp55.h"
26
27static void ide_init(struct device *dev)
28{
29 struct southbridge_nvidia_mcp55_config *conf;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000[diff] [blame]30 u32 dword;
31 u16 word;
32 u8 byte;
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]33 conf = dev->chip_info;
34
35 word = pci_read_config16(dev, 0x50);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000[diff] [blame]36 /* Ensure prefetch is disabled. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]37 word &= ~((1 << 15) | (1 << 13));
38 if (conf->ide1_enable) {
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000[diff] [blame]39 /* Enable secondary IDE interface. */
40 word |= (1 << 0);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]41 printk(BIOS_DEBUG, "IDE1 \t");
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]42 }
43 if (conf->ide0_enable) {
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000[diff] [blame]44 /* Enable primary IDE interface. */
45 word |= (1 << 1);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]46 printk(BIOS_DEBUG, "IDE0\n");
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]47 }
48
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000[diff] [blame]49 word |= (1 << 12);
50 word |= (1 << 14);
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]51
52 pci_write_config16(dev, 0x50, word);
53
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000[diff] [blame]54 byte = 0x20; /* Latency: 64-->32 */
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]55 pci_write_config8(dev, 0xd, byte);
56
57 dword = pci_read_config32(dev, 0xf8);
58 dword |= 12;
59 pci_write_config32(dev, 0xf8, dword);
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]60}
61
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000[diff] [blame]62static struct device_operations ide_ops = {
63 .read_resources = pci_dev_read_resources,
64 .set_resources = pci_dev_set_resources,
65 .enable_resources = pci_dev_enable_resources,
66 .init = ide_init,
67 .scan_bus = 0,
68// .enable = mcp55_enable,
69 .ops_pci = &mcp55_pci_ops,
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]70};
71
Stefan Reinauerf1cf1f72007-10-24 09:08:58 +0000[diff] [blame]72static const struct pci_driver ide_driver __pci_driver = {
Yinghai Luc65bd562007-02-01 00:10:05 +0000[diff] [blame]73 .ops = &ide_ops,
74 .vendor = PCI_VENDOR_ID_NVIDIA,
75 .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE,
76};