Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 AMD |
| 5 | * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
Stefan Reinauer | d55e26f | 2010-04-25 13:54:30 +0000 | [diff] [blame] | 18 | #ifdef UNUSED_CODE |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 19 | int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); |
Myles Watson | ad894c5 | 2010-04-30 17:11:03 +0000 | [diff] [blame] | 20 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 21 | static int set_ht_link_mcp55(u8 ht_c_num) |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 22 | { |
| 23 | unsigned vendorid = 0x10de; |
| 24 | unsigned val = 0x01610109; |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 25 | /* NVIDIA MCP55 hardcode, hardware can not set it automatically. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 26 | return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); |
| 27 | } |
| 28 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 29 | static void setup_ss_table(unsigned index, unsigned where, unsigned control, |
| 30 | const unsigned int *register_values, int max) |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 31 | { |
| 32 | int i; |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 33 | unsigned val; |
| 34 | |
| 35 | val = inl(control); |
| 36 | val &= 0xfffffffe; |
| 37 | outl(val, control); |
| 38 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 39 | outl(0, index); /* Index */ |
| 40 | for (i = 0; i < max; i++) { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 41 | unsigned long reg; |
| 42 | reg = register_values[i]; |
| 43 | outl(reg, where); |
| 44 | } |
| 45 | |
| 46 | val = inl(control); |
| 47 | val |= 1; |
| 48 | outl(val, control); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 49 | } |
Stefan Reinauer | d55e26f | 2010-04-25 13:54:30 +0000 | [diff] [blame] | 50 | #endif |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 51 | |
| 52 | /* SIZE 0x100 */ |
| 53 | #define ANACTRL_IO_BASE 0x2800 |
| 54 | #define ANACTRL_REG_POS 0x68 |
| 55 | |
| 56 | /* SIZE 0x100 */ |
| 57 | #define SYSCTRL_IO_BASE 0x2400 |
| 58 | #define SYSCTRL_REG_POS 0x64 |
| 59 | |
| 60 | /* SIZE 0x100 */ |
| 61 | #define ACPICTRL_IO_BASE 0x2000 |
| 62 | #define ACPICTRL_REG_POS 0x60 |
| 63 | |
| 64 | /* |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 65 | * 16 1 1 1 1 8 :0 |
| 66 | * 16 0 4 0 0 8 :1 |
| 67 | * 16 0 4 2 2 4 :2 |
| 68 | * 4 4 4 4 4 8 :3 |
| 69 | * 8 8 4 0 0 8 :4 |
| 70 | * 8 0 4 4 4 8 :5 |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 71 | */ |
| 72 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 73 | #define MCP55_CHIP_REV 3 |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 74 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 75 | static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, |
| 76 | unsigned *devn, unsigned *io_base) |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 77 | { |
| 78 | |
| 79 | static const unsigned int ctrl_devport_conf[] = { |
| 80 | PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, |
| 81 | PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, |
| 82 | PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE, |
| 83 | }; |
| 84 | |
| 85 | int j; |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 86 | for (j = 0; j < mcp55_num; j++ ) { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 87 | setup_resource_map_offset(ctrl_devport_conf, |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 88 | ARRAY_SIZE(ctrl_devport_conf), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 89 | PCI_DEV(busn[j], devn[j], 0) , io_base[j]); |
| 90 | } |
| 91 | } |
| 92 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 93 | static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, |
| 94 | unsigned *devn, unsigned *io_base) |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 95 | { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 96 | static const unsigned int ctrl_devport_conf_clear[] = { |
| 97 | PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, |
| 98 | PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, |
| 99 | PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0, |
| 100 | }; |
| 101 | |
| 102 | int j; |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 103 | for (j = 0; j < mcp55_num; j++ ) { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 104 | setup_resource_map_offset(ctrl_devport_conf_clear, |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 105 | ARRAY_SIZE(ctrl_devport_conf_clear), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 106 | PCI_DEV(busn[j], devn[j], 0) , io_base[j]); |
| 107 | } |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 108 | } |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 109 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 110 | static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, |
| 111 | unsigned anactrl_io_base, unsigned pci_e_x) |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 112 | { |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 113 | u32 tgio_ctrl, pll_ctrl, dword; |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 114 | int i; |
| 115 | device_t dev; |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 116 | |
| 117 | dev = PCI_DEV(busnx, devnx + 1, 1); |
| 118 | |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 119 | dword = pci_read_config32(dev, 0xe4); |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 120 | dword |= 0x3f0; /* Disable it at first. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 121 | pci_write_config32(dev, 0xe4, dword); |
| 122 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 123 | for (i = 0; i < 3; i++) { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 124 | tgio_ctrl = inl(anactrl_io_base + 0xcc); |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 125 | tgio_ctrl &= ~(3 << 9); |
| 126 | tgio_ctrl |= (i << 9); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 127 | outl(tgio_ctrl, anactrl_io_base + 0xcc); |
| 128 | pll_ctrl = inl(anactrl_io_base + 0x30); |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 129 | pll_ctrl |= (1 << 31); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 130 | outl(pll_ctrl, anactrl_io_base + 0x30); |
| 131 | do { |
| 132 | pll_ctrl = inl(anactrl_io_base + 0x30); |
| 133 | } while (!(pll_ctrl & 1)); |
| 134 | } |
| 135 | tgio_ctrl = inl(anactrl_io_base + 0xcc); |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 136 | tgio_ctrl &= ~((7 << 4) | (1 << 8)); |
| 137 | tgio_ctrl |= (pci_e_x << 4) | (1 << 8); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 138 | outl(tgio_ctrl, anactrl_io_base + 0xcc); |
| 139 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 140 | udelay(100); /* Wait 100us. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 141 | |
| 142 | dword = pci_read_config32(dev, 0xe4); |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 143 | dword &= ~(0x3f0); /* Enable. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 144 | pci_write_config32(dev, 0xe4, dword); |
| 145 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 146 | mdelay(100); /* Need to wait 100ms. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 147 | } |
| 148 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 149 | static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, |
| 150 | unsigned *devn, unsigned *io_base, |
| 151 | unsigned *pci_e_x) |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 152 | { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 153 | static const unsigned int ctrl_conf_1[] = { |
| 154 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, |
| 155 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000, |
| 156 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200, |
| 157 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002, |
| 158 | |
| 159 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230, |
| 160 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222, |
| 161 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000, |
| 162 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000, |
| 163 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000, |
| 164 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, |
| 165 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200, |
| 166 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, |
| 167 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400, |
| 168 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, |
| 169 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000, |
| 170 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010, |
| 171 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500, |
| 172 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000, |
| 173 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000, |
| 174 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00, |
| 175 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000, |
| 176 | |
| 177 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 178 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002, |
| 179 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011, |
| 180 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923, |
| 181 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000, |
| 182 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F, |
| 183 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000, |
| 184 | |
| 185 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 186 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084, |
| 187 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 188 | |
| 189 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001, |
| 190 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002, |
| 191 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 192 | |
| 193 | RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 194 | RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF, |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 195 | RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 196 | |
| 197 | RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 198 | RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF, |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 199 | RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | static const unsigned int ctrl_conf_1_1[] = { |
| 203 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 204 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003, |
| 205 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001, |
| 206 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000, |
| 207 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100, |
| 208 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000, |
| 209 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A, |
| 210 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000, |
| 211 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, |
| 212 | }; |
| 213 | |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 214 | static const unsigned int ctrl_conf_mcp55_only[] = { |
| 215 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE, |
| 216 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, |
| 217 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000, |
| 218 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000, |
| 219 | |
| 220 | RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 221 | RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 222 | |
| 223 | RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 224 | |
| 225 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE, |
| 226 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000, |
| 227 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000, |
| 228 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00, |
| 229 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000, |
| 230 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570, |
| 231 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 232 | |
| 233 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104, |
| 234 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000, |
| 235 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000, |
| 236 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005, |
| 237 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000, |
| 238 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, |
| 239 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, |
| 240 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, |
Jonathan A. Kollasch | acba73a | 2015-07-20 09:51:34 -0500 | [diff] [blame] | 241 | #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) |
| 242 | /* |
| 243 | * Avoid crash (complete with severe memory corruption!) during initial CAR boot |
| 244 | * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78. |
| 245 | * Interestingly once the system is fully booted into Linux this can be set, but |
| 246 | * not before! Apparently something isn't initialized but the amount of effort |
| 247 | * required to fix this is non-negligible and of unknown real-world benefit |
| 248 | */ |
| 249 | #else |
Arne Georg Gleditsch | e7a5b76 | 2010-09-13 15:11:35 +0000 | [diff] [blame] | 250 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, |
Jonathan A. Kollasch | acba73a | 2015-07-20 09:51:34 -0500 | [diff] [blame] | 251 | #endif |
Uwe Hermann | f845e02 | 2007-09-25 01:31:35 +0000 | [diff] [blame] | 252 | |
Patrick Georgi | abc0c77 | 2010-10-05 17:59:12 +0000 | [diff] [blame] | 253 | #if CONFIG_MCP55_USE_AZA |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 254 | RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, |
| 255 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 256 | // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 257 | #endif |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 258 | |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 259 | #ifdef MCP55_MB_SETUP |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 260 | /* Play a while with GPIO in MCP55. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 261 | MCP55_MB_SETUP |
| 262 | #endif |
| 263 | |
Patrick Georgi | abc0c77 | 2010-10-05 17:59:12 +0000 | [diff] [blame] | 264 | #if CONFIG_MCP55_USE_AZA |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 265 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2), |
| 266 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2), |
| 267 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 268 | #endif |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 269 | }; |
| 270 | |
| 271 | static const unsigned int ctrl_conf_master_only[] = { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 272 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000, |
| 273 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 274 | /* Master MCP55???? YHLU */ |
| 275 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | static const unsigned int ctrl_conf_2[] = { |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 279 | /* I didn't put PCI-E related stuff here. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 280 | |
| 281 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0, |
| 282 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000, |
| 283 | |
| 284 | RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000, |
| 285 | |
| 286 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, |
| 287 | |
Patrick Georgi | abc0c77 | 2010-10-05 17:59:12 +0000 | [diff] [blame] | 288 | #if CONFIG_MCP55_USE_NIC |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 289 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 290 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 291 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), |
| 292 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 293 | #endif |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 294 | }; |
| 295 | |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 296 | int j, i; |
| 297 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 298 | for (j = 0; j < mcp55_num; j++) { |
| 299 | mcp55_early_pcie_setup(busn[j], devn[j], |
| 300 | io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 301 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 302 | setup_resource_map_x_offset(ctrl_conf_1, |
| 303 | ARRAY_SIZE(ctrl_conf_1), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 304 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 305 | |
| 306 | for (i = 0; i < 3; i++) { /* Three SATA */ |
| 307 | setup_resource_map_x_offset(ctrl_conf_1_1, |
| 308 | ARRAY_SIZE(ctrl_conf_1_1), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 309 | PCI_DEV(busn[j], devn[j], i), io_base[j]); |
| 310 | } |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 311 | |
| 312 | if (busn[j] == 0) { |
| 313 | setup_resource_map_x_offset(ctrl_conf_mcp55_only, |
| 314 | ARRAY_SIZE(ctrl_conf_mcp55_only), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 315 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
| 316 | } |
| 317 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 318 | if ((busn[j] == 0) && (mcp55_num>1)) { |
| 319 | setup_resource_map_x_offset(ctrl_conf_master_only, |
| 320 | ARRAY_SIZE(ctrl_conf_master_only), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 321 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
| 322 | } |
| 323 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 324 | setup_resource_map_x_offset(ctrl_conf_2, |
| 325 | ARRAY_SIZE(ctrl_conf_2), |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 326 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | #if 0 |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 330 | for (j = 0; j < mcp55_num; j++) { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 331 | // PCI-E (XSPLL) SS table 0x40, x044, 0x48 |
| 332 | // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 |
| 333 | // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 334 | setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, |
| 335 | io_base[j] + ANACTRL_IO_BASE + 0x44, |
| 336 | io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); |
| 337 | setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, |
| 338 | io_base[j] + ANACTRL_IO_BASE + 0xb4, |
| 339 | io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); |
| 340 | setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, |
| 341 | io_base[j] + ANACTRL_IO_BASE + 0xc4, |
| 342 | io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 343 | } |
| 344 | #endif |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | #ifndef HT_CHAIN_NUM_MAX |
| 348 | |
| 349 | #define HT_CHAIN_NUM_MAX 4 |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 350 | #define HT_CHAIN_BUSN_D 0x40 |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 351 | #define HT_CHAIN_IOBASE_D 0x4000 |
| 352 | |
| 353 | #endif |
| 354 | |
| 355 | static int mcp55_early_setup_x(void) |
| 356 | { |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 357 | /* Find out how many MCP55 we have. */ |
Scott Duplichan | 45057d2 | 2010-10-26 05:26:01 +0000 | [diff] [blame] | 358 | unsigned busn[HT_CHAIN_NUM_MAX] = {0}; |
| 359 | unsigned devn[HT_CHAIN_NUM_MAX] = {0}; |
| 360 | unsigned io_base[HT_CHAIN_NUM_MAX] = {0}; |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 361 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 362 | /* |
| 363 | * FIXME: May have problem if there is different MCP55 HTX card with |
| 364 | * different PCI_E lane allocation. Need to use same trick about |
| 365 | * pci1234 to verify node/link connection. |
| 366 | */ |
| 367 | unsigned pci_e_x[HT_CHAIN_NUM_MAX] = { |
| 368 | CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, |
| 369 | CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3, |
| 370 | }; |
| 371 | int mcp55_num = 0, ht_c_index; |
| 372 | unsigned busnx, devnx; |
| 373 | |
| 374 | /* FIXME: Multi PCI segment handling. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 375 | |
| 376 | /* Any system that only have IO55 without MCP55? */ |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 377 | for (ht_c_index = 0; ht_c_index < HT_CHAIN_NUM_MAX; ht_c_index++) { |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 378 | busnx = ht_c_index * HT_CHAIN_BUSN_D; |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 379 | for (devnx = 0; devnx < 0x20; devnx++) { |
| 380 | u32 id; |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 381 | device_t dev; |
| 382 | dev = PCI_DEV(busnx, devnx, 0); |
| 383 | id = pci_read_config32(dev, PCI_VENDOR_ID); |
| 384 | if(id == 0x036910de) { |
| 385 | busn[mcp55_num] = busnx; |
| 386 | devn[mcp55_num] = devnx; |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 387 | |
| 388 | /* We may have HT chain other than MCP55. */ |
| 389 | io_base[mcp55_num] |
| 390 | = ht_c_index * HT_CHAIN_IOBASE_D; |
| 391 | |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 392 | mcp55_num++; |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 393 | if (mcp55_num == CONFIG_MCP55_NUM) |
| 394 | goto out; |
| 395 | break; /* Only one MCP55 on one chain. */ |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 396 | } |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | out: |
Stefan Reinauer | 5ab52dd | 2015-01-05 13:01:01 -0800 | [diff] [blame] | 401 | printk(BIOS_DEBUG, "mcp55_num: %02x\n", mcp55_num); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 402 | |
| 403 | mcp55_early_set_port(mcp55_num, busn, devn, io_base); |
| 404 | mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x); |
| 405 | |
| 406 | mcp55_early_clear_port(mcp55_num, busn, devn, io_base); |
| 407 | |
Uwe Hermann | c7f0c8f | 2011-01-04 19:51:33 +0000 | [diff] [blame] | 408 | // set_ht_link_mcp55(HT_CHAIN_NUM_MAX); |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 409 | |
| 410 | return 0; |
Yinghai Lu | c65bd56 | 2007-02-01 00:10:05 +0000 | [diff] [blame] | 411 | } |