Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef SOUTHBRIDGE_INTEL_SCH_CHIP_H |
| 17 | #define SOUTHBRIDGE_INTEL_SCH_CHIP_H |
| 18 | |
| 19 | struct southbridge_intel_sch_config { |
| 20 | /** |
| 21 | * Interrupt Routing configuration |
| 22 | * If bit7 is 1, the interrupt is disabled. |
| 23 | */ |
| 24 | uint8_t pirqa_routing; |
| 25 | uint8_t pirqb_routing; |
| 26 | uint8_t pirqc_routing; |
| 27 | uint8_t pirqd_routing; |
| 28 | uint8_t pirqe_routing; |
| 29 | uint8_t pirqf_routing; |
| 30 | uint8_t pirqg_routing; |
| 31 | uint8_t pirqh_routing; |
| 32 | }; |
| 33 | |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 34 | #endif |