Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include "pch.h" |
| 22 | |
| 23 | static void pci_init(struct device *dev) |
| 24 | { |
| 25 | u16 reg16; |
| 26 | u8 reg8; |
| 27 | |
| 28 | printk(BIOS_DEBUG, "PCI init.\n"); |
| 29 | /* Enable Bus Master */ |
| 30 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 31 | reg16 |= PCI_COMMAND_MASTER; |
| 32 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 33 | |
| 34 | /* This device has no interrupt */ |
| 35 | pci_write_config8(dev, INTR, 0xff); |
| 36 | |
| 37 | /* disable parity error response and SERR */ |
| 38 | reg16 = pci_read_config16(dev, BCTRL); |
| 39 | reg16 &= ~(1 << 0); |
| 40 | reg16 &= ~(1 << 1); |
| 41 | pci_write_config16(dev, BCTRL, reg16); |
| 42 | |
| 43 | /* Master Latency Count must be set to 0x04! */ |
| 44 | reg8 = pci_read_config8(dev, SMLT); |
| 45 | reg8 &= 0x07; |
| 46 | reg8 |= (0x04 << 3); |
| 47 | pci_write_config8(dev, SMLT, reg8); |
| 48 | |
| 49 | /* Will this improve throughput of bus masters? */ |
| 50 | pci_write_config8(dev, PCI_MIN_GNT, 0x06); |
| 51 | |
| 52 | /* Clear errors in status registers */ |
| 53 | reg16 = pci_read_config16(dev, PSTS); |
| 54 | //reg16 |= 0xf900; |
| 55 | pci_write_config16(dev, PSTS, reg16); |
| 56 | |
| 57 | reg16 = pci_read_config16(dev, SECSTS); |
| 58 | // reg16 |= 0xf900; |
| 59 | pci_write_config16(dev, SECSTS, reg16); |
| 60 | } |
| 61 | |
| 62 | #undef PCI_BRIDGE_UPDATE_COMMAND |
| 63 | static void ich_pci_dev_enable_resources(struct device *dev) |
| 64 | { |
| 65 | const struct pci_operations *ops; |
| 66 | uint16_t command; |
| 67 | |
| 68 | /* Set the subsystem vendor and device id for mainboard devices */ |
| 69 | ops = ops_pci(dev); |
| 70 | if (dev->on_mainboard && ops && ops->set_subsystem) { |
| 71 | printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", |
| 72 | dev_path(dev), |
| 73 | CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, |
| 74 | CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); |
| 75 | ops->set_subsystem(dev, |
| 76 | CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, |
| 77 | CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); |
| 78 | } |
| 79 | |
| 80 | command = pci_read_config16(dev, PCI_COMMAND); |
| 81 | command |= dev->command; |
| 82 | #ifdef PCI_BRIDGE_UPDATE_COMMAND |
| 83 | /* If we write to PCI_COMMAND, on some systems |
| 84 | * this will cause the ROM and APICs not being visible |
| 85 | * anymore. |
| 86 | */ |
| 87 | printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); |
| 88 | pci_write_config16(dev, PCI_COMMAND, command); |
| 89 | #else |
| 90 | printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); |
| 91 | #endif |
| 92 | } |
| 93 | |
| 94 | static void ich_pci_bus_enable_resources(struct device *dev) |
| 95 | { |
| 96 | uint16_t ctrl; |
| 97 | /* enable IO in command register if there is VGA card |
| 98 | * connected with (even it does not claim IO resource) |
| 99 | */ |
| 100 | if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 101 | dev->command |= PCI_COMMAND_IO; |
| 102 | ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); |
| 103 | ctrl |= dev->link_list->bridge_ctrl; |
| 104 | ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ |
| 105 | printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); |
| 106 | pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 107 | |
| 108 | /* This is the reason we need our own pci_bus_enable_resources */ |
| 109 | ich_pci_dev_enable_resources(dev); |
| 110 | } |
| 111 | |
| 112 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 113 | { |
| 114 | /* NOTE: This is not the default position! */ |
| 115 | if (!vendor || !device) { |
| 116 | pci_write_config32(dev, 0x54, |
| 117 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 118 | } else { |
| 119 | pci_write_config32(dev, 0x54, |
| 120 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | static struct pci_operations pci_ops = { |
| 125 | .set_subsystem = set_subsystem, |
| 126 | }; |
| 127 | |
| 128 | static struct device_operations device_ops = { |
| 129 | .read_resources = pci_bus_read_resources, |
| 130 | .set_resources = pci_dev_set_resources, |
| 131 | .enable_resources = ich_pci_bus_enable_resources, |
| 132 | .init = pci_init, |
| 133 | .scan_bus = pci_scan_bridge, |
| 134 | .ops_pci = &pci_ops, |
| 135 | }; |
| 136 | |
| 137 | static const struct pci_driver pch_pci __pci_driver = { |
| 138 | .ops = &device_ops, |
| 139 | .vendor = PCI_VENDOR_ID_INTEL, |
| 140 | .device = 0x2448, |
| 141 | }; |