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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / southbridge / intel / lynxpoint / nvs.h
blob: 50936cf5e180eed8a136f2dffa18d497e7622825 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2011 Google Inc
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]15 */
16
17#include "vendorcode/google/chromeos/gnvs.h"
18typedef struct {
19 /* Miscellaneous */
20 u16 osys; /* 0x00 - Operating System */
21 u8 smif; /* 0x02 - SMI function call ("TRAP") */
22 u8 prm0; /* 0x03 - SMI function call parameter */
23 u8 prm1; /* 0x04 - SMI function call parameter */
24 u8 scif; /* 0x05 - SCI function call (via _L00) */
25 u8 prm2; /* 0x06 - SCI function call parameter */
26 u8 prm3; /* 0x07 - SCI function call parameter */
27 u8 lckf; /* 0x08 - Global Lock function for EC */
28 u8 prm4; /* 0x09 - Lock function parameter */
29 u8 prm5; /* 0x0a - Lock function parameter */
30 u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
31 u8 lids; /* 0x0f - LID state (open = 1) */
32 u8 pwrs; /* 0x10 - Power state (AC = 1) */
33 /* Thermal policy */
34 u8 tlvl; /* 0x11 - Throttle Level Limit */
35 u8 flvl; /* 0x12 - Current FAN Level */
36 u8 tcrt; /* 0x13 - Critical Threshold */
37 u8 tpsv; /* 0x14 - Passive Threshold */
38 u8 tmax; /* 0x15 - CPU Tj_max */
39 u8 f0of; /* 0x16 - FAN 0 OFF Threshold */
40 u8 f0on; /* 0x17 - FAN 0 ON Threshold */
41 u8 f0pw; /* 0x18 - FAN 0 PWM value */
42 u8 f1of; /* 0x19 - FAN 1 OFF Threshold */
43 u8 f1on; /* 0x1a - FAN 1 ON Threshold */
44 u8 f1pw; /* 0x1b - FAN 1 PWM value */
45 u8 f2of; /* 0x1c - FAN 2 OFF Threshold */
46 u8 f2on; /* 0x1d - FAN 2 ON Threshold */
47 u8 f2pw; /* 0x1e - FAN 2 PWM value */
48 u8 f3of; /* 0x1f - FAN 3 OFF Threshold */
49 u8 f3on; /* 0x20 - FAN 3 ON Threshold */
50 u8 f3pw; /* 0x21 - FAN 3 PWM value */
51 u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
52 u8 f4on; /* 0x23 - FAN 4 ON Threshold */
53 u8 f4pw; /* 0x24 - FAN 4 PWM value */
54 u8 tmps; /* 0x25 - Temperature Sensor ID */
55 u8 rsvd3[2];
56 /* Processor Identification */
57 u8 apic; /* 0x28 - APIC enabled */
58 u8 mpen; /* 0x29 - MP capable/enabled */
59 u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
60 u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
61 u8 ppcm; /* 0x2c - Max. PPC state */
62 u8 pcnt; /* 0x2d - Processor Count */
63 u8 rsvd4[4];
64 /* Super I/O & CMOS config */
65 u8 natp; /* 0x32 - SIO type */
66 u8 s5u0; /* 0x33 - Enable USB0 in S5 */
67 u8 s5u1; /* 0x34 - Enable USB1 in S5 */
68 u8 s3u0; /* 0x35 - Enable USB0 in S3 */
69 u8 s3u1; /* 0x36 - Enable USB1 in S3 */
70 u8 s33g; /* 0x37 - Enable S3 in 3G */
Kyösti Mälkkia0b4a8d2014-06-15 14:28:23 +0300[diff] [blame]71 u32 obsolete_cmem; /* 0x38 - CBMEM TOC */
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]72 /* Integrated Graphics Device */
73 u8 igds; /* 0x3c - IGD state */
74 u8 tlst; /* 0x3d - Display Toggle List Pointer */
75 u8 cadl; /* 0x3e - currently attached devices */
76 u8 padl; /* 0x3f - previously attached devices */
77 u16 cste; /* 0x40 - current display state */
78 u16 nste; /* 0x42 - next display state */
79 u16 sste; /* 0x44 - set display state */
80 u8 ndid; /* 0x46 - number of device ids */
81 u32 did[5]; /* 0x47 - 5b device id 1..5 */
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]82 /* TPM support */
Duncan Lauried0d7e7d2013-03-22 11:05:38 -0700[diff] [blame]83 u8 tpmp; /* 0x5b - TPM Present */
84 u8 tpme; /* 0x5c - TPM Enable */
85 u8 rsvd5[3];
86 /* LynxPoint Serial IO device BARs */
87 u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
88 u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
Aaron Durbin764d0092013-05-01 13:41:44 -0500[diff] [blame]89 u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
90 u8 rsvd6[16];
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]91 /* IGD OpRegion (not implemented yet) */
92 u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
93 u8 ibtt; /* 0xb8 - IGD boot type */
94 u8 ipat; /* 0xb9 - IGD panel type */
95 u8 itvf; /* 0xba - IGD TV format */
96 u8 itvm; /* 0xbb - IGD TV minor format */
97 u8 ipsc; /* 0xbc - IGD Panel Scaling */
98 u8 iblc; /* 0xbd - IGD BLC configuration */
99 u8 ibia; /* 0xbe - IGD BIA configuration */
100 u8 issc; /* 0xbf - IGD SSC configuration */
101 u8 i409; /* 0xc0 - IGD 0409 modified settings */
102 u8 i509; /* 0xc1 - IGD 0509 modified settings */
103 u8 i609; /* 0xc2 - IGD 0609 modified settings */
104 u8 i709; /* 0xc3 - IGD 0709 modified settings */
105 u8 idmm; /* 0xc4 - IGD Power Conservation */
106 u8 idms; /* 0xc5 - IGD DVMT memory size */
107 u8 if1e; /* 0xc6 - IGD Function 1 Enable */
108 u8 hvco; /* 0xc7 - IGD HPLL VCO */
109 u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
110 u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
111 u8 pavp; /* 0xe9 - IGD PAVP data */
112 u8 rsvd12; /* 0xea - rsvd */
113 u8 oscc; /* 0xeb - PCIe OSC control */
114 u8 npce; /* 0xec - native pcie support */
115 u8 plfl; /* 0xed - platform flavor */
116 u8 brev; /* 0xee - board revision */
117 u8 dpbm; /* 0xef - digital port b mode */
118 u8 dpcm; /* 0xf0 - digital port c mode */
119 u8 dpdm; /* 0xf1 - digital port c mode */
120 u8 alfp; /* 0xf2 - active lfp */
121 u8 imon; /* 0xf3 - current graphics turbo imon value */
122 u8 mmio; /* 0xf4 - 64bit mmio support */
123 u8 rsvd13[11]; /* 0xf5 - rsvd */
124
125 /* ChromeOS specific (starts at 0x100)*/
126 chromeos_acpi_t chromeos;
127} __attribute__((packed)) global_nvs_t;
128
129#ifdef __SMM__
130/* Used in SMM to find the ACPI GNVS address */
131global_nvs_t *smm_get_gnvs(void);
132#endif
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200[diff] [blame]133
134void acpi_create_gnvs(global_nvs_t * gnvs);