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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / southbridge / intel / i82870 / pci_parity.c
blob: 71d2c538e9194f8f44377c519aa2da431e76f4c5 [file] [log] [blame]
Yinghai Lu70093f72004-07-01 03:55:03 +0000[diff] [blame]1#include <pci.h>
2#include <arch/io.h>
3#include <printk.h>
4#
5
6void p64h2_pci_parity_enable(void)
7{
8 uint8_t reg;
9
10 /* 2SERREN - SERR enable for PCI bridge secondary device */
11 /* 2PEREN - Parity error for PCI bridge secondary device */
12 pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
13 reg |= ((1 << 1) + (1 << 0));
14 pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
15
16 /* 2SERREN - SERR enable for PCI bridge secondary device */
17 /* 2PEREN - Parity error for PCI bridge secondary device */
18 pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
19 reg |= ((1 << 1) + (1 << 0));
20 pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
21
22 return;
23}