Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * 2012 secunet Security Networks AG |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <console/console.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <cpu/cpu.h> |
| 24 | #include <cpu/x86/cache.h> |
| 25 | #include <cpu/x86/smm.h> |
| 26 | #include <string.h> |
| 27 | #include "i82801ix.h" |
| 28 | |
| 29 | extern unsigned char _binary_smm_start; |
| 30 | extern unsigned char _binary_smm_size; |
| 31 | |
| 32 | /* I945/GM45 */ |
| 33 | #define SMRAM 0x9d |
| 34 | #define D_OPEN (1 << 6) |
| 35 | #define D_CLS (1 << 5) |
| 36 | #define D_LCK (1 << 4) |
| 37 | #define G_SMRAME (1 << 3) |
| 38 | #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) |
| 39 | |
| 40 | /* While we read PMBASE dynamically in case it changed, let's |
| 41 | * initialize it with a sane value |
| 42 | */ |
| 43 | static u16 pmbase = DEFAULT_PMBASE; |
| 44 | |
| 45 | /** |
| 46 | * @brief read and clear PM1_STS |
| 47 | * @return PM1_STS register |
| 48 | */ |
| 49 | static u16 reset_pm1_status(void) |
| 50 | { |
| 51 | u16 reg16; |
| 52 | |
| 53 | reg16 = inw(pmbase + PM1_STS); |
| 54 | /* set status bits are cleared by writing 1 to them */ |
| 55 | outw(reg16, pmbase + PM1_STS); |
| 56 | |
| 57 | return reg16; |
| 58 | } |
| 59 | |
| 60 | static void dump_pm1_status(u16 pm1_sts) |
| 61 | { |
| 62 | printk(BIOS_DEBUG, "PM1_STS: "); |
| 63 | if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); |
| 64 | if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); |
| 65 | if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); |
| 66 | if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); |
| 67 | if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); |
| 68 | if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); |
| 69 | if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); |
| 70 | if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); |
| 71 | printk(BIOS_DEBUG, "\n"); |
| 72 | } |
| 73 | |
| 74 | /** |
| 75 | * @brief read and clear SMI_STS |
| 76 | * @return SMI_STS register |
| 77 | */ |
| 78 | static u32 reset_smi_status(void) |
| 79 | { |
| 80 | u32 reg32; |
| 81 | |
| 82 | reg32 = inl(pmbase + SMI_STS); |
| 83 | /* set status bits are cleared by writing 1 to them */ |
| 84 | outl(reg32, pmbase + SMI_STS); |
| 85 | |
| 86 | return reg32; |
| 87 | } |
| 88 | |
| 89 | static void dump_smi_status(u32 smi_sts) |
| 90 | { |
| 91 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 92 | if (smi_sts & (1 << 27)) printk(BIOS_DEBUG, "GPIO_UNLOCK "); |
| 93 | if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); |
| 94 | if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); |
| 95 | if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); |
| 96 | if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); |
| 97 | if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); |
| 98 | if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); |
| 99 | if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); |
| 100 | if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); |
| 101 | if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); |
| 102 | if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); |
| 103 | if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); |
| 104 | if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); |
| 105 | if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); |
| 106 | if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); |
| 107 | if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); |
| 108 | if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); |
| 109 | if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); |
| 110 | if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); |
| 111 | if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); |
| 112 | printk(BIOS_DEBUG, "\n"); |
| 113 | } |
| 114 | |
| 115 | |
| 116 | /** |
| 117 | * @brief read and clear GPE0_STS |
| 118 | * @return GPE0_STS register |
| 119 | */ |
| 120 | static u64 reset_gpe0_status(void) |
| 121 | { |
| 122 | u32 reg_h, reg_l; |
| 123 | |
| 124 | reg_l = inl(pmbase + GPE0_STS); |
| 125 | reg_h = inl(pmbase + GPE0_STS + 4); |
| 126 | /* set status bits are cleared by writing 1 to them */ |
| 127 | outl(reg_l, pmbase + GPE0_STS); |
| 128 | outl(reg_h, pmbase + GPE0_STS + 4); |
| 129 | |
| 130 | return (((u64)reg_h) << 32) | reg_l; |
| 131 | } |
| 132 | |
| 133 | static void dump_gpe0_status(u64 gpe0_sts) |
| 134 | { |
| 135 | int i; |
| 136 | printk(BIOS_DEBUG, "GPE0_STS: "); |
| 137 | if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 "); |
Konstantin Aladyshev | 62f8083 | 2013-03-07 04:04:27 +0400 | [diff] [blame] | 138 | for (i=31; i>= 16; i--) { |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 139 | if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); |
| 140 | } |
| 141 | if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); |
| 142 | if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); |
| 143 | if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); |
| 144 | if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); |
| 145 | if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); |
| 146 | if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); |
| 147 | if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); |
| 148 | if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); |
| 149 | if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); |
| 150 | if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 "); |
| 151 | if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); |
| 152 | if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); |
| 153 | if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); |
| 154 | if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG "); |
| 155 | if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); |
| 156 | printk(BIOS_DEBUG, "\n"); |
| 157 | } |
| 158 | |
| 159 | |
| 160 | /** |
| 161 | * @brief read and clear ALT_GP_SMI_STS |
| 162 | * @return ALT_GP_SMI_STS register |
| 163 | */ |
| 164 | static u16 reset_alt_gp_smi_status(void) |
| 165 | { |
| 166 | u16 reg16; |
| 167 | |
| 168 | reg16 = inl(pmbase + ALT_GP_SMI_STS); |
| 169 | /* set status bits are cleared by writing 1 to them */ |
| 170 | outl(reg16, pmbase + ALT_GP_SMI_STS); |
| 171 | |
| 172 | return reg16; |
| 173 | } |
| 174 | |
| 175 | static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) |
| 176 | { |
| 177 | int i; |
| 178 | printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); |
Konstantin Aladyshev | 62f8083 | 2013-03-07 04:04:27 +0400 | [diff] [blame] | 179 | for (i=15; i>= 0; i--) { |
Konstantin Aladyshev | 07c3fc0 | 2013-03-07 04:37:02 +0400 | [diff] [blame] | 180 | if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 181 | } |
| 182 | printk(BIOS_DEBUG, "\n"); |
| 183 | } |
| 184 | |
| 185 | |
| 186 | |
| 187 | /** |
| 188 | * @brief read and clear TCOx_STS |
| 189 | * @return TCOx_STS registers |
| 190 | */ |
| 191 | static u32 reset_tco_status(void) |
| 192 | { |
| 193 | u32 tcobase = pmbase + 0x60; |
| 194 | u32 reg32; |
| 195 | |
| 196 | reg32 = inl(tcobase + 0x04); |
| 197 | /* set status bits are cleared by writing 1 to them */ |
| 198 | outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS |
| 199 | if (reg32 & (1 << 18)) |
| 200 | outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS |
| 201 | |
| 202 | return reg32; |
| 203 | } |
| 204 | |
| 205 | |
| 206 | static void dump_tco_status(u32 tco_sts) |
| 207 | { |
| 208 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 209 | if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); |
| 210 | if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); |
| 211 | if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); |
| 212 | if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); |
| 213 | if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); |
| 214 | if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); |
| 215 | if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); |
| 216 | if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); |
| 217 | if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); |
| 218 | if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); |
| 219 | if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); |
| 220 | if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); |
| 221 | if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); |
| 222 | printk(BIOS_DEBUG, "\n"); |
| 223 | } |
| 224 | |
| 225 | |
| 226 | /** |
| 227 | * @brief Set the EOS bit |
| 228 | */ |
| 229 | static void smi_set_eos(void) |
| 230 | { |
| 231 | u8 reg8; |
| 232 | |
| 233 | reg8 = inb(pmbase + SMI_EN); |
| 234 | reg8 |= EOS; |
| 235 | outb(reg8, pmbase + SMI_EN); |
| 236 | } |
| 237 | |
| 238 | extern uint8_t smm_relocation_start, smm_relocation_end; |
| 239 | |
| 240 | static void smm_relocate(void) |
| 241 | { |
| 242 | u32 smi_en; |
| 243 | u16 pm1_en; |
| 244 | |
| 245 | printk(BIOS_DEBUG, "Initializing SMM handler..."); |
| 246 | |
| 247 | pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc; |
| 248 | printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); |
| 249 | |
| 250 | smi_en = inl(pmbase + SMI_EN); |
| 251 | if (smi_en & GBL_SMI_EN) { |
| 252 | printk(BIOS_INFO, "SMI# handler already enabled?\n"); |
| 253 | return; |
| 254 | } |
| 255 | |
| 256 | /* copy the SMM relocation code */ |
| 257 | memcpy((void *)0x38000, &smm_relocation_start, |
| 258 | &smm_relocation_end - &smm_relocation_start); |
| 259 | |
| 260 | printk(BIOS_DEBUG, "\n"); |
| 261 | dump_smi_status(reset_smi_status()); |
| 262 | dump_pm1_status(reset_pm1_status()); |
| 263 | dump_gpe0_status(reset_gpe0_status()); |
| 264 | dump_alt_gp_smi_status(reset_alt_gp_smi_status()); |
| 265 | dump_tco_status(reset_tco_status()); |
| 266 | |
| 267 | /* Enable SMI generation: |
| 268 | * - on TCO events |
| 269 | * - on APMC writes (io 0xb2) |
| 270 | * - on writes to GBL_RLS (bios commands) |
| 271 | * No SMIs: |
| 272 | * - on microcontroller writes (io 0x62/0x66) |
| 273 | */ |
| 274 | |
| 275 | smi_en = 0; /* reset SMI enables */ |
| 276 | |
| 277 | smi_en |= TCO_EN; |
| 278 | smi_en |= APMC_EN; |
| 279 | #if DEBUG_PERIODIC_SMIS |
| 280 | /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using |
| 281 | * periodic SMIs. |
| 282 | */ |
| 283 | smi_en |= PERIODIC_EN; |
| 284 | #endif |
| 285 | smi_en |= BIOS_EN; |
| 286 | |
| 287 | /* The following need to be on for SMIs to happen */ |
| 288 | smi_en |= EOS | GBL_SMI_EN; |
| 289 | |
| 290 | outl(smi_en, pmbase + SMI_EN); |
| 291 | |
| 292 | pm1_en = 0; |
| 293 | pm1_en |= PWRBTN_EN; |
| 294 | pm1_en |= GBL_EN; |
| 295 | outw(pm1_en, pmbase + PM1_EN); |
| 296 | |
| 297 | /** |
| 298 | * There are several methods of raising a controlled SMI# via |
| 299 | * software, among them: |
| 300 | * - Writes to io 0xb2 (APMC) |
| 301 | * - Writes to the Local Apic ICR with Delivery mode SMI. |
| 302 | * |
| 303 | * Using the local apic is a bit more tricky. According to |
| 304 | * AMD Family 11 Processor BKDG no destination shorthand must be |
| 305 | * used. |
| 306 | * The whole SMM initialization is quite a bit hardware specific, so |
| 307 | * I'm not too worried about the better of the methods at the moment |
| 308 | */ |
| 309 | |
| 310 | /* raise an SMI interrupt */ |
| 311 | printk(BIOS_SPEW, " ... raise SMI#\n"); |
| 312 | outb(0x00, 0xb2); |
| 313 | } |
| 314 | |
| 315 | static int smm_handler_copied = 0; |
| 316 | |
| 317 | static int is_wakeup(void) |
| 318 | { |
| 319 | device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); |
| 320 | |
| 321 | if (!dev0) |
| 322 | return 0; |
| 323 | |
| 324 | return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; |
| 325 | } |
| 326 | |
| 327 | static void smm_install(void) |
| 328 | { |
| 329 | /* The first CPU running this gets to copy the SMM handler. But not all |
| 330 | * of them. |
| 331 | */ |
| 332 | if (smm_handler_copied) |
| 333 | return; |
| 334 | smm_handler_copied = 1; |
| 335 | |
| 336 | |
| 337 | /* if we're resuming from S3, the SMM code is already in place, |
| 338 | * so don't copy it again to keep the current SMM state */ |
| 339 | |
| 340 | if (!is_wakeup()) { |
| 341 | /* enable the SMM memory window */ |
| 342 | pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, |
| 343 | D_OPEN | G_SMRAME | C_BASE_SEG); |
| 344 | |
| 345 | /* copy the real SMM handler */ |
| 346 | memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size); |
| 347 | wbinvd(); |
| 348 | } |
| 349 | |
| 350 | /* close the SMM memory window and enable normal SMM */ |
| 351 | pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, |
| 352 | G_SMRAME | C_BASE_SEG); |
| 353 | } |
| 354 | |
| 355 | void smm_init(void) |
| 356 | { |
| 357 | /* Put SMM code to 0xa0000 */ |
| 358 | smm_install(); |
| 359 | |
| 360 | /* Put relocation code to 0x38000 and relocate SMBASE */ |
| 361 | smm_relocate(); |
| 362 | |
| 363 | /* We're done. Make sure SMIs can happen! */ |
| 364 | smi_set_eos(); |
| 365 | } |
| 366 | |
| 367 | void smm_lock(void) |
| 368 | { |
| 369 | /* LOCK the SMM memory window and enable normal SMM. |
| 370 | * After running this function, only a full reset can |
| 371 | * make the SMM registers writable again. |
| 372 | */ |
| 373 | printk(BIOS_DEBUG, "Locking SMM.\n"); |
| 374 | pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, |
| 375 | D_LCK | G_SMRAME | C_BASE_SEG); |
| 376 | } |
| 377 | |
| 378 | void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |
| 379 | { |
| 380 | /* The GDT or coreboot table is going to live here. But a long time |
| 381 | * after we relocated the GNVS, so this is not troublesome. |
| 382 | */ |
| 383 | *(u32 *)0x500 = (u32)gnvs; |
| 384 | *(u32 *)0x504 = (u32)tcg; |
| 385 | *(u32 *)0x508 = (u32)smi1; |
| 386 | outb(APM_CNT_GNVS_UPDATE, 0xb2); |
| 387 | } |