Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Timothy Pearson | 58649b0 | 2015-04-05 18:03:15 -0500 | [diff] [blame] | 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 5 | * Copyright (C) 2008-2009 coresystems GmbH |
| 6 | * 2012 secunet Security Networks AG |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H |
| 19 | #define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H |
| 20 | |
| 21 | #ifndef __ACPI__ |
| 22 | #ifndef __ASSEMBLER__ |
| 23 | #include "chip.h" |
| 24 | #endif |
| 25 | #endif |
| 26 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 27 | #define DEFAULT_TBAR ((u8 *)0xfed1b000) |
| 28 | #ifndef __ACPI__ |
| 29 | #define DEFAULT_RCBA ((u8 *)0xfed1c000) |
| 30 | #else |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 31 | #define DEFAULT_RCBA 0xfed1c000 |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 32 | #endif |
| 33 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 34 | #if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) |
Gerd Hoffmann | b142a51 | 2013-09-17 09:49:02 +0200 | [diff] [blame] | 35 | /* |
| 36 | * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a |
| 37 | * non-conflicting address. No need to worry about speedstep, it |
| 38 | * is not supported by qemu and isn't enabled in the qemu config. |
| 39 | */ |
| 40 | # define DEFAULT_PMBASE 0x00000600 |
| 41 | #else |
| 42 | # define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ |
| 43 | #endif |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 44 | #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) |
| 45 | #define DEFAULT_GPIOBASE 0x00000580 |
| 46 | |
| 47 | |
| 48 | #define APM_CNT 0xb2 |
| 49 | |
| 50 | #define PM1_STS 0x00 |
| 51 | #define PWRBTN_STS (1 << 8) |
| 52 | #define RTC_STS (1 << 10) |
| 53 | #define PM1_EN 0x02 |
| 54 | #define PWRBTN_EN (1 << 8) |
| 55 | #define GBL_EN (1 << 5) |
| 56 | #define PM1_CNT 0x04 |
| 57 | #define SCI_EN (1 << 0) |
| 58 | #define PM_LV2 0x14 |
| 59 | #define PM_LV3 0x15 |
| 60 | #define PM_LV4 0x16 |
| 61 | #define PM_LV5 0x17 |
| 62 | #define PM_LV6 0x18 |
| 63 | #define GPE0_STS 0x20 |
| 64 | #define SMI_EN 0x30 |
| 65 | #define PERIODIC_EN (1 << 14) |
| 66 | #define TCO_EN (1 << 13) |
| 67 | #define APMC_EN (1 << 5) |
| 68 | #define BIOS_EN (1 << 2) |
| 69 | #define EOS (1 << 1) |
| 70 | #define GBL_SMI_EN (1 << 0) |
| 71 | #define SMI_STS 0x34 |
| 72 | #define ALT_GP_SMI_EN 0x38 |
| 73 | #define ALT_GP_SMI_STS 0x3a |
| 74 | |
| 75 | |
Timothy Pearson | 58649b0 | 2015-04-05 18:03:15 -0500 | [diff] [blame] | 76 | #define GP_IO_USE_SEL 0x00 |
| 77 | #define GP_IO_SEL 0x04 |
| 78 | #define GP_LVL 0x0c |
| 79 | #define GPO_BLINK 0x18 |
| 80 | #define GPI_INV 0x2c |
| 81 | #define GP_IO_USE_SEL2 0x30 |
| 82 | #define GP_IO_SEL2 0x34 |
| 83 | #define GP_LVL2 0x38 |
| 84 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 85 | #define DEBUG_PERIODIC_SMIS 0 |
| 86 | |
| 87 | #define MAINBOARD_POWER_OFF 0 |
| 88 | #define MAINBOARD_POWER_ON 1 |
| 89 | #define MAINBOARD_POWER_KEEP 2 |
| 90 | |
| 91 | #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 92 | #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| 93 | #endif |
| 94 | |
| 95 | |
| 96 | /* D31:F0 LPC bridge */ |
| 97 | #define D31F0_PMBASE 0x40 |
| 98 | #define D31F0_ACPI_CNTL 0x44 |
| 99 | #define D31F0_GPIO_BASE 0x48 |
| 100 | #define D31F0_GPIO_CNTL 0x4c |
| 101 | #define D31F0_PIRQA_ROUT 0x60 |
| 102 | #define D31F0_PIRQB_ROUT 0x61 |
| 103 | #define D31F0_PIRQC_ROUT 0x62 |
| 104 | #define D31F0_PIRQD_ROUT 0x63 |
| 105 | #define D31F0_SERIRQ_CNTL 0x64 |
| 106 | #define D31F0_PIRQE_ROUT 0x68 |
| 107 | #define D31F0_PIRQF_ROUT 0x69 |
| 108 | #define D31F0_PIRQG_ROUT 0x6a |
| 109 | #define D31F0_PIRQH_ROUT 0x6b |
| 110 | #define D31F0_LPC_IODEC 0x80 |
| 111 | #define D31F0_LPC_EN 0x82 |
| 112 | #define D31F0_GEN1_DEC 0x84 |
Vladimir Serbinenko | 9d2cb7c | 2014-08-10 21:56:41 +0200 | [diff] [blame] | 113 | #define D31F0_GEN2_DEC 0x88 |
| 114 | #define D31F0_GEN3_DEC 0x8c |
| 115 | #define D31F0_GEN4_DEC 0x90 |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 116 | #define D31F0_GEN_PMCON_1 0xa0 |
| 117 | #define D31F0_GEN_PMCON_3 0xa4 |
| 118 | #define D31F0_C5_EXIT_TIMING 0xa8 |
| 119 | #define D31F0_CxSTATE_CNF 0xa9 |
| 120 | #define D31F0_C4TIMING_CNT 0xaa |
| 121 | #define D31F0_GPIO_ROUT 0xb8 |
| 122 | #define D31F0_RCBA 0xf0 |
| 123 | |
| 124 | /* GEN_PMCON_3 bits */ |
| 125 | #define RTC_BATTERY_DEAD (1 << 2) |
| 126 | #define RTC_POWER_FAILED (1 << 1) |
| 127 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 128 | |
| 129 | |
| 130 | /* D31:F2 SATA */ |
| 131 | #define D31F2_IDE_TIM_PRI 0x40 |
| 132 | #define D31F2_IDE_TIM_SEC 0x42 |
| 133 | #define D31F2_SIDX 0xa0 |
| 134 | #define D31F2_SDAT 0xa4 |
| 135 | |
| 136 | |
| 137 | /* D30:F0 PCI-to-PCI bridge */ |
| 138 | #define D30F0_SMLT 0x1b |
| 139 | |
| 140 | |
| 141 | /* D28:F0-5 PCIe root ports */ |
| 142 | #define D28Fx_XCAP 0x42 |
| 143 | #define D28Fx_SLCAP 0x54 |
| 144 | |
| 145 | |
| 146 | #define SMBUS_IO_BASE 0x0400 |
| 147 | |
| 148 | /* PCI Configuration Space (D31:F3): SMBus */ |
| 149 | #define SMB_BASE 0x20 |
| 150 | #define HOSTC 0x40 |
| 151 | |
| 152 | /* HOSTC bits */ |
| 153 | #define I2C_EN (1 << 2) |
| 154 | #define SMB_SMI_EN (1 << 1) |
| 155 | #define HST_EN (1 << 0) |
| 156 | |
| 157 | /* SMBus I/O bits. */ |
| 158 | #define SMBHSTSTAT 0x0 |
| 159 | #define SMBHSTCTL 0x2 |
| 160 | #define SMBHSTCMD 0x3 |
| 161 | #define SMBXMITADD 0x4 |
| 162 | #define SMBHSTDAT0 0x5 |
| 163 | #define SMBHSTDAT1 0x6 |
| 164 | #define SMBBLKDAT 0x7 |
| 165 | #define SMBTRNSADD 0x9 |
| 166 | #define SMBSLVDATA 0xa |
| 167 | #define SMLINK_PIN_CTL 0xe |
| 168 | #define SMBUS_PIN_CTL 0xf |
| 169 | |
| 170 | #define SMBUS_TIMEOUT (10 * 1000 * 100) |
| 171 | |
| 172 | |
| 173 | #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) |
| 174 | #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) |
| 175 | #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) |
| 176 | |
| 177 | #define RCBA_V0CTL 0x0014 |
| 178 | #define RCBA_V1CAP 0x001c |
| 179 | #define RCBA_V1CTL 0x0020 |
| 180 | #define RCBA_V1STS 0x0026 |
| 181 | #define RCBA_PAT 0x0030 |
| 182 | #define RCBA_ESD 0x0104 |
| 183 | #define RCBA_ULD 0x0110 |
| 184 | #define RCBA_ULBA 0x0118 |
| 185 | #define RCBA_LCAP 0x01a4 |
| 186 | #define RCBA_LCTL 0x01a8 |
| 187 | #define RCBA_LSTS 0x01aa |
| 188 | #define RCBA_DMIC 0x0234 |
| 189 | #define RCBA_RPFN 0x0238 |
| 190 | #define RCBA_DMC 0x2010 |
| 191 | #define RCBA_HPTC 0x3404 |
| 192 | #define RCBA_BUC 0x3414 |
| 193 | #define RCBA_FD 0x3418 /* Function Disable, see below. */ |
| 194 | #define RCBA_CG 0x341c |
| 195 | #define RCBA_FDSW 0x3420 |
| 196 | #define RCBA_MAP 0x35f0 /* UHCI cotroller #6 remapping */ |
| 197 | |
| 198 | #define BUC_LAND (1 << 5) /* LAN */ |
| 199 | #define FD_SAD2 (1 << 25) /* SATA #2 */ |
| 200 | #define FD_TTD (1 << 24) /* Thermal Throttle */ |
| 201 | #define FD_PE6D (1 << 21) /* PCIe root port 6 */ |
| 202 | #define FD_PE5D (1 << 20) /* PCIe root port 5 */ |
| 203 | #define FD_PE4D (1 << 19) /* PCIe root port 4 */ |
| 204 | #define FD_PE3D (1 << 18) /* PCIe root port 3 */ |
| 205 | #define FD_PE2D (1 << 17) /* PCIe root port 2 */ |
| 206 | #define FD_PE1D (1 << 16) /* PCIe root port 1 */ |
| 207 | #define FD_EHCI1D (1 << 15) /* EHCI #1 */ |
| 208 | #define FD_LBD (1 << 14) /* LPC bridge */ |
| 209 | #define FD_EHCI2D (1 << 13) /* EHCI #2 */ |
| 210 | #define FD_U5D (1 << 12) /* UHCI #5 */ |
| 211 | #define FD_U4D (1 << 11) /* UHCI #4 */ |
| 212 | #define FD_U3D (1 << 10) /* UHCI #3 */ |
| 213 | #define FD_U2D (1 << 9) /* UHCI #2 */ |
| 214 | #define FD_U1D (1 << 8) /* UHCI #1 */ |
| 215 | #define FD_U6D (1 << 7) /* UHCI #6 */ |
| 216 | #define FD_HDAD (1 << 4) /* HD audio */ |
| 217 | #define FD_SD (1 << 3) /* SMBus */ |
| 218 | #define FD_SAD1 (1 << 2) /* SATA #1 */ |
| 219 | |
| 220 | |
| 221 | #define SKPAD_ACPI_S3_MAGIC 0xcafed00d |
| 222 | #define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe |
| 223 | |
| 224 | |
| 225 | #ifndef __ACPI__ |
| 226 | #ifndef __ASSEMBLER__ |
| 227 | |
| 228 | static inline int lpc_is_mobile(const u16 devid) |
| 229 | { |
| 230 | return (devid == 0x2917) || (devid == 0x2919); |
| 231 | } |
| 232 | #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) |
| 233 | |
| 234 | #if defined(__PRE_RAM__) |
| 235 | void enable_smbus(void); |
| 236 | int smbus_read_byte(unsigned device, unsigned address); |
| 237 | void i82801ix_early_init(void); |
| 238 | void i82801ix_dmi_setup(void); |
| 239 | void i82801ix_dmi_poll_vc1(void); |
| 240 | #endif |
| 241 | |
| 242 | #endif |
| 243 | #endif |
| 244 | |
| 245 | #endif |