Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 17 | #ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H |
| 18 | #define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 19 | |
Stefan Reinauer | 83a1dd8 | 2010-03-28 15:11:56 +0000 | [diff] [blame] | 20 | #if !defined(__PRE_RAM__) |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 21 | #include "chip.h" |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 22 | extern void i82801bx_enable(device_t dev); |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 23 | #endif |
| 24 | |
Stefan Reinauer | 3f5f6d8 | 2013-05-07 20:35:29 +0200 | [diff] [blame] | 25 | #if defined(__PRE_RAM__) |
Uwe Hermann | 4028ce7 | 2010-12-07 19:16:07 +0000 | [diff] [blame] | 26 | void enable_smbus(void); |
| 27 | int smbus_read_byte(u8 device, u8 address); |
| 28 | #endif |
| 29 | |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 30 | #define SMBUS_IO_BASE 0x0f00 |
| 31 | #define PMBASE_ADDR 0x0400 |
| 32 | #define GPIO_BASE_ADDR 0x0500 |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 33 | |
| 34 | #define SECSTS 0x1e |
| 35 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 36 | #define PCI_DMA_CFG 0x90 |
| 37 | #define SERIRQ_CNTL 0x64 |
| 38 | #define GEN_CNTL 0xd0 |
| 39 | #define GEN_STS 0xd4 |
| 40 | #define RTC_CONF 0xd8 |
| 41 | #define GEN_PMCON_3 0xa4 |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 42 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 43 | #define PMBASE 0x40 |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 44 | #define ACPI_CNTL 0x44 |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 45 | #define ACPI_EN (1 << 4) |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 46 | #define BIOS_CNTL 0x4E |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 47 | #define GPIO_BASE 0x58 /* GPIO Base Address Register */ |
| 48 | #define GPIO_CNTL 0x5C /* GPIO Control Register */ |
| 49 | #define GPIO_EN (1 << 4) |
Joseph Smith | 68d8a56 | 2007-10-30 21:55:11 +0000 | [diff] [blame] | 50 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 51 | #define PIRQA_ROUT 0x60 |
Joseph Smith | 68d8a56 | 2007-10-30 21:55:11 +0000 | [diff] [blame] | 52 | #define PIRQB_ROUT 0x61 |
| 53 | #define PIRQC_ROUT 0x62 |
| 54 | #define PIRQD_ROUT 0x63 |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 55 | #define PIRQE_ROUT 0x68 |
Joseph Smith | 68d8a56 | 2007-10-30 21:55:11 +0000 | [diff] [blame] | 56 | #define PIRQF_ROUT 0x69 |
| 57 | #define PIRQG_ROUT 0x6A |
| 58 | #define PIRQH_ROUT 0x6B |
| 59 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 60 | #define FUNC_DIS 0xF2 |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 61 | |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 62 | #define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */ |
| 63 | #define LPC_EN 0xE6 /* LPC IF Enables Register */ |
| 64 | |
| 65 | // TODO: FDC_DEC etc |
Joseph Smith | 68d8a56 | 2007-10-30 21:55:11 +0000 | [diff] [blame] | 66 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 67 | #define SBUS_NUM 0x19 |
| 68 | #define SUB_BUS_NUM 0x1A |
| 69 | #define SMLT 0x1B |
| 70 | #define IOBASE 0x1C |
| 71 | #define IOLIM 0x1D |
| 72 | #define MEMBASE 0x20 |
| 73 | #define MEMLIM 0x22 |
| 74 | #define CNF 0x50 |
| 75 | #define MTT 0x70 |
| 76 | #define PCI_MAST_STS 0x82 |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 77 | |
Joseph Smith | 0dc5697 | 2008-04-06 04:26:19 +0000 | [diff] [blame] | 78 | #define TCOBASE 0x60 /* TCO Base Address Register */ |
| 79 | #define TCO1_CNT 0x08 /* TCO1 Control Register */ |
| 80 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 81 | /* GEN_PMCON_3 bits */ |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 82 | #define RTC_BATTERY_DEAD (1 << 2) |
| 83 | #define RTC_POWER_FAILED (1 << 1) |
| 84 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 85 | |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 86 | /* IDE Timing registers (IDE_TIM) */ |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 87 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 88 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 89 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 90 | /* IDE_TIM bits */ |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 91 | #define IDE_DECODE_ENABLE (1 << 15) |
| 92 | |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 93 | /* SMbus */ |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 94 | #define SMB_BASE 0x20 |
| 95 | #define HOSTC 0x40 |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 96 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 97 | /* HOSTC bits */ |
| 98 | #define I2C_EN (1 << 2) |
| 99 | #define SMB_SMI_EN (1 << 1) |
| 100 | #define HST_EN (1 << 0) |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 101 | |
Uwe Hermann | 0ea281f | 2010-10-11 21:38:49 +0000 | [diff] [blame] | 102 | /* SMBus I/O registers. */ |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 103 | #define SMBHSTSTAT 0x0 |
| 104 | #define SMBHSTCTL 0x2 |
| 105 | #define SMBHSTCMD 0x3 |
| 106 | #define SMBXMITADD 0x4 |
| 107 | #define SMBHSTDAT0 0x5 |
| 108 | #define SMBHSTDAT1 0x6 |
| 109 | #define SMBBLKDAT 0x7 |
| 110 | #define SMBTRNSADD 0x9 |
| 111 | #define SMBSLVDATA 0xa |
| 112 | #define SMLINK_PIN_CTL 0xe |
| 113 | #define SMBUS_PIN_CTL 0xf |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 114 | |
Uwe Hermann | dfb3c13 | 2007-06-19 22:47:11 +0000 | [diff] [blame] | 115 | #define SMBUS_TIMEOUT (10 * 1000 * 100) |
Corey Osgood | e99bd10 | 2007-06-14 06:10:57 +0000 | [diff] [blame] | 116 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 117 | #endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */ |