Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef _RANGELEY_PCI_DEVS_H_ |
| 18 | #define _RANGELEY_PCI_DEVS_H_ |
| 19 | |
| 20 | #define BUS0 0 |
| 21 | |
| 22 | /* All these devices live on bus 0 with the associated device and function */ |
| 23 | #define DEV_FUNC(x,y) ((x<<3) | y) |
| 24 | |
| 25 | /* Host Bridge */ |
| 26 | #define SOC_DEV 0x0 |
| 27 | #define SOC_FUNC 0 |
| 28 | # define SOC_DEVID 0x1f08 |
| 29 | # define SOC_DEV_FUNC DEV_FUNC(SOC_DEV,SOC_FUNC) |
| 30 | |
| 31 | /* PCIE Port 1 */ |
| 32 | #define PCIE_PORT1_DEV 0x1 |
| 33 | #define PCIE_PORT1_FUNC 0 |
| 34 | # define PCIE_PORT1_DEVID 0x1f10 |
| 35 | # define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) |
| 36 | |
| 37 | /* PCIE Port 2 */ |
| 38 | #define PCIE_PORT2_DEV 0x2 |
| 39 | #define PCIE_PORT2_FUNC 0 |
| 40 | # define PCIE_PORT2_DEVID 0x1f11 |
| 41 | # define PCIE_PORT2_DEV_FUNC DEV_FUNC(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) |
| 42 | |
| 43 | /* PCIE Port 3 */ |
| 44 | #define PCIE_PORT3_DEV 0x3 |
| 45 | #define PCIE_PORT3_FUNC 0 |
| 46 | # define PCIE_PORT3_DEVID 0x1f12 |
| 47 | # define PCIE_PORT3_DEV_FUNC DEV_FUNC(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) |
| 48 | |
| 49 | /* PCIE Port 4 */ |
| 50 | #define PCIE_PORT4_DEV 0x4 |
| 51 | #define PCIE_PORT4_FUNC 0 |
| 52 | # define PCIE_PORT4_DEVID 0x1f13 |
| 53 | # define PCIE_PORT4_DEV_FUNC DEV_FUNC(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) |
| 54 | |
| 55 | /* Host Bridge, Fabric, and RAS Registers */ |
| 56 | #define HOST_BRIDGE_DEV 0xe |
| 57 | #define HOST_BRIDGE_FUNC 0 |
| 58 | # define HOST_BRIDGE_DEVID 0x1f14 |
| 59 | # define HOST_BRIDGE_DEV_FUNC DEV_FUNC(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) |
| 60 | |
| 61 | /* Root Complex Event Collector (RCEC) */ |
| 62 | #define RCEC_DEV 0xf |
| 63 | #define RCEC_FUNC 0 |
| 64 | # define RCEC_DEVID 0x1f16 |
| 65 | # define RCEC_DEV_FUNC DEV_FUNC(RCEC_DEV,RCEC_FUNC) |
| 66 | |
| 67 | /* SMBus 2.0 1 */ |
| 68 | #define SMBUS1_DEV 0x13 |
| 69 | #define SMBUS1_FUNC 0 |
| 70 | # define SMBUS1_DEVID 0x1f15 |
| 71 | # define SMBUS1_DEV_FUNC DEV_FUNC(SMBUS1_DEV,SMBUS1_FUNC) |
| 72 | |
| 73 | /* Gigabit Ethernet (GbE) */ |
| 74 | #define GBE_DEV 0x14 |
| 75 | #define GBE_DEVID 0x1f41 |
| 76 | #define GBE1_DEV GBE_DEV |
| 77 | #define GBE1_FUNC 0 |
| 78 | # define GBE1_DEVID GBE_DEVID |
| 79 | # define GBE1_DEV_FUNC DEV_FUNC(GBE1_DEV,GBE1_FUNC) |
| 80 | #define GBE2_DEV GBE_DEV |
| 81 | #define GBE2_FUNC 1 |
| 82 | # define GBE2_DEVID GBE_DEVID |
| 83 | # define GBE2_DEV_FUNC DEV_FUNC(GBE2_DEV,GBE2_FUNC) |
| 84 | #define GBE3_DEV GBE_DEV |
| 85 | #define GBE3_FUNC 2 |
| 86 | # define GBE3_DEVID GBE_DEVID |
| 87 | # define GBE3_DEV_FUNC DEV_FUNC(GBE3_DEV,GBE3_FUNC) |
| 88 | #define GBE4_DEV GBE_DEV |
| 89 | #define GBE4_FUNC 3 |
| 90 | # define GBE4_DEVID GBE_DEVID |
| 91 | # define GBE4_DEV_FUNC DEV_FUNC(GBE4_DEV,GBE4_FUNC) |
| 92 | |
| 93 | /* USB 2.0 */ |
| 94 | #define USB2_DEV 0x16 |
| 95 | #define USB2_FUNC 0 |
| 96 | # define USB2_DEVID 0x1f2c |
| 97 | # define USB2_DEV_FUNC DEV_FUNC(USB2_DEV,USB2_FUNC) |
| 98 | |
| 99 | /* SATA Gen 2 */ |
| 100 | #define SATA2_DEV 0x17 |
| 101 | #define SATA2_FUNC 0 |
| 102 | # define SATA2_DEVID 0x1f22 |
| 103 | # define SATA2_DEV_FUNC DEV_FUNC(SATA2_DEV,SATA2_FUNC) |
| 104 | |
| 105 | /* SATA Gen 3 */ |
| 106 | #define SATA3_DEV 0x18 |
| 107 | #define SATA3_FUNC 0 |
| 108 | # define SATA3_DEVID 0x1f32 |
| 109 | # define SATA3_DEV_FUNC DEV_FUNC(SATA3_DEV,SATA3_FUNC) |
| 110 | |
| 111 | /* Platform Control Unit (PCU) */ |
| 112 | #define PCU_DEV 0x1f |
| 113 | |
| 114 | /* Low Pin Count (LPC/ISA) */ |
| 115 | #define LPC_DEV PCU_DEV |
| 116 | #define LPC_FUNC 0 |
| 117 | # define LPC_DEVID 0x1f38 |
| 118 | # define LPC_DEV_FUNC DEV_FUNC(LPC_DEV,LPC_FUNC) |
| 119 | # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) |
| 120 | |
| 121 | /* SMBus 2.0 0 */ |
| 122 | #define SMBUS0_DEV PCU_DEV |
| 123 | #define SMBUS0_FUNC 3 |
| 124 | # define SMBUS0_DEVID 0x1f3c |
| 125 | # define SMBUS0_DEV_FUNC DEV_FUNC(SMBUS0_DEV,SMBUS0_FUNC) |
| 126 | |
| 127 | /* Intel QuickAssist Integrated Accelerator (IQIA) */ |
| 128 | #define IQAT_DEV 0xb |
| 129 | #define IQAT_FUNC 0 |
| 130 | # define IQAT_DEVID 0x1f18 |
| 131 | # define IQAT_DEV_FUNC DEV_FUNC(IQAT_DEV,IQAT_FUNC) |
| 132 | |
| 133 | #endif /* _RANGELEY_PCI_DEVS_H_ */ |