Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <pc80/mc146818rtc.h> |
| 23 | #include <pc80/isa-dma.h> |
| 24 | #include <pc80/i8259.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <arch/ioapic.h> |
| 27 | #include <arch/acpi.h> |
| 28 | #include <cpu/cpu.h> |
| 29 | #include <elog.h> |
| 30 | #include <string.h> |
| 31 | #include <cbmem.h> |
| 32 | #include <arch/acpi.h> |
| 33 | #include <arch/acpigen.h> |
| 34 | #include "soc.h" |
| 35 | #include "irq.h" |
| 36 | #include "nvs.h" |
| 37 | |
| 38 | #define NMI_OFF 0 |
| 39 | |
| 40 | #define ENABLE_ACPI_MODE_IN_COREBOOT 0 |
| 41 | #define TEST_SMM_FLASH_LOCKDOWN 0 |
| 42 | |
| 43 | typedef struct southbridge_intel_fsp_rangeley_config config_t; |
| 44 | |
| 45 | static void soc_enable_apic(struct device *dev) |
| 46 | { |
| 47 | int i; |
| 48 | u32 reg32; |
| 49 | volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); |
| 50 | volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); |
| 51 | u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); |
| 52 | |
| 53 | /* |
| 54 | * Enable ACPI I/O and power management. |
| 55 | * Set SCI IRQ to IRQ9 |
| 56 | */ |
| 57 | write32(ilb_base + ILB_OIC, 0x100); /* AEN */ |
| 58 | reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ |
| 59 | write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ |
| 60 | |
| 61 | *ioapic_index = 0; |
| 62 | *ioapic_data = (1 << 25); |
| 63 | |
| 64 | /* Affirm full set of redirection table entries ("write once") */ |
| 65 | *ioapic_index = 1; |
| 66 | reg32 = *ioapic_data; |
| 67 | *ioapic_index = 1; |
| 68 | *ioapic_data = reg32; |
| 69 | |
| 70 | *ioapic_index = 0; |
| 71 | reg32 = *ioapic_data; |
| 72 | printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); |
| 73 | if (reg32 != (1 << 25)) |
| 74 | die("APIC Error\n"); |
| 75 | |
| 76 | printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); |
| 77 | for (i=0; i<3; i++) { |
| 78 | *ioapic_index = i; |
| 79 | printk(BIOS_SPEW, " reg 0x%04x:", i); |
| 80 | reg32 = *ioapic_data; |
| 81 | printk(BIOS_SPEW, " 0x%08x\n", reg32); |
| 82 | } |
| 83 | |
| 84 | *ioapic_index = 3; /* Select Boot Configuration register. */ |
| 85 | *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ |
| 86 | } |
| 87 | |
| 88 | static void soc_enable_serial_irqs(struct device *dev) |
| 89 | { |
| 90 | u8 *ibase; |
| 91 | |
| 92 | ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); |
| 93 | |
| 94 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 95 | write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); |
| 96 | |
| 97 | #if !CONFIG_SERIRQ_CONTINUOUS_MODE |
| 98 | write8(ibase + ILB_SERIRQ_CNTL, 0); |
| 99 | #endif |
| 100 | } |
| 101 | |
| 102 | /* |
| 103 | * Write PCI config space IRQ assignments. PCI devices have the INT_LINE |
| 104 | * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing |
| 105 | * information to operating systems and drivers. The INT_PIN register is |
| 106 | * generally read only and reports which interrupt pin A - D it uses. The |
| 107 | * INT_LINE register is configurable and reports which IRQ (generally the |
| 108 | * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling |
| 109 | * on devices that are downstream on a PCI bridge into account. |
| 110 | * |
| 111 | * This function will loop through all enabled PCI devices and program the |
| 112 | * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it |
| 113 | * uses. It then configures each interrupt in the pic to be level triggered. |
| 114 | */ |
| 115 | static void write_pci_config_irqs(void) |
| 116 | { |
| 117 | device_t irq_dev; |
| 118 | device_t targ_dev; |
| 119 | uint8_t int_line = 0; |
| 120 | uint8_t original_int_pin = 0; |
| 121 | uint8_t new_int_pin = 0; |
| 122 | uint16_t current_bdf = 0; |
| 123 | uint16_t parent_bdf = 0; |
| 124 | uint8_t pirq = 0; |
| 125 | uint8_t device_num = 0; |
| 126 | const struct rangeley_irq_route *ir = &global_rangeley_irq_route; |
| 127 | |
| 128 | if (ir == NULL) { |
| 129 | printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" |
| 130 | " 'global_rangeley_irq_route' structure does not exist\n"); |
| 131 | return; |
| 132 | } |
| 133 | |
| 134 | /* |
| 135 | * Loop through all enabled devices and program their |
| 136 | * INT_LINE, INT_PIN registers from values taken from |
| 137 | * the Interrupt Route registers in the ILB |
| 138 | */ |
| 139 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); |
| 140 | for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 141 | |
| 142 | if ((irq_dev->path.type != DEVICE_PATH_PCI) || |
| 143 | (!irq_dev->enabled)) |
| 144 | continue; |
| 145 | |
| 146 | current_bdf = irq_dev->path.pci.devfn | |
| 147 | irq_dev->bus->secondary << 8; |
| 148 | |
| 149 | /* |
| 150 | * Step 1: Get the INT_PIN and device structure to look for |
| 151 | * in the pirq_data table defined in the mainboard directory. |
| 152 | */ |
| 153 | targ_dev = NULL; |
| 154 | new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); |
| 155 | if (targ_dev == NULL || new_int_pin < 1) |
| 156 | continue; |
| 157 | |
| 158 | /* Get the original INT_PIN for record keeping */ |
| 159 | original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 160 | |
| 161 | parent_bdf = targ_dev->path.pci.devfn |
| 162 | | targ_dev->bus->secondary << 8; |
| 163 | device_num = PCI_SLOT(parent_bdf); |
| 164 | |
| 165 | if (ir->pcidev[device_num] == 0) { |
| 166 | printk(BIOS_WARNING, |
| 167 | "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", |
| 168 | device_num); |
| 169 | continue; |
| 170 | } |
| 171 | |
| 172 | /* Find the PIRQ that is attached to the INT_PIN this device uses */ |
| 173 | pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; |
| 174 | |
| 175 | /* Get the INT_LINE this device/function will use */ |
| 176 | int_line = ir->pic[pirq]; |
| 177 | |
| 178 | if (int_line != PIRQ_PIC_IRQDISABLE) { |
| 179 | /* Set this IRQ to level triggered since it is used by a PCI device */ |
| 180 | i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); |
| 181 | /* Set the Interrupt Line register in PCI config space */ |
| 182 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 183 | } else { |
| 184 | /* Set the Interrupt line register as "unknown or unused" */ |
| 185 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, |
| 186 | PIRQ_PIC_UNKNOWN_UNUSED); |
| 187 | } |
| 188 | |
| 189 | printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", |
| 190 | original_int_pin, pin_to_str(original_int_pin)); |
| 191 | if (parent_bdf != current_bdf) |
| 192 | printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", |
| 193 | new_int_pin, pin_to_str(new_int_pin)); |
| 194 | printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" |
| 195 | "\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 196 | 'A' + pirq, int_line, int_line); |
| 197 | } |
| 198 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); |
| 199 | } |
| 200 | |
| 201 | static void soc_pirq_init(device_t dev) |
| 202 | { |
| 203 | int i, j; |
| 204 | int pirq; |
| 205 | u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); |
| 206 | u8 *pr_base = ibase + 0x08; |
| 207 | u16 *ir_base = (u16 *)(ibase + 0x20); |
| 208 | u32 *actl = (u32 *)ibase; |
| 209 | const struct rangeley_irq_route *ir = &global_rangeley_irq_route; |
| 210 | |
| 211 | /* Set up the PIRQ PIC routing based on static config. */ |
| 212 | printk(BIOS_SPEW, "Start writing IRQ assignments\n" |
| 213 | "PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n" |
| 214 | "IRQ "); |
| 215 | for (i = 0; i < NUM_PIRQS; i++) { |
| 216 | write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]); |
| 217 | printk(BIOS_SPEW, "\t%d", ir->pic[i]); |
| 218 | } |
| 219 | printk(BIOS_SPEW, "\n\n"); |
| 220 | |
| 221 | /* Set up the per device PIRQ routing based on static config. */ |
| 222 | printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" |
| 223 | "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); |
| 224 | for (i = 0; i < NUM_OF_PCI_DEVS; i++) { |
| 225 | write16(ir_base + i, ir->pcidev[i]); |
| 226 | |
| 227 | /* If the entry is more than just 0, print it out */ |
| 228 | if(ir->pcidev[i]) { |
| 229 | printk(BIOS_SPEW, " %d: ", i); |
| 230 | for (j = 0; j < 4; j++) { |
| 231 | pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; |
| 232 | printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); |
| 233 | } |
| 234 | printk(BIOS_SPEW, "\n"); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | /* Route SCI to IRQ9 */ |
| 239 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
| 240 | printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); |
| 241 | |
| 242 | /* Write IRQ assignments to PCI config space */ |
| 243 | write_pci_config_irqs(); |
| 244 | } |
| 245 | |
| 246 | static void soc_power_options(device_t dev) |
| 247 | { |
| 248 | u8 reg8; |
| 249 | u16 pmbase; |
| 250 | u32 reg32; |
| 251 | |
| 252 | /* Get the chip configuration */ |
| 253 | config_t *config = dev->chip_info; |
| 254 | |
| 255 | int nmi_option; |
| 256 | |
| 257 | /* Set up NMI on errors. */ |
| 258 | reg8 = inb(0x61); |
| 259 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 260 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 261 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 262 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 263 | outb(reg8, 0x61); |
| 264 | |
| 265 | reg8 = inb(0x70); |
| 266 | nmi_option = NMI_OFF; |
| 267 | get_option(&nmi_option, "nmi"); |
| 268 | if (nmi_option) { |
| 269 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 270 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 271 | } else { |
| 272 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
| 273 | reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
| 274 | } |
| 275 | outb(reg8, 0x70); |
| 276 | |
| 277 | pmbase = pci_read_config16(dev, ABASE) & ~0xf; |
| 278 | |
| 279 | outl(config->gpe0_en, pmbase + GPE0_EN); |
| 280 | outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); |
| 281 | |
| 282 | /* Set up power management block and determine sleep mode */ |
| 283 | reg32 = inl(pmbase + PM1_CNT); // PM1_CNT |
| 284 | reg32 &= ~(7 << 10); // SLP_TYP |
| 285 | reg32 |= (1 << 0); // SCI_EN |
| 286 | outl(reg32, pmbase + PM1_CNT); |
| 287 | } |
| 288 | |
| 289 | /* Disable the HPET, Clear the counter, and re-enable it. */ |
| 290 | static void enable_hpet(void) |
| 291 | { |
| 292 | write8((u8 *)HPET_GCFG, 0x00); |
| 293 | write32((u32 *)HPET_MCV, 0x00000000); |
| 294 | write32((u32 *)(HPET_MCV + 0x04), 0x00000000); |
| 295 | write8((u8 *)HPET_GCFG, 0x01); |
| 296 | } |
| 297 | |
| 298 | static void soc_disable_smm_only_flashing(struct device *dev) |
| 299 | { |
| 300 | u8 reg8; |
| 301 | |
| 302 | printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); |
| 303 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 304 | reg8 &= ~(1 << 5); |
| 305 | pci_write_config8(dev, 0xdc, reg8); |
| 306 | } |
| 307 | |
| 308 | static void lpc_init(struct device *dev) |
| 309 | { |
| 310 | printk(BIOS_DEBUG, "soc: lpc_init\n"); |
| 311 | |
| 312 | /* Set the value for PCI command register. */ |
| 313 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 314 | |
| 315 | /* IO APIC initialization. */ |
| 316 | soc_enable_apic(dev); |
| 317 | |
| 318 | soc_enable_serial_irqs(dev); |
| 319 | |
| 320 | /* Setup the PIRQ. */ |
| 321 | soc_pirq_init(dev); |
| 322 | |
| 323 | /* Setup power options. */ |
| 324 | soc_power_options(dev); |
| 325 | |
| 326 | /* Initialize power management */ |
| 327 | switch (soc_silicon_type()) { |
| 328 | case SOC_TYPE_RANGELEY: |
| 329 | break; |
| 330 | default: |
| 331 | printk(BIOS_DEBUG, "Unknown Chipset: 0x%04x\n", dev->device); |
| 332 | } |
| 333 | |
| 334 | /* Initialize ISA DMA. */ |
| 335 | isa_dma_init(); |
| 336 | |
| 337 | /* Initialize the High Precision Event Timers, if present. */ |
| 338 | enable_hpet(); |
| 339 | |
| 340 | setup_i8259(); |
| 341 | |
| 342 | /* Interrupt 9 should be level triggered (SCI) */ |
| 343 | i8259_configure_irq_trigger(9, 1); |
| 344 | |
| 345 | soc_disable_smm_only_flashing(dev); |
| 346 | } |
| 347 | |
| 348 | static void soc_lpc_read_resources(device_t dev) |
| 349 | { |
| 350 | struct resource *res; |
| 351 | config_t *config = dev->chip_info; |
| 352 | u8 io_index = 0; |
| 353 | |
| 354 | /* Get the normal PCI resources of this device. */ |
| 355 | pci_dev_read_resources(dev); |
| 356 | |
| 357 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 358 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 359 | res->base = 0; |
| 360 | res->size = 0x1000; |
| 361 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 362 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 363 | |
| 364 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 365 | res->base = 0xff800000; |
| 366 | res->size = 0x00800000; /* 8 MB for flash */ |
| 367 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 368 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 369 | |
| 370 | res = new_resource(dev, 3); /* IOAPIC */ |
| 371 | res->base = IO_APIC_ADDR; |
| 372 | res->size = 0x00001000; |
| 373 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 374 | |
| 375 | /* Set SOC IO decode ranges if required.*/ |
| 376 | if ((config->gen1_dec & 0xFFFC) > 0x1000) { |
| 377 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 378 | res->base = config->gen1_dec & 0xFFFC; |
| 379 | res->size = (config->gen1_dec >> 16) & 0xFC; |
| 380 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 381 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 382 | } |
| 383 | |
| 384 | if ((config->gen2_dec & 0xFFFC) > 0x1000) { |
| 385 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 386 | res->base = config->gen2_dec & 0xFFFC; |
| 387 | res->size = (config->gen2_dec >> 16) & 0xFC; |
| 388 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 389 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 390 | } |
| 391 | |
| 392 | if ((config->gen3_dec & 0xFFFC) > 0x1000) { |
| 393 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 394 | res->base = config->gen3_dec & 0xFFFC; |
| 395 | res->size = (config->gen3_dec >> 16) & 0xFC; |
| 396 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 397 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 398 | } |
| 399 | |
| 400 | if ((config->gen4_dec & 0xFFFC) > 0x1000) { |
| 401 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 402 | res->base = config->gen4_dec & 0xFFFC; |
| 403 | res->size = (config->gen4_dec >> 16) & 0xFC; |
| 404 | res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | |
| 405 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 406 | } |
| 407 | } |
| 408 | |
| 409 | static void soc_lpc_enable_resources(device_t dev) |
| 410 | { |
| 411 | return pci_dev_enable_resources(dev); |
| 412 | } |
| 413 | |
| 414 | static void soc_lpc_enable(device_t dev) |
| 415 | { |
| 416 | soc_enable(dev); |
| 417 | } |
| 418 | |
| 419 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 420 | { |
| 421 | if (!vendor || !device) { |
| 422 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 423 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 424 | } else { |
| 425 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 426 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | static void southbridge_inject_dsdt(device_t dev) |
| 431 | { |
| 432 | global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); |
| 433 | |
| 434 | if (gnvs) { |
| 435 | memset(gnvs, 0, sizeof(*gnvs)); |
| 436 | acpi_create_gnvs(gnvs); |
| 437 | acpi_save_gnvs((unsigned long)gnvs); |
| 438 | #if CONFIG_HAVE_SMI_HANDLER |
| 439 | /* And tell SMI about it */ |
| 440 | smm_setup_structures(gnvs, NULL, NULL); |
| 441 | #endif |
| 442 | |
| 443 | /* Add it to DSDT. */ |
| 444 | acpigen_write_scope("\\"); |
| 445 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 446 | acpigen_pop_len(); |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | static struct pci_operations pci_ops = { |
| 451 | .set_subsystem = set_subsystem, |
| 452 | }; |
| 453 | |
| 454 | static struct device_operations device_ops = { |
| 455 | .read_resources = soc_lpc_read_resources, |
| 456 | .set_resources = pci_dev_set_resources, |
| 457 | .enable_resources = soc_lpc_enable_resources, |
| 458 | .init = lpc_init, |
| 459 | .write_acpi_tables = acpi_write_hpet, |
| 460 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
| 461 | .enable = soc_lpc_enable, |
| 462 | .scan_bus = scan_lpc_bus, |
| 463 | .ops_pci = &pci_ops, |
| 464 | }; |
| 465 | |
| 466 | /* IDs for LPC device of Intel 89xx Series Chipset */ |
| 467 | static const unsigned short pci_device_ids[] = { 0x1F38, 0x1F39, 0x1F3A, 0x1F3B, |
| 468 | 0 }; |
| 469 | |
| 470 | static const struct pci_driver soc_lpc __pci_driver = { |
| 471 | .ops = &device_ops, |
| 472 | .vendor = PCI_VENDOR_ID_INTEL, |
| 473 | .devices = pci_device_ids, |
| 474 | }; |