| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef INTEL_RANGELEY_GPIO_H |
| 18 | #define INTEL_RANGELEY_GPIO_H |
| 19 | |
| 20 | #define GPIO_MODE_NATIVE 0 |
| 21 | #define GPIO_MODE_GPIO 1 |
| 22 | #define GPIO_MODE_NONE 1 |
| 23 | |
| 24 | #define GPIO_DIR_OUTPUT 0 |
| 25 | #define GPIO_DIR_INPUT 1 |
| 26 | |
| 27 | #define GPIO_LEVEL_LOW 0 |
| 28 | #define GPIO_LEVEL_HIGH 1 |
| 29 | |
| 30 | #define GPIO_TPE_DISABLE 0 |
| 31 | #define GPIO_TPE_ENABLE 1 |
| 32 | |
| 33 | #define GPIO_TNE_DISABLE 0 |
| 34 | #define GPIO_TNE_ENABLE 1 |
| 35 | |
| 36 | #define GPIO_TS_DISABLE 0 |
| 37 | #define GPIO_TS_ENABLE 1 |
| 38 | |
| 39 | #define GPIO_WE_DISABLE 0 |
| 40 | #define GPIO_WE_ENABLE 1 |
| 41 | |
| 42 | struct soc_gpio { |
| 43 | u32 gpio0 : 1; |
| 44 | u32 gpio1 : 1; |
| 45 | u32 gpio2 : 1; |
| 46 | u32 gpio3 : 1; |
| 47 | u32 gpio4 : 1; |
| 48 | u32 gpio5 : 1; |
| 49 | u32 gpio6 : 1; |
| 50 | u32 gpio7 : 1; |
| 51 | u32 gpio8 : 1; |
| 52 | u32 gpio9 : 1; |
| 53 | u32 gpio10 : 1; |
| 54 | u32 gpio11 : 1; |
| 55 | u32 gpio12 : 1; |
| 56 | u32 gpio13 : 1; |
| 57 | u32 gpio14 : 1; |
| 58 | u32 gpio15 : 1; |
| 59 | u32 gpio16 : 1; |
| 60 | u32 gpio17 : 1; |
| 61 | u32 gpio18 : 1; |
| 62 | u32 gpio19 : 1; |
| 63 | u32 gpio20 : 1; |
| 64 | u32 gpio21 : 1; |
| 65 | u32 gpio22 : 1; |
| 66 | u32 gpio23 : 1; |
| 67 | u32 gpio24 : 1; |
| 68 | u32 gpio25 : 1; |
| 69 | u32 gpio26 : 1; |
| 70 | u32 gpio27 : 1; |
| 71 | u32 gpio28 : 1; |
| 72 | u32 gpio29 : 1; |
| 73 | u32 gpio30 : 1; |
| 74 | u32 gpio31 : 1; |
| 75 | } __attribute__ ((packed)); |
| 76 | |
| 77 | struct soc_cfio { |
| 78 | u32 pad_conf_0; |
| 79 | u32 pad_conf_1; |
| 80 | u32 pad_val; |
| 81 | u32 pad_dft; |
| 82 | } __attribute__ ((packed)); |
| 83 | |
| 84 | struct soc_gpio_map { |
| 85 | /* GPIO core */ |
| 86 | struct { |
| 87 | const struct soc_gpio *mode; |
| 88 | const struct soc_gpio *direction; |
| 89 | const struct soc_gpio *level; |
| 90 | const struct soc_gpio *tpe; |
| 91 | const struct soc_gpio *tne; |
| 92 | const struct soc_gpio *ts; |
| 93 | const struct soc_cfio *cfio_init; |
| 94 | const u32 cfio_entrynum; |
| 95 | }core; |
| 96 | |
| 97 | /* GPIO SUS */ |
| 98 | struct { |
| 99 | const struct soc_gpio *mode; |
| 100 | const struct soc_gpio *direction; |
| 101 | const struct soc_gpio *level; |
| 102 | const struct soc_gpio *tpe; |
| 103 | const struct soc_gpio *tne; |
| 104 | const struct soc_gpio *ts; |
| 105 | const struct soc_gpio *we; |
| 106 | const struct soc_cfio *cfio_init; |
| 107 | const u32 cfio_entrynum; |
| 108 | }sus; |
| 109 | |
| 110 | |
| 111 | }; |
| 112 | |
| 113 | /* Configure GPIOs with mainboard provided settings */ |
| 114 | void setup_soc_gpios(const struct soc_gpio_map *gpio); |
| 115 | |
| 116 | /* Get GPIO pin value */ |
| 117 | int get_gpio(int gpio_num); |
| 118 | /* |
| 119 | * Get a number comprised of multiple GPIO values. gpio_num_array points to |
| 120 | * the array of GPIO pin numbers to scan, terminated by -1. |
| 121 | */ |
| 122 | unsigned get_gpios(const int *gpio_num_array); |
| 123 | |
| 124 | #endif |