Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
| 19 | #include <stdlib.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <pc80/mc146818rtc.h> |
| 24 | #include <version.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include "pci_devs.h" |
| 27 | #include "soc.h" |
| 28 | |
| 29 | static void rangeley_setup_bars(void) |
| 30 | { |
| 31 | /* Setting up Southbridge. */ |
| 32 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
| 33 | pci_write_config32(LPC_BDF, RCBA, (uintptr_t)DEFAULT_RCBA | RCBA_ENABLE); |
| 34 | pci_write_config32(LPC_BDF, ABASE, DEFAULT_ABASE | SET_BAR_ENABLE); |
| 35 | pci_write_config32(LPC_BDF, PBASE, DEFAULT_PBASE | SET_BAR_ENABLE); |
| 36 | printk(BIOS_DEBUG, " done.\n"); |
| 37 | |
| 38 | printk(BIOS_DEBUG, "Disabling Watchdog timer..."); |
| 39 | /* Disable the watchdog reboot and turn off the watchdog timer */ |
| 40 | write8((void *)(DEFAULT_PBASE + PMC_CFG), |
| 41 | read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger |
| 42 | outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | |
| 43 | TCO_TMR_HALT); // disable watchdog timer |
| 44 | |
| 45 | printk(BIOS_DEBUG, " done.\n"); |
| 46 | |
| 47 | } |
| 48 | |
| 49 | static void reset_rtc(void) |
| 50 | { |
| 51 | uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & |
| 52 | 0xfffffff0; |
| 53 | uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1)); |
| 54 | int rtc_failed = !!(gen_pmcon1 & RPS); |
| 55 | |
| 56 | if (rtc_failed) { |
| 57 | printk(BIOS_DEBUG, |
| 58 | "RTC Failure detected. Resetting Date to %s\n", |
| 59 | coreboot_dmi_date); |
| 60 | |
| 61 | /* Clear the power failure flag */ |
| 62 | write32((void *)(DEFAULT_PBASE + GEN_PMCON1), |
| 63 | gen_pmcon1 & ~RPS); |
| 64 | } |
| 65 | |
| 66 | cmos_init(rtc_failed); |
| 67 | } |
| 68 | |
| 69 | void rangeley_sb_early_initialization(void) |
| 70 | { |
| 71 | /* Setup all BARs required for early PCIe and raminit */ |
| 72 | rangeley_setup_bars(); |
| 73 | |
| 74 | reset_rtc(); |
| 75 | } |